Verify Setup issue

[victobui]

I am new to this I ahve installed the vscode exetension with all dependencies.
But when I verify setup it says there are errors in the checks, but shows me that all have passed.

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Checking general configuration (https://terostechnology.github.io/terosHDLdoc/docs/category/installation-checklist)
❌ Some checks failed ❌

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⊙ Checking make. This tool is used to run some external tools. Current configured installation path: ""
🔎 Searching for the binary "make" in the system path
✅ make Found in the system path using the command: "make --version"
🎉 The make installation path is correctly configured.

⊙ Checking Python installation. Configured installation path: ""
✅ Python was found in the path "python". Tried to find it using the command: "python -c "import sys; check_version = sys.version_info > (3,0); exit(0) if check_version == True else exit(-1)""
🎉 Python installation path is correctly configured.

⊙ Checking Python dependencies. Current configured installation path: ""
🎉 vunit found.
🎉 edalize found.
🎉 cocotb (optional) found.
🎉 vsg (optional) found.

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Checking Linter configuration (https://terostechnology.github.io/terosHDLdoc/docs/guides/linter)
🎉 Correctly configured 🎉🎉

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⊙ Linter errors for VHDL is disabled. Skipping configuration check.

⊙ Checking linter errors with modelsim for Verilog/SV. Current configured installation path: System path
🔎 Searching for the binary "Modelsim" in the system path
✅ Modelsim Found in the system path using the command: "vlog -version"
🎉 The linter installation path is correctly configured.

⊙ Checking linter style with vsg for VHDL. Current configured installation path: System path
🔎 Searching for the binary "Vsg" in the system path
✅ Vsg Found in the system path using the command: "vsg --version"
🎉 The linter installation path is correctly configured.

⊙ Linter style for Verilog/SV is disabled. Skipping configuration check.

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Checking External Tool Configuration (https://terostechnology.github.io/terosHDLdoc/docs/external_tools/)
🎉 Correctly configured 🎉🎉

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⊙ Selected external tool: GHDL. Installation path: ""
🔎 Searching for the binary "ghdl" in the system path
✅ ghdl Found in the system path using the command: "ghdl --version"
🎉 The GHDL installation path is correctly configured.

⊙ Execution mode: CMD. The tool will be executend in the command line.

⊙ Waveform viewer: TOOL. Built-in tool waveform viewer will be opened after the simulation if it is available.

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Checking Formatter configuration (https://terostechnology.github.io/terosHDLdoc/docs/guides/formatter)
🎉 Correctly configured 🎉🎉

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⊙ Checking formatter standalone for VHDL.
The formatter is built into TerosHDL. Skipping configuration check.
🎉 The linter installation path is correctly configured.

⊙ Checking formatter istyle for Verilog/SV.
The formatter is built into TerosHDL. Skipping configuration check.
🎉 The linter installation path is correctly configured.

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Checking Schematic configuration (https://terostechnology.github.io/terosHDLdoc/docs/guides/schematic_viewer/installation)
🎉 Correctly configured 🎉🎉

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⊙ Selected backend: yowasp with installation path: "". This backend doesn't support VHDL files.
🔎 Searching for the binary "yowasp" in the system path
✅ yowasp Found in the system path using the command: "yowasp-yosys --version"
🎉 The Schematic Backend installation path is correctly configured.

Could someone explain to me if there are skipped checks that are causing errors.