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Is your feature request related to a problem? Please describe.
There currently does not appear to be a way to create separate tables for groups of constants. All constants are currently put into one table. This applies to signals, types, etc.
Describe the solution you'd like
It would be very useful to be able to create separate tables for each group of constants, etc., similar to how @virtualbus allows groupings of ports together.
Describe alternatives you've considered
I tried using @virtualbus on the off chance that it would work for constants, but it did not. I suppose it is possible to separate groups into different VHDL files, but this would require jumping to different files for groups of constants, etc. that should probably belong in single file.
Additional context
Example of VHDL with two groups of constants put into single constant table in documentation.
library ieee;
use ieee.std_logic_1164.all;
entity constant_tables is
end entity constant_tables;
architecture behavioral of constant_tables is
--! Logic
constant ZERO : std_logic := '0'; --! zero
constant ONE : std_logic := '1'; --! one
--! Unknown
constant UNKNOWN : std_logic := 'U'; --! unknown
constant DRIVING_UNKNOWN : std_logic := 'X'; --! driving unknown
begin
end architecture behavioral;
The text was updated successfully, but these errors were encountered:
Is your feature request related to a problem? Please describe.
There currently does not appear to be a way to create separate tables for groups of constants. All constants are currently put into one table. This applies to signals, types, etc.
Describe the solution you'd like
It would be very useful to be able to create separate tables for each group of constants, etc., similar to how @virtualbus allows groupings of ports together.
Describe alternatives you've considered
I tried using @virtualbus on the off chance that it would work for constants, but it did not. I suppose it is possible to separate groups into different VHDL files, but this would require jumping to different files for groups of constants, etc. that should probably belong in single file.
Additional context
Example of VHDL with two groups of constants put into single constant table in documentation.
The text was updated successfully, but these errors were encountered: