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Use Sta::readVerilog and Sta::linkDesign in OpenROAD instead of dbReadVerilog and dbLinkDesign #6611

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eder-matheus opened this issue Jan 29, 2025 · 0 comments
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@eder-matheus eder-matheus self-assigned this Jan 29, 2025
@eder-matheus eder-matheus added the sta Static Timing Analysis label Jan 29, 2025
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