From 348f495a7894586d0b3f62e695430ca3328de10e Mon Sep 17 00:00:00 2001 From: Threetwosevensixseven Date: Mon, 20 Jan 2020 12:33:43 -0500 Subject: [PATCH] NXTP dot command now sets 115200 baud using a prescaler derived from the current video timing. --- docs/baud prescalar.xlsx | Bin 0 -> 16501 bytes docs/nextreg-TBBLUE.30007.SPRITES.txt | 772 ++++++++++++++++++++++++++ dot/NXTP | Bin 5994 -> 6196 bytes src/asm/constants.asm | 5 +- src/asm/esp.asm | 4 + src/asm/macros.asm | 1 - src/asm/main.asm | 62 ++- src/asm/msg.asm | 46 +- src/asm/vars.asm | 1 + src/asm/version.asm | 26 +- 10 files changed, 887 insertions(+), 30 deletions(-) create mode 100644 docs/baud prescalar.xlsx create mode 100644 docs/nextreg-TBBLUE.30007.SPRITES.txt diff --git a/docs/baud prescalar.xlsx b/docs/baud prescalar.xlsx new file mode 100644 index 0000000000000000000000000000000000000000..961a9cd7ea55aa347f8177ab2bcaef92d22c75a7 GIT binary patch literal 16501 zcmeIZ^J8U8v-rJZV`AI3ZF|CrF|ln;Y-?gql8J4b6Wg}^X3lf(d!A?Rxqrd;t{?W= zSXFCv@2;*-S63-WgMgv{zyXi|0DurM;GP`g1OxyOfCB)?07zghVH;~lV{1oU6*pUB z2W>i6D@%f0P+*E|0Px54|9AX9+ykQt+R{A?C_(37@4`dnwTomSgU#A9ZNL1kA$oTl zX{F<1;>S+cJ<_}gl-T>B-Df6A_Pw$^+j=gW=Z2tpROfcevToIZ#WX*sx{a@WojBx` zW`N8KtOvKR2Qu28x}CMHxATSij6JG>>F=?DV+>W-Im*SrqNJ`HF3{mU{yheU5rXgF z_N=j%%oobclx4y60rH#rQ4CLciHG!-Ah9&ra%iO5c%Vab91$X=F6M0y=_;p@3g*6^ z24^cFY`+$6TI@QUv(wL7)^?>BnQsX6xn!{Ib1ySbeZh6%Cyf#?1+-yO{?+yxGw?*0Z6$Jc^Yh7PF3E5lqaSCuGu@A4kj8o*0ndZxrOM($ z8^U10lja^T5aLoj;cBq5Yg7ufYdm|;2QUD@`#T6g;Xkak?lS}N&BqXw`7lP94{O!6 zH@0-3r~Cc-e^&bcuxb8V)63#y<$D-lgU%&hf(P$sS7Q)`q+J9hS_oCVeI-{A>LT+< zuva_CaS&Co0zkxl+Pq(emsfcrj|K_vwphx-kx;ma>s`u&lAr9HAgIXflf>-GHhVug z&)&}7rHV_rQ8>3nQ~hWx&XFEkCl;Hz6sba-pi{$wLN34wLgP*K)9jbkSTlI20Gbt2 zJ}nQbY+%nmil0dLnNKP_gyRq4lsTDBMICf7__|o(IcQ0E`-t^f*_6|)(je2Gi^xsa z$g=ZVB)tRq)st2(V^E2R1?holLVSQU`_@OZmgREfyIU_iRL_sWiy{AT{Nl9_$Mrvr zJ;YDw>6V{c(#V`K5#ot1sIvdQB>eDj`uh3IvGW;-t)q5{qR zQLFvgs{WaDdKifO0h;4$I@#yCcdr4Ge6tp=-DdPp*vmaV%*+$8$yv^_Ry<0Cm^R{M z&9*WD^XMtq89-dOLC1G`D#!KC{L;DB0tBULFYq~#=0 zQEVdmhoE}f>aAQt=p+NHk;v@)1k{4k5~~vqzg5J!G><@$jDRjRYSqaIbZud+I*3oT zWY7mAVOBf7b13_rtRg&)*grPLzzLGdOpZz*SR)H1D&}a>jWhz5xp%O+fz$v#JDtA4 z>|IkWYOH05U#=3H0j3`EPv74Mt3J7-`ma7?WCZUl`tvb;?;)oCm5}B!seK7?mF!d< zt_Y)Lf&KJSah$!I;xNpyE-fGi!nHVpAml!YAVRXd*fca(d5vmvv+L*j?8*aDWf3aG zH|&O+tSBhxZ(vWry80xdLP=La#lr_8yi7$yTR%YW(fvQV6eCQC?kx30!fK_Y!f2%v z{tBJl|6LY_6#X=jd_~tdi%{8R z=hGGV5kS*RLs!rs=DCel#J`=NTc2ZWd!c3p#Up87tO<2&dQi$RLw+SROEmQvB;%8y zlI?WK5djn&FB9)Oy7;^idjXjw+?k*?i=VT}B=E=*Gv;7{ohw1w@r5Y)o0J9MC-+y{bE-1|#Vk zp^1eWMqqeRb{PfmX?wiH&w)zoCVray*jBn&kdKp2Ia$YOWdX3fG9*v9TcsjPMGbQ~ z9tLpt;ubG+?(nG22H|p+t2%ffIsU)EP*O9Wcm@W$s_L`3Z#7E2!M&Jmaoom990{)F z&YqIc`w)RA`sRL(*q#NuB^9-gx4r>L-^H=dMrbhGEz^ue1JhuXcslPdk}8yl1WUb& zEjK)**lzQF+4<$N3p0-hSAl3i^NdWGRN&`Yrajl7S1-NJLZs^%-ODTIa+xAFv)>$x zMA!73**Vm$b5Lx2{!HGG8uh$+=)>F!a&F;XczNW-O{1Sa7G$(>Q6d;MOxx|RQ>7VcR{zODwi znglFJl~a3Js&nA*)*2$hzgClNJl7Ww3cl}j>HP;#pG-V%9l+-owq8+t`1rd;OLZA)JIC!}E*v_| zL&Nn~rVzp~DP4U;hQbhpL|LRzKiwd=FUVp;V!YTI%TOjVw1PWoXA;B)=!z>ERp?nBWWCLjNa+ zuwW0nBJ<%4_K5%hjK3X%gQ>BxqXYe4C&s@#gQiCGvKXv4{p33Vq-bpR;;ivVeY0~F zU+tYcE~u<~tGTfoZEwAbq({Ml4?QPyGlj-?6h?Pf(ko)loq;CL+mVsWY#uO4EU}_0 z^DjrGNEt7t*qM0!M>bh2;W?%GsV+eNsK&S7#j(Jmu~MV<>%Xr3Q}p zMhwJflzi}U+HRP_0+3r5MTe$FHYRoirMF2g>SYdHCuOu7>hjPtRiZXXm@uZS(Vx0_ zuJEI~D7OhDZ7-NE_*aAN((-Vf)4L#IuXwSlYqy{v=yr^V9t(Iv(n3iKi}lR)JO$tnYx z-m|2|Iy#x88IFDY7r`*#)wXzomaCo`j-!IkWE$woVpls3Qn`LD4A#@1ymdOFGq>!^ z-TM3*nq>=wHB^y8I_W>E+q4ubWot6Hz4pN1DM~z-+FSL3h4;$>)9X<{rI~o9c#80+ zcFhMdIQb5|dus?QX~Lv|vJTc_iG~C3ivZ-|jm8ItFJM`=Ca!^od&x^I03Piuc|*#< zh@V1v1IKvWjT0E)KOpslex1er6Ln3#V))#RgpPP5SY#2L`}{KI6^oZX;6gw8>`ouD z3jF)&F^_~7g*W8U^hqAKw<7@Z;io-pY@b5w8Vr7rZTjiJ5x~&3kL#>t*ek}Q0t5J+ z@f*eahEh=H76k(yEZE!o==yTVuHMFe#uZhT+L6Rzo>ZVzenxp8+OlDws}d zK;0HfLdGn}b&E}Olxt8HMnc-pDq>h{R0(e2wzdTPm- z55t;{88?gG9Zj6M_1d1kG1N>ty~&>a<$ik8quk+cY4aJ9c7rVX&FJCLYr3u)`-r>^ zny+5FR}riO3J71bbLX2P24 zn)5W2z!W~NBY4osLH)iv?ma+N!m4?TeAN6qbgR2`n>|=Uk+=&uKfYI|&c_71;lJoaK}i1s4Ig2Wcmup(}Tgsi%7xtG}#=6j9lXmA|o%byRV zD73y{?i;-z4od@W?2oO&V+ue4%V|8anz-tc2Q`sELF-HqYxb`-B)yy1A%Kr>r2&;z z;GmOyFduJTk7hv4Q%P)l5|4LGSz=`o8d@#kL5GI=&9~*`8DeaMm5W)l@(^j>I{bww zR%HpRGgIc+(2eR-1$BdS>w8HA=jtD-1%G7-v#k!>PULeK9WW@&o+eS}&~Ws^R5Dsg z0e*3cNHit@5OEA(v*F7~Zhqh}4PLC;dr`vIaaAS(itR$&ZOMUR90v2DR%~~#aSTq? z_GPob<4VL)Sx1s6sOkzLC7h8#m2{L)XjLhaV|%IR5J-v~6Owc#?@J2pm4V&M#F01% zAwlgzOX~d;CdY#EwT_bjB#@YKRmM%8lR(WUlS4(ps6`IqjjjCA6@c@`cU2FkhZ1!Ms%@@Lr{`3>}#scHoXe-Q|6_Y)jYC=sr z&Bpt)L%DM1z<^0<38Q(jHVmX_+nRMcv5@9--Apt6)aVUB!N1itA?dIIu>wH z7y&9EnOX=!4fQHFZ0n^l%<}u6b5s@s&d!IG+z6ufaTvDUOXxQr?V^q4arn3arx8-h zTm{fzsTFt;k*f)V>37Qy{d?-5VYrY{pDFha!Y#US@KlTJ-GF@^;Eba{1@57IK?Ur9 zC$|9H;m^?*-12}%FUq}*(lSQi6IiP-S*eznZQEXy;z%i#&74qQ$8^~+D*mmOkX7=>3Pcu*I`gk2xVm1w~` zj2>2Z91{E+MH2H*IYi%|zb|U@IZITf6A9rlaXOede;q$Lsj%^Wv*$6TS4`_0 zGRxJPFRTzPVp!}iDhho&mw%g;n6KvHunG{i4f&CmKq4qPv7h00Kb&nhqNyBk3Dg= z!=R13c*OW_4<9EMOaSp-;gMIF|q%Hfin|mi;=JQ5gTN-&hVfjQ%(|# z2TyNBw@e4oTvzGAut&Fu;V%r?W{|BmO4bFb?((vR_pywKB%p~++g9_hau>sD>&57V z9)9zn(|AQ1sp!n;fMTQQvTatn=UkJ!;SYMk+9MpiN6-E9oe7S1h_JE5{zyqAE+UwA4E%Ll8bvzAn^r@x3D~7eNP!XK=h+| z@K32`fY{95$Vqw~f7u9X+=2wydmsqGtkL-N}D8tn;!=1&Dy*{p*ntLE&l6RI7p&sI(iFE`^LpwF)mRw~)* z7mTvuus0Pjhh5iNz7LhMz_pejTNMu*!RzX@c~h>=mN$Y`|`PIAyo9d(Hz{UHZxwGd8UUthZ>8!~%qlh=dd z3zmj3(lH!FFSG{!*xl#nD%-;xTPS=fNF?q`jyY;$c5YWnQRkDCO|KX+Ep3|fD39>) zucJw4TF+SwP?lmtMx#fli7L@e#HPRSHF;ZzSf~eKJQr(QY*)Tj!muX9j>bxgH6C3m zN|0DY^gDc!&j$98hUQ}W0Fa;lC)^eEG5P|5*}m%}6h}o$&ciA6Ul@_d#IzL#d1WxQVUF^0}6>bdTWM%1)W5?j7dpD(~;M~YmG4w!~pawWV zom)ZDf==&Z+N@V)!24&-|(uUi;1 zLgI^EK@*>+D8k0OvQ^EBNK%Ad6v@roCD4s4mor=@LTLKd;rB28=u44Ihnemh%c&4n z;x>pSXrpbnM6BDG^c8ShVJ3ywAd^w?YT2cxfPudR%|AW(4(vNhDAZj5?7M+z2yoIX z$kyFQv>H8cYDWtGKp|>?1Wqm<4+Q`Pr`im_{^gM=SpAXJ?UU(Oh`9VH>R8a}BWwx( z=~WWKM|Na0YPKVzJOo_mIFSTAAtX%K;lN12QcoCp% zq7UXs^!Fy0Y;32JOoJ~&1vE?M0u*8cK|ffl14NQTjmkBY+O@s7{apCax+2EJOqCx{ zEz!dk436Cdd=K$J_@yfuy-CS}aWQjpJF~>@8{YUM^f0O#4F`FSY$~t-yBZ2Ws-l*o zQfcyh2YOy@M=Bh|0_+1!C;$mxa)3Tq>U;oIEHw=^l*u)^P!2QUtPqx07EN(u1jcOg zW2q!E96}bM0IsW(54(Eny230v>}uqus8FE@J~2Ibl?#}Z#RT&WW0HkXg?{>;u=!M) z@Bvh+zqtfhKok?H6He{zEMarBBtr5xfN=cs?c>E6laRT#-v9zE;Pzht629q@39x;Z8ue?Q$^dc>Vw>UyYL*9} z@KDGDz)5`n0+8uck5^Cuw|gQi=BfqAy~<^!*LWCD21<&*55-75i-~ zCK_ML4r`P3P45iezGEF{Y@L_dVBO`A4W*gZAmMiHxSc)(Tb*x>_<1jnuxi`;6t5UQ z-?YAB7{~S7ejW3sH_Xk7XOR!UsF=IIc(DMchYx4wJ|58J8``dX;*=S;14S|6=FEFx zjX!+<$Jm+YcFUvt2WCW3{jY%z=D#o_&B|s=3~^vx?Z~CFOgS+=Zi5`s4mk@r2mpmB zHy`Yh2trl`&rpXOr#ySUws^Z8bs8F)=Hc5p?&JK`#AogH>1brxnHYD4;O1qut}K(f zdgmtTP~=@cBHR89p!5r4L$t-*_H*vplr9C%8PYYCV8JPb@f{#^FDG>2zD^ zY+P6A(U7tMdYRqG%52`uO6IX@Gu{Y(_B;HsI9b|nv@iNh>vn?WI*%9?{TZVV%KNMT84GPqx(pBB>z(`A0M;8N268pB z#VC=G^TOWt`OL(D_FhBseN1$d7P6kHZ|hmbYmoYZFh=!k$!$?Y_jNw@n3q?aL3@dT zP8DPCDEKr;x>&;2v!X8bXnNfj^o8DvH$@ZCzx=viSGVo+jVEoxt;4JW*QBPqV~^

J|t)X0HP7IYkebE(;BQ1)LN z`p#J{TR8Ra6|Be|k>cEYi=Fs%#wPpZZUnwL@j-7q*BK)`Ety{I4@G*Ld$yaGyG0}r zG987BT^)UXB9ZRkSbqJfgs^1Ke3zrdR41x@QE=N|6aU0i>0Ro@ce)pa`bK=` zs!)F6o&NCnzE<~P6`07heAl-s-&#fwG5pE1yx?`04)eLEQ zb>Q^PeYwnKzwNT&aXy~=Rb{riwp(k;KvO&5zI#wKKGl?I*6m^Y1{Gq87ImYw*|X4H z$7Pn&C;P~{pIU8rKt1&qEVeu~rMx=77{9$0#LFrGr)rvrXL;v28(|vrVCJz+f!mhq;ML8KxLxF{Z1a6moM9a!*D+ z?%AN~XtU6~?c3QxuSPOi|9Abh0w#1jV_THHWU0Vz^Hh(XR(a#*YSNhLY)MH32lJE} zl?SD9y1jcLBt!|bzEu5jB~jP9La|S^{&boB4w`P(Dc3Sh4ADjXEd+(%@L{hBk?F?P zF|*oFqcLDwLH`7KwD^BGiu$3vqPX|@EQS!64Xonp*ZUIdfU z!iuvT&!_c0$J8%Q0E2TJVShfbR?AEO)VecC_B_;pIyvzGK|2PXU()YPl1dpwXEy9& z13}$XzirHAX0D(ko=>?Rfm>!xDPqV)zFp5bZV!xtskUpRGAaoaS%xSLPj1A|J%p(E zM#=K)G$?^-(lo@A9LDl4b5G!fb z9e=s2TsRlhI487|y>ijdabFGMm`68AU}_I>M6nx*n3fzTJ&*jPke2`u@w_bSS9g*% z4|Ky_QZB(m&$ z%|x~(B;=2*R2hX<7LzueTWv*4J9zeM${$`z4u<89(@K2Czn+xZT5y?cC^|lb(KnuA z5^xrRTXpCAjkX8~*cm}3ZL(90g|WG8SCQ%5VY}6 z;%Sy(VCbn7ctvE2UgK|$UTRMP&j_KQ#{5W9WyB_=E|v4Pjn6iBhkvjPtdst9>Xz&NpGWS!i*aW zqn1{~2WIIGQg0&xdd0V=leiJ+J|Ba<`Jo=Xm}RpcKuar8gJ4VC4{>EMqa)!NQ~2$s zN~`h!oXJdTJAj3DBk#mXByI0OfDmhjkP8prZitW`d0HA*RDFoGK;ol`VINJ*gTyV# zAo{C`g^*U#Nt^!lyqQECHNY|tZ85~-my611zR0+z>ko^w&pe9Y>>=c%@9)islD^&N zc6v5<+-t=iQ6Nifl9cJ|CkR9^R@Av*i&w%0Pml$cB{w4o5l2?ajTE>EsNUEKgTujx z-BMLMky%Ky9@3NnTix*Aju->5YVxwe`Z2#=Y;t`6iNZ1n#a~O9n-o{b0`-szt51;& z?zX#67s#lQ@}f$i|DwNeA%b3*HJFiycY9b;#_6*Wa+`1sv0iQ@8=@Zr1HM#$rc=X_ zorec=bQxf6Cvfly*?Zyb%y%n&AA{`$r){mi(VsRmX8=#sKt2Twz z3abRwekCdVmiXqw^Wgfm{35cIH>iA7K?iS-Llzy+LqUeH>0CR0K}TiLc{RCY`TNJV z%m3V|??OjxmxBNR`U!p~pZ&E{?`UdlWlaCq>tA~^CmLhn*z71B=uiBx4lXaO+tH+J z8xxlCt0YF>6L9M4PZU*|nc`Zpk%37$ZOGa?pJNM@3JEI24wJmn=4 zB0d>ISwF(iyhtx+dE0-o8iE{H0C^O#%t^wRw^r6ZR|AR@LMN~7?9{D&O#f& z!3|hTL8C5ED#sv>d(iPWQ1I|#A|yV6OO*2QC~1}7WQ-Mpi=bFnE3G2UsoL(T77F=x zpmc^yxOAnT$;gejp0OmMjuY$X*Q=t?fmly+S;V9c1;s* zY4o@GY!#o%Abi;74N;h%f|Pt;dV;^36n#CO&qmSJ>Y0~5)lq1;u}~0^v~LWe`&MV} z(zJwX)O`?zyapQ}*cL}Qp%?@A<3veWMxBU#S2N;_i4WiltVANYHPiefenIrDYu4lncVps*8$E!*jB5eLwi;OCbL5y$nLV zaRQ$XoQuy!27z_72#&g)Do?wYan$?4T6sDw7Mt-en@FNke~MLstr$i)W4Lf_l%|bb zT-avHtj1qAg|>uF##)@wNtFTa_nEWRwv-klD~Il88mJF0{uaDTK2hwRSt zGHuCJhTfbZ{tO72Ar-dQBUPfS6*dSN={6<^T)G-tv-;UnY%$C0X+*65@f-}^Atk&0 zBc^nUCrX?mjI6lr;YK@5_C8(WWEJ!zBJN?7*H4Btfzo?i!M9j~9ni4b@XvVKy=-yP z_6O5V;TX)Zyv_@e3Oo)=GI4{w-emBEqOmRklIWh%i`*i-!Z-@mj4KUL_1&)~M2%oO z=4lD!Ay3BRxK*tYscrb^j{cS5#!Ec)3w2|m%-mepC5cNd7|MU7Jbz}1oiEU$oC(bmS+j+3+ZeKAShz0ZOHLEk$n@P)#NWO z!+0)04&Y$XT9?lWTk6DFLEfc3Qqxp;xLPDMa46fY|_lQ)?IjT1ej zv8K?hBoNbX+mZ2;Gc83=!fFZ|uXbjH$=s^AGLvN+<_9}bqh?K(Kg(UaMn}%beQhdh zPAh={i+gmX{1PdgELC`*$$P$5{_EKLK*dEP8JuEq218%Q1Y6MwLs1uA2u0^>pw42d z`jn&kl)_PRj;5I1E;NG`Dyr-5-G*q}Zm{5zV2}w;!oDGDQEh5#L@%_RKzS6kH`lYJ@c;MO~k*n&~ud=oiQadtsh+UlQ7Y% zgGCa!zQoH7gEPjacqH`F>eBio!m&)@O)<*sW(}&iK%<4Gw6xoeYOWyhZ#b^tfq z`&!sXb@ad0&5 zmm?=Cgblq|#V_zP$4@|C^e07~&3+Ed)17Va(vE%m6do?4JBnVn`LxykWzo~_{1d_V z=epr+4J&8!ZzgrT6rgQ#d6Oq|T;Fucwa($(S1YG*crMzA;oz5Mtrd>hq3i4$v>?q% zjlJ_UiXjrExQiRGU$b8cs15aYDZPx^0r%!D_5U0$s8m7%%KAu@lYs{S;Qr-)9UR>( zjU9f+2zu4DqtiK1ynfcccU^J!i2Fi)QeYh-_-y_|ikbTK$47v`{G`mzL{jbbyp4@S z|5vIr-?SN?zgN`+Z}PE+WsyxwP@Yz)CYfl^D+~fLm6Qf!)%e9a`#0vk;#m=uKxskd z)*@Q(^!HmbtJ}<(W4Hn=pg>dR)+u*xht>L($)H+vdug!Nk^=LPpbE{FQ&mN!IuoUy z)y`{!211z)JpH+ZXdttYr|M;{0?T@l8q{r>b6PYpSx%1*G^JQnh|=%)aY#$PHfNfe9 zq+qJX2VHvEz(;hMcwo#kJlypkVBztm^Ju3kB0OJ>20A=8Peg0}Wct!M5wOnr{gtS) z#=BQoZ$=FkFc)oNLddx$nnE(f(hA!)!T@cM{bmQT$JA#x_HX5WS6YrT&q-1ma?D?#h|=nidoueRJ5?zwBY&sY_Tx zY%*0N$_fZpD2DX=Cjkp__TE-(Sw2VH3)+#r6_i-7cn4i{D7|dZAn88|ZeGFIvc~oi-mHp?fVjw0K_KdjJEq4C-D@qbusaGbexw{ zSum9mgs-&0$9`D;xP!V`mY8@>?oah^es?JzNWE(ZWf0L|DLdMmS%3Y@pe^GB<$DM)g3ig_AiA62rCRE-hI7-EkzJ~f zFtsd0!OU~G-rG{NWe)v%o-aIgyRi@Uirp_r#i%3c^jo_TA+^)Rj_Ly^X5VssJGm;b z*RW}&9*AjHDzBN%%R#(Vmyw*u;nW}(n~}qo6EOqt*w0N=RvtO(2jTNJB2NQtOT|IA zVJYcYLF-a$srA!@8O$CzLrUMemW9;<$GgxEDN6z8XM}`>Uzq-&+ z-_lUnRNu_{_k8H6v1q+4f#``4J1EJ6`0D^{Si?~cXFol!A!uyy?lN zysy>|By-@Dc`uK_{?)SWC55Hoo$Ltv(gVe8SaQxgZ#z7q zT&UCCsl-h2@qR@PL*4vn7fUXMTY9YO<06-c0&BRYAUk!nW{$$DGe(@=^Ao0h_+?Zq zI#$>-&=xMa6m8asUrr-}ZSa6wSAK%^z87bVlBJP zJ-BKIoYcFYleQ)LwI>8kI+RaS+3qr7b*u?F%c#3XLX(_SEMMS_5)xsoQW1o;*a#nX zUwsXe_*oQcel+AQ&)be-L5J>Z=cs4{f5q8}0Kj4x0I(=({*-R(m1 z0c2+|@x$spm%Rm47_V?h@+(V|L9tCOmE%TdAxHqa5@e!ZE20*9YRTZ4Ea%mGK!&za z250JH&RX>#d0gy_ZD0The>=*`3qn^NJpwoy&4#w2`1@!bmlFmu(4Z`iRTzXD8(d^y z`T>hV2gGj6sLcg*ylg`jSV{P(DQEditkaF`Cg4+Jdh}MDfXL9GbF-W#h*{PVUQ#W3 zR`DFherX+e%(LoiBlT(q2_^+VRh0|`4WppTfB_Ypb!a$fypF=VWtG0(SZA1D7|`g- zDy8Wet}nTYUXDgIRIE+*^qea@Sc`d*(DZ1<64uWNJ+(2k2ow`FtMBO+bl??DIGsO$ zaL$W;BSFyTI@@APr>{Zc#_T^IiklapHcTt2A13qOG{p-Y)TD0Jq6lRzx?3r=GYy&$ zlvq?eqJm(1O<0_rQ-iamjZ&X2V9QRhE^i9!O@cW(^fqMq&M(1lhi%?=R;+Y0re50f zWQImIew{G4MT1-(VHo3Os=I}wqo_D zZ^g_|1oKpegb`HdHp9@+t7p*Eusko-o z<@9>3av8xvY5R%SRR_AELM;u5EIrGD&ruR6c>t98T%{2l-o%;u<3pwcM@F?Mm20s5QsR!a7YO?DI%ag7PuH@K2`@*#06z56_=@Z&I6WR z&s*7ROXi5yZ0V-)&TOqd{<`}v(b~T%l};--vWbv0>_JA&lz9&BrNAciRQal*ZRYi~ zgT(!vQ(0@Q&+glc1-_iV9dOP)a%z`(V}x{K7kHHk?~=B)Q+_R$*dl>9M2Z_>k~~c1 zk8hakkA9nTeJ8j#c@vb`ijy%-Q;3TQfe?t@%$rd1{73Kklcf47<>MF8kL3j7zmG$G zTigE|h9BeazmAOfF6-sr)mb2S@Ihyh878Me0;-Jp*zO0F0K4THvY9Fc4JMH}iMyNl zlUb*wOn2f(WPZN5xJIs8wqwHV%L=^_(Qzi*CAI!j7-zLNp67lhl3gm}wg7)zpvA;H zs(f8F8WbCFlE-H)Z7STtTaX)T&Em{#2gpt8U7VwD#x+tW85ayv}tyJI~@#kJI zNY5bm7ELnxrMp9WD2t@7c*grdybADidTJ1>XtNp*_PX;hZXSbZLqG49w%U`0=!K{M zOzr|Jl>q8bw(q7?A?b~;dhtVriq;6T4ij30yeZF@YJv` z{8P)HNezE%8N>ZYEq|pr{Hf*7t%kp~c#-|3<~GP2#(#yykop+vsJy>F{ePe(Y+?Wa literal 0 HcmV?d00001 diff --git a/docs/nextreg-TBBLUE.30007.SPRITES.txt b/docs/nextreg-TBBLUE.30007.SPRITES.txt new file mode 100644 index 0000000..ff863b4 --- /dev/null +++ b/docs/nextreg-TBBLUE.30007.SPRITES.txt @@ -0,0 +1,772 @@ +The ZX Next stores configuration state in a field of registers. +These registers are accessible via two io ports or via the special nextreg instructions. + +Port 0x243B (9275) is used to select the register by number, listed below. +Port 0x253B (9531) is used to read or write the register value. + +Some registers are accessible only during the initialization process. +Registers 0x80 and above are inaccessible to the copper. + +Initial values are set during a hard or soft reset but may be modified by the operating system. +A hard reset is generated at power on, by the F1 key or via a write to nextreg 0x02 with bit 1 set. +A soft reset is generated by a hard reset, the F4 key or via a write to nextreg 0x02 with bit 0 set. + +NEXTREG REGISTER SPACE (Core 3.00.07) +Generally a set bit indicates the property is asserted + +0x00 (00) => Machine ID +(R) + 00000001 = DE1A + 00000010 = DE2A + 00000101 = FBLABS + 00000110 = VTRUCCO + 00000111 = WXEDA + 00001000 = EMULATORS * + 00001010 = ZX Spectrum Next * + 00001011 = Multicore + 11111010 = ZX Spectrum Next Anti-brick * + * = Relevant for ZX Next machines & software + +0x01 (01) => Core Version +(R) + bits 7:4 = Major version number + bits 3:0 = Minor version number + (see register 0x0E for sub minor version number) + +0x02 (02) => Reset +(R) + bit 7 = Indicates the reset signal to the expansion bus and esp is asserted + bits 6:2 = Reserved + bit 1 = Indicates the last reset was a hard reset + bit 0 = Indicates the last reset was a soft reset + * Only one of bits 1:0 will be set +(W) + bit 7 = Assert and hold reset to the expansion bus and the esp wifi (hard reset = 0) + bits 6:2 = Reserved, must be 0 + bit 1 = Generate a hard reset (reboot) + bit 0 = Generate a soft reset + * Hard reset has precedence + +0x03 (03) => Machine Type +(R) + bit 7 = nextreg 0x44 second byte indicator + bits 6:4 = Display timing + bit 3 = User lock on display timing applied + bits 2-0 = Machine type +(W) + A write to this register disables the bootrom in config mode + bit 7 = 1 to allow changes to bits 6:4 + bits 6:4 = Selects display timing (VGA/RGB only) + 000 = Internal Use + 001 = ZX 48K display timing + 010 = ZX 128K/+2 display timing + 011 = ZX +2A/+2B/+3 display timing + 100 = Pentagon display timing 50 Hz only + bit 3 = 1 to toggle user lock on display timing (hard reset = 0) + bits 2:0 = Selects machine type (config mode only) + may affect port decoding and enabling of some hardware + 000 = Configuration mode + 001 = ZX 48K + 010 = ZX 128K/+2 + 011 = ZX +2A/+2B/+3 + 100 = Pentagon + +0x04 (04) => Config Mapping (config mode only, bootrom disabled) +(W) + bits 7:5 = Reserved, must be 0 + bits 4:0 = 16K SRAM bank mapped to 0x0000-0x3FFF (first 1MB of sram) (hard reset = 0) + +0x05 (05) => Peripheral 1 Setting +(R/W) + bits 7:6 = Joystick 1 mode (LSB) + bits 5:4 = Joystick 2 mode (LSB) + bit 3 = Joystick 1 mode (MSB) + bit 2 = 50/60 Hz mode (0 = 50Hz, 1 = 60Hz, Pentagon is always 50Hz) + bit 1 = Joystick 2 mode (MSB) + bit 0 = Enable scandoubler (1 = enabled) +Joystick modes: + 000 = Sinclair 2 (67890) + 001 = Kempston 1 (port 0x1F) + 010 = Cursor (56780) + 011 = Sinclair 1 (12345) + 100 = Kempston 2 (port 0x37) + 101 = MD 1 (3 or 6 button joystick port 0x1F) + 110 = MD 2 (3 or 6 button joystick port 0x37) + +0x06 (06) => Peripheral 2 Setting +(R/W) + bit 7 = Enable F8 cpu speed hotkey (soft reset = 1) + bit 6 = DMA mode (0 = zxn dma, 1 = z80 dma) (hard reset = 0) + bit 5 = Enable F3 50/60 Hz hotkey (soft reset = 1) + bit 4 = Enable divmmc automap and divmmc nmi by DRIVE button (hard reset = 0) + bit 3 = Enable multiface nmi by M1 button (hard reset = 0) + bit 2 = PS/2 mode (0 = keyboard primary, 1 = mouse primary; config mode only) + bits 1-0 = Audio chip mode (00 = YM, 01 = AY, 11 = Hold all AY in reset) + +0x07 (07) => CPU Speed +(R) + bits 7:6 = Reserved + bits 5:4 = Current actual cpu speed + bits 3:2 = Reserved + bits 1:0 = Programmed cpu speed +(W) + bits 7:2 = Reserved, must be 0 + bits 1:0 = Set cpu speed (soft reset = 00) + 00 = 3.5 MHz + 01 = 7 MHz + 10 = 14 MHz + 11 = 28 MHz + +0x08 (08) => Peripheral 3 Setting +(R/W) + bit 7 = Unlock port 0x7ffd (read 1 indicates port 0x7ffd is not locked) + bit 6 = Disable ram and port contention (soft reset = 0) + bit 5 = AY stereo mode (0 = ABC, 1 = ACB) (hard reset = 0) + bit 4 = Enable internal speaker (hard reset = 1) + bit 3 = Enable 8-bit DACs (A,B,C,D) (hard reset = 0) + bit 2 = Enable port 0xff Timex video mode read (disables floating bus on 0xff) (hard reset = 0) + bit 1 = Enable turbosound (currently selected AY is frozen when disabled) (hard reset = 0) + bit 0 = Implement issue 2 keyboard (hard reset = 0) + +0x09 (09) => Peripheral 4 Setting +(R/W) + bit 7 = Place AY 2 in mono mode (hard reset = 0) + bit 6 = Place AY 1 in mono mode (hard reset = 0) + bit 5 = Place AY 0 in mono mode (hard reset = 0) + bit 4 = Sprite id lockstep (nextreg 0x34 and port 0x303B are in lockstep) (soft reset = 0) + bit 3 = Reset divmmc mapram bit (port 0xe3 bit 6) (read returns 0) + bit 2 = 1 to silence hdmi audio (hard reset = 0) + bits 1:0 = Scanline weight + 00 = scanlines off + 01 = scanlines 75% + 10 = scanlines 50% + 11 = scanlines 25% + +0x0E (14) => Core Version (sub minor number) +(R) (see register 0x01 for the major and minor version number) + +0x10 (16) => Core Boot +(R) + bits 7:2 = Reserved, must be 0 + bit 1 = Button DRIVE (divmmc) is pressed + bit 0 = Button M1 (multiface) is pressed +(W) + bit 7 = Start selected core + bits 6:5 = Reserved, must be 0 + bits 4:0 = Core ID 0-31 (config mode only) + +0x11 (17) => Video Timing (writable in config mode only) +(R/W) + bits 7:3 = Reserved, must be 0 + bits 2:0 = Mode (VGA = 0..6, HDMI = 7) + 000 = Base VGA timing, clk28 = 28000000 + 001 = VGA setting 1, clk28 = 28571429 + 010 = VGA setting 2, clk28 = 29464286 + 011 = VGA setting 3, clk28 = 30000000 + 100 = VGA setting 4, clk28 = 31000000 + 101 = VGA setting 5, clk28 = 32000000 + 110 = VGA setting 6, clk28 = 33000000 + 111 = HDMI, clk28 = 27000000 + * 50/60Hz selection depends on bit 2 of nextreg 0x05 + +0x12 (18) => Layer 2 Active RAM bank +(R/W) + bit 7 = Reserved, must be 0 + bits 6:0 = Starting 16K RAM bank (soft reset = 8) + +0x13 (19) => Layer 2 Shadow RAM bank +(R/W) + bit 7 = Reserved, must be 0 + bits 6:0 = Starting 16K RAM bank (soft reset = 11) + +0x14 (20) => Global Transparency Colour +(R/W) + bits 7:0 = Transparency colour value (soft reset = 0xe3) + * Note: This value is 8-bit, so the transparency colour is compared against + the MSB bits of the final 9-bit colour only. + * Note: This colour only applies to Layer 2, ULA and LoRes. + Sprites use nextreg 0x4B and the tilemap uses nextreg 0x4C for transparency. + +0x15 (21) => Sprite and Layers System +(R/W) + bit 7 = Enable lores mode (soft reset = 0) + bit 6 = Sprite priority (1 = sprite 0 on top, 0 = sprite 127 on top) (soft reset = 0) + bit 5 = Enable sprite clipping in over border mode (soft reset = 0) + bits 4:2 = Set layer priority (eg SLU = sprites over layer 2 over ula) (soft reset = 000) + 000 - S L U + 001 - L S U + 010 - S U L + 011 - L U S + 100 - U S L + 101 - U L S + 110 - S(U+L) ULA and Layer 2 combined, colours clamped to 7 + 111 - S(U+L-5) ULA and Layer 2 combined, colours clamped to [0,7] + bit 1 = Enable sprites over border (soft reset = 0) + bit 0 = Enable sprites (soft reset = 0) + +0x16 (22) => Layer2 X Scroll LSB +(R/W) + bits 7:0 = X Offset (0-255) (soft reset = 0) + +0x17 (23) => Layer2 Y Scroll +(R/W) + bits 7:0 = Y Offset (0-191) (soft reset = 0) + +0x18 (24) => Clip Window Layer 2 +(R/W) + bits 7:0 = Clip window coordinate (inclusive) + 1st write - X1 position (soft reset = 0) + 2nd write - X2 position (soft reset = 255) + 3rd write - Y1 position (soft reset = 0) + 4rd write - Y2 position (soft reset = 191) + Reads do not advance the clip position + +0x19 (25) => Clip Window Sprites +(R/W) + bits 7:0 = Clip window coordinate (inclusive) + 1st write - X1 position (soft reset = 0) + 2nd write - X2 position (soft reset = 255) + 3rd write - Y1 position (soft reset = 0) + 4rd write - Y2 position (soft reset = 191) + Reads do not advance the clip position + When the clip window is enabled for sprites in "over border" mode, + the X coords are internally doubled and the clip window origin is + moved to the sprite origin inside the border. + +0x1A (26) => Clip Window ULA (and LoRes, see note) +(R/W) + bits 7:0 = Clip window coordinate (inclusive) + 1st write = X1 position (soft reset = 0) + 2nd write = X2 position (soft reset = 255) + 3rd write = Y1 position (soft reset = 0) + 4rd write = Y2 position (soft reset = 191) + Reads do not advance the clip position + LoRes may get a separate clip window in the future + +0x1B (27) => Clip Window Tilemap +(R/W) + bits 7:0 = Clip window coordinate (inclusive) + 1st write = X1 position (soft reset = 0) + 2nd write = X2 position (soft reset = 159) + 3rd write = Y1 position (soft reset = 0) + 4rd write = Y2 position (soft reset = 255) + Reads do not advance the clip position + The X coordinates are internally doubled. + +0x1C (28) => Clip Window control +(R) (may change) + bits 7:6 = Tilemap clip index + bits 5:4 = ULA/Lores clip index + bits 3:2 = Sprite clip index + bits 1:0 = Layer 2 clip index +(W) (may change) + bits 7:4 = Reserved, must be 0 + bit 3 = Reset the tilemap clip index + bit 2 = Reset the ULA/LoRes clip index + bit 1 = Reset the sprite clip index + bit 0 = Reset the Layer 2 clip index + +0x1E (30) => Active video line (MSB) +(R) + bits 7:1 = Reserved + bit 0 = Active line MSB + +0x1F (31) => Active video line (LSB) +(R) + bits 7:0 = Active line LSB + +0x22 (34) => Line Interrupt control +(R/W) + bit 7 = (R) Indicates if the ula is asserting an interrupt (even if disabled) + bits 7:3 = Reserved, must be 0 + bit 2 = Disables ula interrupt (soft reset = 0) + bit 1 = Enables line Interrupt (soft reset = 0) + bit 0 = MSB of line interrupt value (soft reset = 0) + +0x23 (35) => Line Interrupt Value LSB +(R/W) + bits 7:0 = Line Interrupt value LSB (soft reset = 0) + +0x26 (38) => ULA X Scroll +(R/W) + bits 7:0 = X Offset (0-255) (soft reset = 0) + +0x27 (39) => ULA Y Scroll +(R/W) + bits 7:0 = Y Offset (0-191) (soft reset = 0) + +0x28 (40) => PS/2 Keymap Address MSB +(R) + bits 7:0 = Stored palette value from nextreg 0x44 +(W) + bits 7:1 = Reserved, must be 0 + bit 0 = MSB address + +0x29 (41) => PS/2 Keymap Address LSB +(W) + bits 7:0 = LSB adress + +0x2A (42) => PS/2 Keymap Data MSB +(W) + bits 7:1 = Reserved, must be 0 + bit 0 = MSB data + +0x2B (43) => PS/2 Keymap Data LSB +(W) (write causes the data to be written and auto-increments the keymap address) + bits 7:0 = LSB data + +0x2C (44) => DAC B Mirror (left) +(R) + bits 7:0 = MSB of current I2S (pi) left side sample + the LSB is latched and can be read from nextreg 0x2D later +(W) + bits 7:0 = 8-bit sample written to left side DAC B (soft reset = 0x80) + +0x2D (45) => DAC A+D Mirror (mono) +(R) + bits 7:0 = LSB of last I2S (pi) sample read from nextreg 0x2C or nextreg 0x2E +(W) + bits 7:0 = 8-bit sample written to DACs A and D (soft reset = 0x80) + +0x2E (46) => DAC C Mirror (right) +(R) + bits 7:0 = MSB of current I2S (pi) right side sample + the LSB is latched and can be read from nextreg 0x2D later +(W) + bits 7:0 = 8-bit sample written to right side DAC C (soft reset = 0x80) + +0x2F (47) => Tilemap X Scroll MSB +(R/W) + bits 7:2 = Reserved, must be 0 + bits 1:0 = MSB X Offset (soft reset = 0) + Meaningful Range is 0-319 in 40 char mode, 0-639 in 80 char mode + +0x30 (48) => Tilemap X Scroll LSB +(R/W) + bits 7:0 = LSB X Offset (soft reset = 0) + Meaningful range is 0-319 in 40 char mode, 0-639 in 80 char mode + +0x31 (49) => Tilemap Offset Y +(R/W) + bits 7:0 = Y Offset (0-255) (soft reset = 0) + +0x32 (50) => LoRes X Scroll +(R/W) + bits 7:0 = X Offset (0-255) (soft reset = 0) + LoRes scrolls in "half-pixels" at the same resolution and smoothness as Layer 2. + +0x33 (51) => LoRes Y Scroll +(R/W) + bits 7:0 = Y Offset (0-191) (soft reset = 0) + LoRes scrolls in "half-pixels" at the same resolution and smoothness as Layer 2. + +0x34 (52) => Sprite Number +(R/W) + If the sprite number is in lockstep with port 0x303B (nextreg 0x09 bit 4 is set) + bit 7 = Pattern address offset (add 128 to pattern address) + bits 6:0 = Sprite number 0-127, Pattern number 0-63 + Selects which sprite has its attributes connected to the following registers. + Effectively performs an out to port 0x303B with the same value + Otherwise + bit 7 = Ignored + bits 6:0 = Sprite number 0-127 + Selects which sprite has its attributes connected to the following registers. + Bit 7 always reads back as zero. + +0x35 (53) => Sprite Attribute 0 +0x75 (117) => Sprite Attribute 0 with automatic post increment of Sprite Number +(W) See documentation at https://www.specnext.com/sprites/ + +0x36 (54) => Sprite Attribute 1 +0x76 (118) => Sprite Attribute 1 with automatic post increment of Sprite Number +(W) See documentation at https://www.specnext.com/sprites/ + +0x37 (55) => Sprite Attribute 2 +0x77 (119) => Sprite Attribute 2 with automatic post increment of Sprite Number +(W) See documentation at https://www.specnext.com/sprites/ + +0x38 (56) => Sprite Attribute 3 +0x78 (120) => Sprite Attribute 3 with automatic post increment of Sprite Number +(W) See documentation at https://www.specnext.com/sprites/ + +0x39 (57) => Sprite Attribute 4 +0x79 (121) => Sprite Attribute 4 with automatic post increment of Sprite Number +(W) See documentation at https://www.specnext.com/sprites/ + +0x40 (64) => Palette Index +(R/W) + bits 7:0 = Select the palette index to change the associated colour. (soft reset = 0) + For the ULA only, INKs are mapped to indices 0-7, Bright INKS to indices 8-15, + PAPERs to indices 16-23 and Bright PAPERs to indices 24-31. + In ULANext mode, INKs come from a subset of indices 0-127 and PAPERs come from + a subset of indices 128-255. The number of active indices depends on the number + of attribute bits assigned to INK and PAPER out of the attribute byte. + In ULA+ mode, the top 64 entries hold the ula+ palette. + The ULA always takes border colour from paper for standard ULA and ULAnext. + +0x41 (65) => Palette Value (8 bit colour) +(R/W) + bits 7:0 = Colour for the palette index selected by nextreg 0x40. + The format is RRRGGGBB - the lower blue bit of the 9-bit colour will be the logical + OR of blue bits 1 and 0 of this 8-bit value. + After the write, the palette index is auto-incremented to the next index if the + auto-increment is enabled in nextreg 0x43. Reads do not auto-increment. + Any other bits associated with the index will be zeroed. + +0x42 (66) => ULANext Attribute Byte Format +(R/W) + bits 7:0 = Mask indicating which bits of an attribute byte are used to represent INK. + Other bits represent PAPER. (soft reset = 0x07) + The mask can only indicate a solid sequence of bits on the right side of an attribute + byte (1, 3, 7, 15, 31, 63, 127 or 255). + INKs are mapped to base index 0 in the palette and PAPERs and border are + mapped to base index 128 in the palette. + The 255 value enables the full ink colour mode making all the palette entries INK. + In this case PAPER and border are both taken from the fallback colour in nextreg 0x4A. + If the mask is not one of those listed above, the INK is taken as the logical AND of + the mask with the attribute byte and the PAPER and border colour are again both taken + from the fallback colour in nextreg 0x4A. + +0x43 (67) => Palette Control +(R/W) + bit 7 = Disable palette write auto-increment (soft reset = 0) + bits 6-4 = Select palette for reading or writing (soft reset = 000) + 000 = ULA first palette + 100 = ULA second palette + 001 = Layer 2 first palette + 101 = Layer 2 second palette + 010 = Sprites first palette + 110 = Sprites second palette + 011 = Tilemap first palette + 111 = Tilemap second palette + bit 3 = Select Sprites palette (0 = first palette, 1 = second palette) (soft reset = 0) + bit 2 = Select Layer 2 palette (0 = first palette, 1 = second palette) (soft reset = 0) + bit 1 = Select ULA palette (0 = first palette, 1 = second palette) (soft reset = 0) + bit 0 = Enabe ULANext mode (soft reset = 0) + +0x44 (68) => Palette Value (9 bit colour) +(R/W) + Two consecutive writes are needed to write the 9 bit colour + 1st write: + bits 7:0 = RRRGGGBB + 2nd write: + bits 7:1 = Reserved, must be 0 + bit 0 = lsb B + If writing to an L2 palette + bit 7 = 1 for L2 priority colour, 0 for normal. + An L2 priority colour moves L2 above all layers. If you need the same + colour in both priority and normal modes, you will need to have two + different entries with the same colour one with and one without priority. + After two consecutive writes the palette index is auto-incremented if + auto-increment is enabled in nextreg 0x43. + Reads only return the 2nd byte and do not auto-increment. + +0x4A (74) => Fallback Colour +(R/W) + bits 7:0 = 8-bit colour used if all layers are transparent (soft reset = 0xe3) + +0x4B (75) => Sprite Transparency Index +(R/W) + bits 7:0 = Sprite colour index treated as transparent (soft reset = 0xe3) + For 4-bit sprites only the bottom 4-bits are used + +0x4C (76) => Tilemap Transparency Index +(R/W) + bits 7-4 = Reserved, must be 0 + bits 3-0 = Tilemap colour index treated as transparent (soft reset = 0xf) + +0x50 (80) => MMU slot 0 +(R/W) + bits 7:0 = 8K RAM page occupying address 0x0000 - 0x1FFF (soft reset = 255) + Pages range from 0 to 223 on a fully expanded Next. + A 255 value causes the ROM to become visible. + +0x51 (81) => MMU slot 1 +(R/W) + bits 7:0 = 8K RAM page occupying address 0x2000 - 0x3FFF (soft reset = 255) + Pages range from 0 to 223 on a fully expanded Next. + A 255 value causes the ROM to become visible. + +0x52 (82) => MMU slot 2 +(R/W) + bits 7:0 = 8K RAM page occupying address 0x4000 - 0x5FFF (soft reset = 10) + Pages range from 0 to 223 on a fully expanded Next. + +0x53 (83) => MMU slot 3 +(R/W) + bits 7:0 = 8K RAM page occupying address 0x6000 - 0x7FFF (soft reset = 11) + Pages range from 0 to 223 on a fully expanded Next. + +0x54 (84) => MMU slot 4 +(R/W) + bits 7:0 = 8K RAM page occupying address 0x8000 - 0x9FFF (soft reset = 4) + Pages range from 0 to 223 on a fully expanded Next. + +0x55 (85) => MMU slot 5 +(R/W) + bits 7:0 = 8K RAM page occupying address 0xA000 - 0xBFFF (soft reset = 5) + Pages range from 0 to 223 on a fully expanded Next. + +0x56 (86) => MMU slot 6 +(R/W) + bits 7:0 = 8K RAM page occupying address 0xC000 - 0xDFFF (soft reset = 0) + Pages range from 0 to 223 on a fully expanded Next. + +0x57 (87) => MMU slot 7 +(R/W) + bits 7:0 = 8K RAM page occupying address 0xE000 - 0xFFFF (soft reset = 1) + Pages range from 0 to 223 on a fully expanded Next. + +0x60 (96) => Copper Data 8-bit Write +(W) + bits 7:0 = Byte to write to copper instruction memory + Note that each copper instruction is two bytes long + After a write, the copper address is auto-incremented to the next memory position + +0x61 (97) => Copper Address LSB +(R/W) + bits 7-0 = Copper instruction memory address LSB (soft reset = 0) + (Copper addresses range over 0 - 0x7FF = 2K) + +0x62 (98) => Copper Control +(R/W) + bits 7:6 = Start control (soft reset = 00) + 00 = Copper fully stopped + 01 = Copper start, execute the list from index 0, and loop to the start + 10 = Copper start, execute the list from last point, and loop to the start + 11 = Copper start, execute the list from index 0, and restart the list + when the raster reaches position (0,0) + bits 2:0 = Copper instruction memory address MSB (soft reset = 0) + (Copper addresses range over 0 - 0x7FF = 2K) + Writing the same start control value does not reset the copper + +0x63 (99) => Copper Data 16-bit Write +(W) + The 16-bit value is written in pairs. The first 8-bits are the MSB and + are destined for an even copper instruction address. The second 8-bits are + the LSB and are destined for an odd copper instruction address. + After each write, the copper address is auto-incremented to the next memory position + After a write to an odd address, the entire 16-bits is written to copper memory at once + +0x68 (104) => ULA Control +(R/W) + bit 7 = Disable ULA output (soft reset = 0) + bit 6 = 0 to select the ULA colour for blending in SLU modes 6 & 7 (soft reset = 0) + = 1 to select the ULA/tilemap mix for blending in SLU modes 6 & 7 + bits 5:4 = Reserved, must be 0 + bit 3 = ULA+ enable (soft reset = 0) + bit 2 = ULA half pixel scroll (may change) (soft reset = 0) + bit 1 = Reserved, must be 0 + bit 0 = Enable stencil mode when both the ULA and tilemap are enabled (soft reset = 0) + (if either are transparent the result is transparent otherwise the result is a logical AND of both colours) + +0x69 (105) => Display Control 1 +(R/W) + bit 7 = Enable layer 2 (alias port 0x123B bit 1) + bit 6 = Enable ULA shadow display (alias port 0x7FFD bit 3) + bits 5:0 = Port 0xFF bits 5:0 alias (Timex display modes) + +0x6A (106) => LoRes Control +(R/W) + bits 7-6 = Reserved, must be 0 + bit 5 = LoRes is Radastan mode (128x96x4, 6144 bytes) (soft reset = 0) + bit 4 = LoRes Radastan timex display file xor (soft reset = 0) + bits 3:0 = LoRes palette offset (bits 1:0 apply in ula+ mode) (soft reset = 0) + +0x6B (107) => Tilemap Control +(R/W) + bit 7 = 1 Enable the tilemap (soft reset = 0) + bit 6 = 0 for 40x32, 1 for 80x32 (soft reset = 0) + bit 5 = Eliminate the attribute entry in the tilemap (soft reset = 0) + bit 4 = Palette select (soft reset = 0) + bit 3 = Select textmode (soft reset = 0) + bit 2 = Reserved, must be 0 + bit 1 = Activate 512 tile mode (soft reset = 0) + bit 0 = Force tilemap on top of ULA (soft reset = 0) + +0x6C (108) => Default Tilemap Attribute +(R/W) + Active if nextreg 0x6B bit 5 is set + bits 7:4 = Palette offset (soft reset = 0) + bit 3 = X mirror (soft reset = 0) + bit 2 = Y mirror (soft reset = 0) + bit 1 = Rotate (soft reset = 0) + bit 0 = ULA over tilemap (soft reset = 0) + (or bit 8 of the tile number if 512 tile mode is enabled) + +0x6E (110) => Tilemap Base Address +(R/W) (soft reset = 0x6c00) + bits 7:6 = Read back as zero, write values ignored + bits 5:0 = MSB of address of the tilemap in Bank 5 + The value written is an offset into Bank 5 allowing the tilemap to be placed + at any multiple of 256 bytes. + Writing a physical MSB address in 0x40-0x7f or 0xc0-0xff range is permitted. + The value read back should be treated as having a fully significant 8-bit value. + +0x6F (111) => Tile Definitions Base Address +(R/W) (soft reset = 0x4c00) + bits 7:6 = Read back as zero, write values ignored + bits 5:0 = MSB of address of tile definitions in Bank 5 + The value written is an offset into Bank 5 allowing tile definitions to be placed + at any multiple of 256 bytes. + Writing a physical MSB address in 0x40-0x7f or 0xc0-0xff range is permitted. + The value read back should be treated as having a fully significant 8-bit value. + +0x70 (112) => Layer 2 Control +(R/W) + bits 7:6 = Reserved, must be 0 + bits 5:4 = Layer 2 resolution (soft reset = 0) + 00 = 256x192x8 + 01 = 320x256x8 + 10 = 640x256x4 + bits 3:0 = Palette offset (soft reset = 0) + +0x71 (113) => Layer 2 X Scroll MSB +(R/W) + bits 7:1 = Reserved, must be 0 + bit 0 = MSB of scroll amount + +0x75 (117) => Sprite Attribute 0 with automatic post increment of Sprite Number +(W) see nextreg 0x35 + +0x76 (118) => Sprite Attribute 1 with automatic post increment of Sprite Number +(W) see nextreg 0x36 + +0x77 (119) => Sprite Attribute 2 with automatic post increment of Sprite Number +(W) see nextreg 0x37 + +0x78 (120) => Sprite Attribute 3 with automatic post increment of Sprite Number +(W) see nextreg 0x38 + +0x79 (121) => Sprite Attribute 4 with automatic post increment of Sprite Number +(W) see nextreg 0x39 + +0x7F (127) => User Register 0 +(R/W) + bits 7:0 = Unused storage available to the user (soft reset = 0xff) + +NEXTREG 0x80 AND HIGHER ARE INACCESSIBLE TO THE COPPER + +0x80 (128) => Expansion Bus Enable +(R/W) (hard reset = 0) +IMMEDIATE +bit 7 = 1 to enable the expansion bus +bit 5 = 1 to disable i/o cycles & ignore iorqula +bit 4 = 1 to disable memory cycles & ignore romcs +AFTER SOFT RESET (copied into bits 7-4) +bit 3 = 1 to enable the expansion bus +bit 1 = 1 to disable i/o cycles & ignore iorqula +bit 0 = 1 to disable memory cycles & ignore romcs + +0x81 (129) => Expansion Bus Control +(R/W) (hard reset = 0) +bit 7 = 1 if ROMCS is asserted on the expansion bus (read only) +bit 4 = 1 to propagate the max cpu clock at all times including when the expansion bus is off +bits 1-0 = max cpu speed when the expansion bus is on (currently fixed at 00 = 3.5MHz) + +0x85,0x84,0x83,0x82 (133-130) => Internal Port Decoding Enables (0x85 is MSB) (soft reset = all 1) +0x89,0x88,0x87,0x86 (137-134) => Expansion Bus Decoding Enables (0x89 is MSB) (hard reset = all 1) +(R/W) + bit 0 = port ff + bit 1 = port 7ffd + bit 2 = port dffd + bit 3 = port 1ffd + bit 4 = +3 floating bus + bit 5 = port 6b dma + bit 6 = port 1f kempston / md1 + bit 7 = port 37 kempston 2 / md2 + ----- + bit 8 = port e3 divmmc control + bit 9 = multiface (two variable ports) + bit 10 = port 103b,113b i2c + bit 11 = port e7,eb spi + bit 12 = port 133b,143b,153b uart + bit 13 = port fadf,fbdf,ffdf mouse + bit 14 = port 57,5b,303b sprites + bit 15 = port 123b layer2 + ----- + bit 16 = port fffd,bffd ay + bit 17 = port 0f,1f,4f,5f dac soundrive mode 1 + bit 18 = port f1,f3,f9,fb dac soundrive mode 2 + bit 19 = port 3f,5f dac stereo profi covox + bit 20 = port 0f,4f dac stereo covox + bit 21 = port fb dac mono pentagon/atm (sd mode 2 off) + bit 22 = port b3 dac mono gs covox + bit 23 = port df dac mono specdrum + ----- + bit 24 = port bf3b, ff3b ula+ + ----- + The internal port decoding enables always apply. + When the expansion bus is on, the expansion port decoding enables are logically ANDed with the internal enables. + A zero bit indicates the internal device is disabled. If the expansion bus is on, this allows io cycles for + disabled ports to propagate to the expansion bus, otherwise corresponding io cycles to the expansion bus are filtered. + +0x8A (138) => Expansion Bus IO Propagate +(R/W) + bits 7:4 = Reserved, must be 0 + bit 3 = Propagate port 0x1ffd io cycles (hard reset = 0) + bit 2 = Propagate port 0xdffd io cycles (hard reset = 0) + bit 1 = Propagate port 0x7ffd io cycles (hard reset = 0) + bit 0 = Propagare port 0xfe io cycles (hard reset = 1) + If any of the bits are set, io cycles for the corresponding ports are propagated to the expansion bus when + the expansion bus is on. If the internal port decode is still active, any response sent by devices on the + expansion bus will be ignored. The purpose here is to allow external peripherals to monitor changes in state + inside the zx next. + Port 0xfe is treated specially so that external keyboards can be attached. When its propagate bit is set, + the value read from the bus will mixed into keyboard reads on port 0xfe. + +0x8C (140) => Alternate ROM +(R/W) (hard reset = 0) +IMMEDIATE + bit 7 = 1 to enable alt rom + bit 6 = 1 to make alt rom visible only during writes, otherwise replaces rom during reads + bit 5 = 1 to lock ROM1 (48K rom) + bit 4 = 1 to lock ROM0 (128K rom) +AFTER SOFT RESET (copied into bits 7-4) + bit 3 = 1 to enable alt rom + bit 2 = 1 to make alt rom visible only during writes, otherwise replaces rom during reads + bit 1 = 1 to lock ROM1 (48K rom) + bit 0 = 1 to lock ROM0 (128K rom) +The locking mechanism also applies if the alt rom is not enabled. For the +3 and zx next, if the two lock bits are not +zero, then the corresponding rom page is locked in place. Other models use the bits to preferentially lock the corresponding +48K rom or the 128K rom. + +0x93,0x92,0x91,0x90 (147-144) => PI GPIO Output Enable (0x93 is MSB) +(R/W) + bits 27:0 Set bits enable GPIO output on the corresponding GPIO pin (soft reset = all 0) + (GPIO pins 1:0 cannot be enabled) + +0x9B,0x9A,0x99,0x98 (155-152) => PI GPIO (0x9B is MSB) +(R/W) + bits 27:0 Read / Write the GPIO pin state (soft reset = 0x00001ff) + (writes only propagate when the corresponding pin has its output enabled) + +0xA0 (160) => PI Peripheral Enable +(R/W) + bits 7:6 = Reserved, must be 0 + bit 5 = Enable UART on GPIO 14,15 (overrides gpio) (soft reset = 0) + bit 4 = 0 to connect Rx to GPIO 15, Tx to GPIO 14 (for comm with pi hats) (soft reset = 0) + = 1 to connect Rx to GPIO 14, Tx to GPIO 15 (for comm with pi) + bit 3 = Enable I2C on GPIO 2,3 (override gpio) (soft reset = 0) + bits 2:1 = Reserved, must be 0 + bit 0 = Enable SPI on GPIO 7,8,9,10,11 (overrides gpio) (soft reset = 0) + +0xA2 (162) => PI I2S Audio Control +(R/W) + bits 7:6 = I2S enable (soft reset = 00) + 00 = i2s off + 01 = i2s is mono source right + 10 = i2s is mono source left + 11 = i2s is stereo + bit 5 = Reserved, must be 0 + bit 4 = 0 PCM_DOUT to pi, PCM_DIN from pi (hats) (soft reset = 0) + = 1 PCM_DOUT from pi, PCM_DIN to pi (pi) + bit 3 = Mute left side (soft reset = 0) + bit 2 = Mute right side (soft reset = 0) + bit 1 = Slave mode (PCM_CLK, PCM_FS supplied externally) (soft reset = 0) + bit 0 = Direct i2s audio to EAR on port 0xFE (soft reset = 0) + +0xA3 (163) => PI I2S Clock Divide (Master Mode) +(R/W) + bits 7:0 = Clock divide sets sample rate when in master mode (soft reset = 11) + clock divider = 538461 / SampleRateHz - 1 diff --git a/dot/NXTP b/dot/NXTP index 3de0d3cabdb4c33f0043338a4fdfafe76b05eae7..26b773bf51d59ee1f4a777531794ba9a95a8aed4 100644 GIT binary patch delta 2196 zcmZWqYitu&7QPcZ#xdB$xDf`NXwD20&b)2M*V&}FfOXSqND`Rx4UHv7n5l5vx&Y+R&D!ZK7rA6euMGh$egQIB_ej zf1J7BcfNDxoICd(|5rJw9d~(i??~MCsPT6x%~;D3vR{JFW5b6erg?c983$zBR}`bR zcb1t)mO)36?WF4I6qAG@PPtiqyES?RzwY=57#O#Q|yNSY#0toFrRrEG+cap{t ziJMMZEp}2M;9t@xVG+(5XC$ko0uu!HqP(@b%IuHAj~a;;5U!flxv}vz4X|1~Sa6r< zE-7ov!(9@ewYy7?mGr@Rsn%-o;n6M$*iy=?Q5cAkl)(sw!!i>>)^U>ET33N{)^Ru` zGZmC^6UKuHk(U`4Az-;?Tu#7QYH5c-+Wx$o57kv#+7+u|C_%lW)O-CEI3ruJ$M|hm zxFtAU9bbl-<{GQ3((1H2+)c}{@m;cMsbiN=oA!@DPko)Ia3LqJ+Ok&j`^*FNaEo?r z%va3*dZ?o1!jbwqf8hd=h%IfKTGnseyw>j{0yzD9e#6#>SJDh-JuIV9G{d*`AUhda zX?e4~8fTNR&1orujoXrOO*TC_0d~v`Dh6No^*n}WLtc=99;N=0ME{5 z!3Ry9srs~3gH8+_;q^dDFC3NqNZeR5{yE6`TD z_}1pVG9h`cQ_g;&eMOe}Vy|p9AhdG0+j(;PJn~o7hOntAZ%uDq z@1J{&Zxp6Ew9U#)RIpy_LB4kQqI}u-Nhy3S|G#Te)~V|jbq&OiDj+GGprmKwZ#{9H_#RE#=0p*k8<3yjM0VGEdp>aB~$A-g7(^17n z=TbUPRFI|u7*x3R3LJA@@*A6X*g+-Dkazz^56#gPC7PBPR?s@Xuf2U^yWh9=k89Zb zSGBDtGwhq3QY!RdLTUZm9&&MJ9*9HwWus|t`A;#J4=@tb5XMMCU76%AY;)8U8M zxbbUZj2sf;Amq;?(UoGtmuA(qDw$xKdVMUfUmr{9CE-nxi#fttHN0sYs#kEeD)CSo z!9m27DtbnxTlXTrtouaq1+}nMHI}O8Rw87qcAi^|bt1ObEykJrohfy&IHjgVYw-K2 zK5=1f?t7JS4rw%GYok*txxiB@@5&6?p3##k&(+{FP)Yxh)@*Q{`!Q(B6fG@UkJPF#Gk4!RczeWx=KUD#Hfi=lc1)7 znj|$CJ+Nj&8@ik2^HJAGckD~y`fL!M#8rt*g&R2;oylKq5X_I z#m2S1U+#$}A}QO;OA!s*-5>1;+n-9SCg5Eg~aN%FQ7G61X4XC N`e2Z&=xbjb{vW!xSpxt7 delta 1988 zcmZWqeQZ-z6n}4JV{{f*2BA~Ip7$`c@3U)n*KDO7vnvg3W3y8r%rN{QCjNl|5#~l( z5=9^qb!jkY_=v=>#Kf(c(4b&+4ar{hWl8^FGC(M@86^)GlP@>ly!Ul07~dcFp5O2M z&bjBEckg}Qxc-!SO~tY00`sCnm4pDTEukoV7c^J&*9)|7Nq|zTMctg{9eVLJGaECb zCbwU3hXt*Bwuz`{%)LU4x!8EkI?I*RBITJE98l&-9h88gb{*(J&)`J(u!^1GoyD(i%a~Akt-&){C=i4L%gpdSQb|7ZApenOcO2 zjUsKr1e})DWgg(1i;Gg5#kyxhE{i!+?S!qQI`vaA6LP}a#D*s4Vv8Z+gDYEtjm@ng zix~@G)5CnzbL;#hLzfdioXM~!=7cYe6qm_b(?zM}2yPf_N0537;xPM9)c>u~u&l#fkaaYC_+yg&q1(Jb+8VXx(4?mO}829Z{2icw4m@z<~> z(DgODXl+-r(|&gc7eZ=6utuujC6O*6y$R#wjSu%GQkAQW^r3-+Z;j&COPRGC{A|2X z1ZizJ4X*uF4rY<=s~047ft-1hgM|cgt5H;s(doS$d_*w*kmmFO4!)WO#pz=loHl@3 zi#x!=;}AUiFSGYSXedCyr63f&|diTMpLWq_zIXKr%f%zOUfz(+vL(3yE?%DWcw z(4GfNc-WE$6+FC^2LT=q7$BbcVCXL6?g5gFlT}-y5&-kK-Q+1$#eFzK>u`NRoB3|{V3=WU_xtzJo z!|S9mK-p=kSWU>8TQf|=t5SAwdtyX4TYz`|t1F*j+KDbzBjAIKPZkqIDSVbHg~0;~ zR9B?x$u&UrR8Z7}Vp!f(tw2*0Zpnad8DLGe+gcmKpV|Hc+jZK0xAT;J+^b;0G&{gr zO_;xf`CBu5{K_LsE5nGs`HT9yK-(tCcxVcbbMKIWSP(`zlell_+jw)9?yyAd&A z6!%*m^NM1Je-GRew2BSv8m;vy5f{!f^Tg;`*Ewt^)4ZrvQk1`+HD*Q>&y}j27=O>= zjj7uu+E=zl>liJt7i-V3i~6^Tf2g~q)EnaeUGIwuaeY8sJ?<3}oDrFn7?^VJe?Cxl z-uGx`xfGax-j~96YIAy0)I;fclHQtjN~x^)efpl5)8iCYiW(tzW;WKJ5NlRQIyK-` zSge8}k`Y!(%!mkKW041Ji@~mv0yJLx0lj{PF38cO#DqvSSj>?~bHri}t**DPs9V{H zucz%&uFlOyoq8Z0+a?ityOdN$U~-DtD}jk(K9RD@$Zgy@9uqr{JLZmM71&TQqJ}+L z{Qa>5lh=8y%f;9(O{-5}by|_evPoqu>s4~X+dPvtgeN512$U{mPLN*&86zlWrRZEq zg)(W~4)*cRzI2J4x-O}GQsz2V(prRNT9AU(T0;x!NdDa|C(_+=fY%aNy5*?8(teFC ziRvx(t7NLTUnG-YKg%**GHvWjN15&#?w0YH?Uq?nM?xMjiP?UV_fF(1}Z94Ck4EAQt>Jjd0gb7rg{eVxev=q&0)ES9{kvS1e-_X!NX*X zL+NLIS4%GzES-q5Nr!33c5hsnh=xaZb@Z?CutT=L#+A|7knKLa?7`= $3004 ld de, CoreMinVersion CpHL(de) - ErrorIfCarry(Err.CoreMin) ; Raise ESP error if no response + ErrorIfCarry(Err.CoreMin) ; Raise minimum core error if < 3.00.04 SavedArgs equ $+1: ld hl, SMC ; Restore args ld a, h ; Check args length @@ -109,7 +109,45 @@ MakeCIPStart: WriteBuffer(PortStart, PortLen) WriteString(Cmd.Terminate, Cmd.TerminateLen) InitialiseESP: - PrintMsg(Messages.InitESP) + PrintMsg(Msg.InitESP) ; "Initialising WiFi..." + PrintMsg(Msg.SetBaud1) ; "Using 115200 baud, " + NextRegRead(Reg.VideoTiming) + and %111 + push af + ld d, a + ld e, 5 + mul + ex de, hl + add hl, Timings.Table + call PrintRst16 ; "VGA0/../VGA6/HDMI" + PrintMsg(Msg.SetBaud2) ; " timings" + pop af + add a,a + ld hl, Baud.Table + add hl, a + ld e, (hl) + inc hl + ld d, (hl) + ex de, hl ; HL now contains the prescalar baud value + ld (Prescaler), hl + ld a, %x0x1 x000 ; Choose ESP UART, and set most significant bits + ld (Prescaler+2), a ; of the 17-bit prescalar baud to zero, + ld bc, UART_Sel ; by writing to port 0x143B. + out (c), a + dec b ; Set baud by writing twice to port 0x143B + out (c), l ; Doesn't matter which order they are written, + out (c), h ; because bit 7 ensures that it is interpreted correctly. + inc b ; Write to UART control port 0x153B + + ld a, (Prescaler+2) ; Print three bytes written for debug purposes + call PrintAHexNoSpace + ld a, (Prescaler+1) + call PrintAHexNoSpace + ld a, (Prescaler) + call PrintAHexNoSpace + ld a, CR + rst 16 + ESPSend("ATE0") ErrorIfCarry(Err.ESPComms1) ; Raise ESP error if no response call ESPReceiveWaitOK @@ -122,24 +160,24 @@ InitialiseESP: call ESPReceiveWaitOK ErrorIfCarry(Err.ESPComms4) ; Raise ESP error if no response Connect: - PrintMsg(Messages.Connect1) + PrintMsg(Msg.Connect1) PrintBuffer(HostStart, HostLen) - PrintMsg(Messages.Connect2) + PrintMsg(Msg.Connect2) ESPSendBuffer(Buffer) ; This is AT+CIPSTART="TCP","",\r\n ErrorIfCarry(Err.ESPConn1) ; Raise ESP error if no connection call ESPReceiveWaitOK ErrorIfCarry(Err.ESPConn2) ; Raise ESP error if no response - //PrintMsg(Messages.Connected) + //PrintMsg(Msg.Connected) PrintAnyZone: ld hl, (ZoneStart) ld a, h or l jp z, PrintNoZone -PrintHasZone: PrintMsg(Messages.UsingTZ) +PrintHasZone: PrintMsg(Msg.UsingTZ) PrintBuffer(ZoneStart, ZoneLen) - PrintMsg(Messages.Connect2) + PrintMsg(Msg.Connect2) jp AfterPrintZone -PrintNoZone: PrintMsg(Messages.UsingTZDef) +PrintNoZone: PrintMsg(Msg.UsingTZDef) AfterPrintZone: MakeRequest: @@ -175,9 +213,9 @@ CalcPacketLength: ld hl, (RequestLen) call ConvertWordToAsc /*PrintCIPSend: - PrintMsg(Messages.Sending1) ; This has to happen before MakeCIPSend + PrintMsg(Msg.Sending1) ; This has to happen before MakeCIPSend PrintBuffer(WordStart, WordLen) ; Because they both use MsgBuffer - PrintMsg(Messages.Sending2)*/ + PrintMsg(Msg.Sending2)*/ MakeCIPSend: ld de, MsgBuffer WriteString(Cmd.CIPSEND, Cmd.CIPSENDLen) @@ -282,7 +320,7 @@ SaveDateTime: ld bc, ProtoTimeLen ldir PrintDateTime: - PrintMsg(Messages.Received) + PrintMsg(Msg.Received) ld hl, DateBufferInt ld bc, ProtoDateLen call PrintBufferLen @@ -294,7 +332,7 @@ PrintDateTime: ld a, CR rst 16 CallDotDate: - PrintMsg(Messages.Setting) + PrintMsg(Msg.Setting) call esxDOS.GetSetDrive ld hl, Files.Date ; HL not IX because we are in a dot command call esxDOS.fOpen ; Open .date file diff --git a/src/asm/msg.asm b/src/asm/msg.asm index 53178f4..d1ed456 100644 --- a/src/asm/msg.asm +++ b/src/asm/msg.asm @@ -1,7 +1,8 @@ ; msg.asm -Messages proc +Msg proc InitESP: db "Initialising WiFi...", CR, 0 + //TestVer: db "Test v", TestVersion, CR, 0 InitDone: db "Initialised", CR, 0 Connect1: db "Connecting to ", 0 Connect2: db "...", CR, 0 @@ -12,6 +13,8 @@ Messages proc Sending2: db " chars...", CR, 0 Received: db "Received ", 0 Setting: db "Setting date and time...", CR, 0 + SetBaud1: db "Using 115200 baud, ", 0 + SetBaud2: db " timings", CR, 0 pend Err proc @@ -62,6 +65,18 @@ Files proc Time: db "/dot/time", 0 pend +Timings: proc Table: + ; Text Index Notes + db "VGA0", 0 ; 0 Timing 0 + db "VGA1", 0 ; 1 Timing 1 + db "VGA2", 0 ; 2 Timing 2 + db "VGA3", 0 ; 3 Timing 3 + db "VGA4", 0 ; 4 Timing 4 + db "VGA5", 0 ; 5 Timing 5 + db "VGA6", 0 ; 6 Timing 6 + db "HDMI", 0 ; 7 Timing 7 +pend + PrintRst16 proc ei Loop: ld a, (hl) @@ -92,10 +107,10 @@ LastChar and %0 1111111 pend PrintHelp proc - ld hl, Msg + ld hl, HelpMsg call PrintRst16 jp Return.ToBasic -Msg: db "NXTP", CR +HelpMsg: db "NXTP", CR db "Set date/time from internet", CR, CR db "nxtp", CR db "Show help", CR, CR @@ -142,3 +157,28 @@ PrintBufferLen proc ret pend +PrintAHexNoSpace proc + //SafePrintStart() + ld b, a + //if DisableScroll + //ld a, 24 ; Set upper screen to not scroll + //ld (SCR_CT), a ; for another 24 rows of printing + //ld a, b + //endif + and $F0 + swapnib + call Print + ld a, b + and $0F + call Print + //SafePrintEnd() + ret +Print: cp 10 + ld c, '0' + jr c, Add + ld c, 'A'-10 +Add: add a, c + rst 16 + ret +pend + diff --git a/src/asm/vars.asm b/src/asm/vars.asm index fbe18cb..f99255e 100644 --- a/src/asm/vars.asm +++ b/src/asm/vars.asm @@ -14,6 +14,7 @@ WordStart: ds 5 WordLen: dw $0000 ResponseStart: dw $0000 ResponseLen: dw $0000 +Prescaler: ds 3 Buffer: ds 256 BufferLen equ $-Buffer MsgBuffer: ds 256 diff --git a/src/asm/version.asm b/src/asm/version.asm index d75cc4b..0c37107 100644 --- a/src/asm/version.asm +++ b/src/asm/version.asm @@ -1,38 +1,38 @@ ; version.asm ; ; Auto-generated by ZXVersion.exe -; On 19 Jan 2020 at 18:01 +; On 20 Jan 2020 at 12:31 BuildNo macro() - db "56" + db "57" mend -BuildNoValue equ "56" -BuildNoWidth equ 0 + FW5 + FW6 +BuildNoValue equ "57" +BuildNoWidth equ 0 + FW5 + FW7 BuildDate macro() - db "19 Jan 2020" + db "20 Jan 2020" mend -BuildDateValue equ "19 Jan 2020" -BuildDateWidth equ 0 + FW1 + FW9 + FWSpace + FWJ + FWa + FWn + FWSpace + FW2 + FW0 + FW2 + FW0 +BuildDateValue equ "20 Jan 2020" +BuildDateWidth equ 0 + FW2 + FW0 + FWSpace + FWJ + FWa + FWn + FWSpace + FW2 + FW0 + FW2 + FW0 BuildTime macro() - db "18:01" + db "12:31" mend -BuildTimeValue equ "18:01" -BuildTimeWidth equ 0 + FW1 + FW8 + FWColon + FW0 + FW1 +BuildTimeValue equ "12:31" +BuildTimeWidth equ 0 + FW1 + FW2 + FWColon + FW3 + FW1 BuildTimeSecs macro() - db "18:01:02" + db "12:31:43" mend -BuildTimeSecsValue equ "18:01:02" -BuildTimeSecsWidth equ 0 + FW1 + FW8 + FWColon + FW0 + FW1 + FWColon + FW0 + FW2 +BuildTimeSecsValue equ "12:31:43" +BuildTimeSecsWidth equ 0 + FW1 + FW2 + FWColon + FW3 + FW1 + FWColon + FW4 + FW3