diff --git a/Main/App.config b/Main/App.config
index 731f6de..329b00c 100644
--- a/Main/App.config
+++ b/Main/App.config
@@ -1,6 +1,21 @@
 <?xml version="1.0" encoding="utf-8" ?>
 <configuration>
+    <configSections>
+        <sectionGroup name="userSettings" type="System.Configuration.UserSettingsGroup, System, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089" >
+            <section name="FoenixIDE.Simulator.Properties.Settings" type="System.Configuration.ClientSettingsSection, System, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089" allowExeDefinition="MachineToLocalUser" requirePermission="false" />
+        </sectionGroup>
+    </configSections>
     <startup> 
         <supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.6.1" />
     </startup>
+<userSettings>
+        <FoenixIDE.Simulator.Properties.Settings>
+                <setting name="Autorun" serializeAs="String">
+                        <value>True</value>
+                </setting>
+                <setting name="BoardRevision" serializeAs="String">
+                        <value>C</value>
+                </setting>
+        </FoenixIDE.Simulator.Properties.Settings>
+    </userSettings>
 </configuration>
\ No newline at end of file
diff --git a/Main/FoenixIDE.csproj b/Main/FoenixIDE.csproj
index 9003d28..1b7d52e 100644
--- a/Main/FoenixIDE.csproj
+++ b/Main/FoenixIDE.csproj
@@ -335,10 +335,12 @@
   </ItemGroup>
   <ItemGroup>
     <Content Include="icon.ico" />
+    <None Include="Resources\kernel_U_Plus.hex" />
     <None Include="UI\Images\memory-btn.png" />
     <None Include="UI\Images\delete-btn.png" />
     <None Include="Resources\foenix-96x96.png" />
     <None Include="Resources\DeleteButton.png" />
+    <None Include="Resources\kernel_U_Plus.lst" />
     <Content Include="Resources\PET-ASCII.png" />
   </ItemGroup>
   <ItemGroup>
diff --git a/Main/Properties/AssemblyInfo.cs b/Main/Properties/AssemblyInfo.cs
index dc323fd..c14e21d 100644
--- a/Main/Properties/AssemblyInfo.cs
+++ b/Main/Properties/AssemblyInfo.cs
@@ -10,7 +10,7 @@
 [assembly: AssemblyConfiguration("")]
 [assembly: AssemblyCompany("C256 Foenix")]
 [assembly: AssemblyProduct("FoenixIDE")]
-[assembly: AssemblyCopyright("Copyright ©  2020")]
+[assembly: AssemblyCopyright("Copyright ©  2020-2021")]
 [assembly: AssemblyTrademark("")]
 [assembly: AssemblyCulture("")]
 
@@ -32,5 +32,5 @@
 // You can specify all the values or you can default the Build and Revision Numbers
 // by using the '*' as shown below:
 // [assembly: AssemblyVersion("1.0.*")]
-[assembly: AssemblyVersion("0.5.4.2")]
-[assembly: AssemblyFileVersion("0.5.4.2")]
+[assembly: AssemblyVersion("0.5.4.3")]
+[assembly: AssemblyFileVersion("0.5.4.3")]
diff --git a/Main/Properties/Resources.Designer.cs b/Main/Properties/Resources.Designer.cs
index 89e644a..2081b4d 100644
--- a/Main/Properties/Resources.Designer.cs
+++ b/Main/Properties/Resources.Designer.cs
@@ -70,6 +70,40 @@ internal static System.Drawing.Bitmap delete_btn {
             }
         }
         
+        /// <summary>
+        ///   Looks up a localized resource of type System.Byte[].
+        /// </summary>
+        internal static byte[] kernel_U_Plus_Hex {
+            get {
+                object obj = ResourceManager.GetObject("kernel_U_Plus_Hex", resourceCulture);
+                return ((byte[])(obj));
+            }
+        }
+        
+        /// <summary>
+        ///   Looks up a localized string similar to 
+        ///; 64tass Turbo Assembler Macro V1.54.1900 listing file
+        ///; 64tass --m65816 -D TARGET=1 -D TARGET_SYS=3 --long-address --flat -b -o kernel_U_Plus.bin --list kernel_U_Plus.lst --labels=kernel_U_Plus.lbl src\kernel.asm
+        ///; Fri Feb 19 14:45:31 2021
+        ///
+        ///;Offset	;PC	;Hex		;Monitor	;Source
+        ///
+        ///;******  Command line definitions
+        ///
+        ///=1						TARGET=1
+        ///=3						TARGET_SYS=3
+        ///
+        ///;******  Processing input file: src\kernel.asm
+        ///
+        ///=0						TEST_KEYBOARD = 0 ; This is to enable the ScreenOutput
+        ///=1						SYS_C256_FMX = 1          [rest of string was truncated]&quot;;.
+        /// </summary>
+        internal static string kernel_U_Plus_Lst {
+            get {
+                return ResourceManager.GetString("kernel_U_Plus_Lst", resourceCulture);
+            }
+        }
+        
         /// <summary>
         ///   Looks up a localized resource of type System.Drawing.Bitmap.
         /// </summary>
diff --git a/Main/Properties/Resources.resx b/Main/Properties/Resources.resx
index 0a7243d..e35ac78 100644
--- a/Main/Properties/Resources.resx
+++ b/Main/Properties/Resources.resx
@@ -121,6 +121,12 @@
   <data name="delete_btn" type="System.Resources.ResXFileRef, System.Windows.Forms">
     <value>..\UI\Images\delete-btn.png;System.Drawing.Bitmap, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a</value>
   </data>
+  <data name="kernel_U_Plus_Hex" type="System.Resources.ResXFileRef, System.Windows.Forms">
+    <value>..\Resources\kernel_U_Plus.hex;System.Byte[], mscorlib, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>
+  </data>
+  <data name="kernel_U_Plus_Lst" type="System.Resources.ResXFileRef, System.Windows.Forms">
+    <value>..\Resources\kernel_U_Plus.lst;System.String, mscorlib, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089;Windows-1252</value>
+  </data>
   <data name="memory_btn" type="System.Resources.ResXFileRef, System.Windows.Forms">
     <value>..\UI\Images\memory-btn.png;System.Drawing.Bitmap, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a</value>
   </data>
diff --git a/Main/Properties/Settings.Designer.cs b/Main/Properties/Settings.Designer.cs
index d35d63b..7c29f57 100644
--- a/Main/Properties/Settings.Designer.cs
+++ b/Main/Properties/Settings.Designer.cs
@@ -22,5 +22,29 @@ public static Settings Default {
                 return defaultInstance;
             }
         }
+        
+        [global::System.Configuration.UserScopedSettingAttribute()]
+        [global::System.Diagnostics.DebuggerNonUserCodeAttribute()]
+        [global::System.Configuration.DefaultSettingValueAttribute("True")]
+        public bool Autorun {
+            get {
+                return ((bool)(this["Autorun"]));
+            }
+            set {
+                this["Autorun"] = value;
+            }
+        }
+        
+        [global::System.Configuration.UserScopedSettingAttribute()]
+        [global::System.Diagnostics.DebuggerNonUserCodeAttribute()]
+        [global::System.Configuration.DefaultSettingValueAttribute("C")]
+        public string BoardRevision {
+            get {
+                return ((string)(this["BoardRevision"]));
+            }
+            set {
+                this["BoardRevision"] = value;
+            }
+        }
     }
 }
diff --git a/Main/Properties/Settings.settings b/Main/Properties/Settings.settings
index 3964565..b217e06 100644
--- a/Main/Properties/Settings.settings
+++ b/Main/Properties/Settings.settings
@@ -1,7 +1,12 @@
 <?xml version='1.0' encoding='utf-8'?>
-<SettingsFile xmlns="http://schemas.microsoft.com/VisualStudio/2004/01/settings" CurrentProfile="(Default)">
-  <Profiles>
-    <Profile Name="(Default)" />
-  </Profiles>
-  <Settings />
-</SettingsFile>
+<SettingsFile xmlns="http://schemas.microsoft.com/VisualStudio/2004/01/settings" CurrentProfile="(Default)" GeneratedClassNamespace="FoenixIDE.Simulator.Properties" GeneratedClassName="Settings">
+  <Profiles />
+  <Settings>
+    <Setting Name="Autorun" Type="System.Boolean" Scope="User">
+      <Value Profile="(Default)">True</Value>
+    </Setting>
+    <Setting Name="BoardRevision" Type="System.String" Scope="User">
+      <Value Profile="(Default)">C</Value>
+    </Setting>
+  </Settings>
+</SettingsFile>
\ No newline at end of file
diff --git a/Main/Resources/kernel_U_Plus.hex b/Main/Resources/kernel_U_Plus.hex
new file mode 100644
index 0000000..31a911c
--- /dev/null
+++ b/Main/Resources/kernel_U_Plus.hex
@@ -0,0 +1,4677 @@
+:020000040038C2
+:1800000000A0AF4C0064003800400000A0AF000000000F000080FFFE96
+:020000040000FA
+:06FF000018FB5C0010007C
+:0BFF1000C2308B0B48DA5A5C0810006E
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diff --git a/Main/Resources/kernel_U_Plus.lst b/Main/Resources/kernel_U_Plus.lst
new file mode 100644
index 0000000..360cc59
--- /dev/null
+++ b/Main/Resources/kernel_U_Plus.lst
@@ -0,0 +1,20542 @@
+
+; 64tass Turbo Assembler Macro V1.54.1900 listing file
+; 64tass --m65816 -D TARGET=1 -D TARGET_SYS=3 --long-address --flat -b -o kernel_U_Plus.bin --list kernel_U_Plus.lst --labels=kernel_U_Plus.lbl src\kernel.asm
+; Fri Feb 19 14:45:31 2021
+
+;Offset	;PC	;Hex		;Monitor	;Source
+
+;******  Command line definitions
+
+=1						TARGET=1
+=3						TARGET_SYS=3
+
+;******  Processing input file: src\kernel.asm
+
+=0						TEST_KEYBOARD = 0 ; This is to enable the ScreenOutput
+=1						SYS_C256_FMX = 1                            ; The target system is the C256 Foenix FMX
+=2						SYS_C256_U = 2                              ; The target system is the C256 Foenix U With 2Megs of Code Memory
+=3						SYS_C256_U_PLUS = 3                         ; The target system is the C256 Foenix U With 4Megs of Code Memory
+=1						TARGET_FLASH = 1                            ; The code is being assembled for Flash
+=2						TARGET_RAM = 2                              ; The code is being assembled for RAM
+=0						START_OF_FLASH := 0
+=0						START_OF_KERNEL := 0
+=0						START_OF_BASIC := 0
+=0						START_OF_CREDITS := 0
+=0						START_OF_SPLASH := 0
+=0						START_OF_FONT := 0
+=$380000					  START_OF_FLASH := $380000                   ; The Foenix FMX Flash starts at $380000
+=$390400					  START_OF_KERNEL := $390400                  ; The kernel itself starts at $390400
+=$3a0000					  START_OF_BASIC := $3A0000                   ; The BASIC flash code starts at $3A0000
+=$3b0000					  START_OF_CREDITS := $3B0000                 ; The credits screen starts at $3B0000
+=$3e0000					  START_OF_SPLASH := $3E0000                  ; SplashScreen Code and Data $3E0000
+=$3f0000					  START_OF_FONT := $3F0000                    ; The font starts at $3F0000
+
+;******  Processing file: src\Includes/macros_inc.asm
+
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/characters.asm
+
+=$01						CHAR_CTRL_A = $01   ; CTRL-A (move to start of line)
+=$03						CHAR_CTRL_C = $03   ; CTRL-C
+=$05						CHAR_CTRL_E = $05   ; CTRL-E (move to end of line)
+=$08						CHAR_BS = $08       ; Backspace (delete character to the left of the cursor)
+=$09						CHAR_TAB = $09      ; TAB (moves cursor to next tabulated column)
+=$0a						CHAR_LF = $0A       ; Line feed
+=$0d						CHAR_CR = $0D       ; Carriage return
+=$0f						CHAR_INS = $0F      ; Insert a space at the cursor
+=$11						CHAR_UP = $11       ; Up arrow
+=$1d						CHAR_RIGHT = $1D    ; Right arrow
+=$20						CHAR_SP = $20       ; Space
+=$91						CHAR_DOWN = $91     ; Down arrow
+=$9d						CHAR_LEFT = $9D     ; Left arrow
+=$7f						CHAR_DEL = $7F      ; Delete key (delete the character at the cursor)
+=$81						CHAR_F1 = $81       ; Function keys
+=$82						CHAR_F2 = $82
+=$83						CHAR_F3 = $83
+=$84						CHAR_F4 = $84
+=$85						CHAR_F5 = $85
+=$86						CHAR_F6 = $86
+=$87						CHAR_F7 = $87
+=$88						CHAR_F8 = $88
+=$89						CHAR_F9 = $89
+=$8a						CHAR_F10 = $8A
+=$8b						CHAR_F11 = $8B
+=$8c						CHAR_F12 = $8C
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/simulator_inc.asm
+
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/page_00_inc.asm
+
+=$000000					BANK0_BEGIN      = $000000 ;Start of bank 0 and Direct page
+=$000000					TMPPTR1          = $000000 ; 4 byte temporary pointer
+=$000004					TMPPTR2          = $000004 ; 4 byte temporary pointer
+=$000008					KRNL_BOOT_MENU_K = $000008 ; Keyboard Tap in Boot Menu
+=$000008					OPL2_ADDY_PTR_LO = $000008 ; THis Points towards the Instruments Database
+=$000009					OPL2_ADDY_PTR_MD = $000009
+=$00000a					OPL2_ADDY_PTR_HI = $00000A ;
+=$00000c					SCREENBEGIN      = $00000C ;3 Bytes Start of screen in video RAM. This is the upper-left corrner of the current video page being written to. This may not be what's being displayed by VICKY. Update this if you change VICKY's display page.
+=$00000f					COLS_VISIBLE     = $00000F ;2 Bytes Columns visible per screen line. A virtual line can be longer than displayed, up to COLS_PER_LINE long. Default = 80
+=$000011					COLS_PER_LINE    = $000011 ;2 Bytes Columns in memory per screen line. A virtual line can be this long. Default=128
+=$000013					LINES_VISIBLE    = $000013 ;2 Bytes The number of rows visible on the screen. Default=25
+=$000015					LINES_MAX        = $000015 ;2 Bytes The number of rows in memory for the screen. Default=64
+=$000017					CURSORPOS        = $000017 ;3 Bytes The next character written to the screen will be written in this location.
+=$00001a					CURSORX          = $00001A ;2 Bytes This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
+=$00001c					CURSORY          = $00001C ;2 Bytes This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
+=$00001e					CURCOLOR         = $00001E ;1 Byte Color of next character to be printed to the screen.
+=$00001f					COLORPOS         = $00001F ;3 Byte address of cursor's position in the color matrix
+=$000022					STACKBOT         = $000022 ;2 Bytes Lowest location the stack should be allowed to write to. If SP falls below this value, the runtime should generate STACK OVERFLOW error and abort.
+=$000024					STACKTOP         = $000024 ;2 Bytes Highest location the stack can occupy. If SP goes above this value, the runtime should generate STACK OVERFLOW error and abort.
+=$000026					OPL2_OPERATOR    = $000026 ;
+=$000027					OPL2_CHANNEL     = $000027 ;
+=$000028					OPL2_REG_REGION  = $000028 ; Offset to the Group of Registers
+=$00002a					OPL2_REG_OFFSET  = $00002A ; 2 Bytes (16Bits)
+=$00002c					OPL2_IND_ADDY_LL = $00002C ; 2 Bytes Reserved (Only need 3)
+=$00002e					OPL2_IND_ADDY_HL = $00002E ; 2 Bytes Reserved (Only need 3)
+=$000030					OPL2_NOTE        = $000030 ; 1 Byte
+=$000031					OPL2_OCTAVE      = $000031 ; 1 Byte
+=$000032					OPL2_PARAMETER0  = $000032 ; 1 Byte - Key On/Feedback
+=$000033					OPL2_PARAMETER1  = $000033 ; 1 Byte
+=$000034					OPL2_PARAMETER2  = $000034 ; 1 Byte
+=$000035					OPL2_PARAMETER3  = $000035 ; 1 Byte
+=$000036					OPL2_LOOP        = $000036 ;
+=$000036					OPL2_BLOCK       = $000036
+=$000038					SDCARD_FILE_PTR  = $000038 ; 3 Bytes Pointer to Filename to open
+=$00003c					SDCARD_BYTE_NUM  = $00003C ; 2Bytes
+=$00003f					SDCARD_PRSNT_MNT = $00003F ; 1 Byte, Indicate that the SDCard is Present and that it is Mounted
+=$000040					BM_CLEAR_SCRN_X  = $000040
+=$000042					BM_CLEAR_SCRN_Y  = $000042
+=$000040					RAD_STARTLINE    = $000040 ; 1 Byte
+=$000041					RAD_PATTERN_IDX  = $000041 ; 1 Byte
+=$000042					RAD_LINE         = $000042 ; 1 Byte
+=$000043					RAD_LINENUMBER   = $000043 ; 1 Byte
+=$000044					RAD_CHANNEL_NUM  = $000044 ; 1 Byte
+=$000045					RAD_ISLASTCHAN   = $000045 ; 1 Byte
+=$000046					RAD_Y_POINTER    = $000046 ; 2 Bytes
+=$000048					RAD_TICK         = $000048
+=$00004a					RAD_CHANNEL_DATA = $00004A ; 2 Bytes
+=$00004c					RAD_CHANNE_EFFCT = $00004C
+=$00004d					RAD_TEMP         = $00004D
+=$000050					RAD_ADDR         = $000050 ; 3 bytes to avoid OPL2 errors.
+=$000053					RAD_PATTRN       = $000053 ; 1 bytes - offset to patter
+=$000054					RAD_PTN_DEST     = $000054 ; 3 bytes - where to write the pattern data
+=$000057					RAD_CHANNEL      = $000057 ; 2 bytes - 0 to 8
+=$000059					RAD_LAST_NOTE    = $000059 ; 1 if this is the last note
+=$00005a					RAD_LINE_PTR     = $00005A ; 2 bytes - offset to memory location
+=$000040					BMP_X_SIZE       = $000040 ; 2 Bytes
+=$000042					BMP_Y_SIZE       = $000042 ; 2 Bytes
+=$000044					BMP_PRSE_SRC_PTR = $000044 ; 3 Bytes
+=$000048					BMP_PRSE_DST_PTR = $000048 ; 3 Bytes
+=$00004c					BMP_COLOR_PALET  = $00004C ; 2 Bytes
+=$00004e					SCRN_X_STRIDE    = $00004E ; 2 Bytes, Basically How many Pixel Accross in Bitmap Mode
+=$000050					BMP_FILE_SIZE    = $000050 ; 4 Bytes
+=$000054					BMP_POSITION_X   = $000054 ; 2 Bytes Where, the BMP will be position on the X Axis
+=$000056					BMP_POSITION_Y   = $000056 ; 2 Bytes Where, the BMP will be position on the Y Axis
+=$000058					BMP_PALET_CHOICE = $000058 ;
+=$0000e0					MOUSE_PTR        = $0000E0
+=$0000e1					MOUSE_POS_X_LO   = $0000E1
+=$0000e2					MOUSE_POS_X_HI   = $0000E2
+=$0000e3					MOUSE_POS_Y_LO   = $0000E3
+=$0000e4					MOUSE_POS_Y_HI   = $0000E4
+=$0000f0					USER_TEMP        = $0000F0 ;32 Bytes Temp space for user programs
+=$000100					GAVIN_BLOCK      = $000100 ;256 Bytes Gavin reserved, overlaps debugging registers at $1F0
+=$000140					INT_CONTROLLER   = $000140 ; $000140...$00015F Interrupt Controller
+=$000160					TIMER_CONTROLLER = $000160 ; $000160...$00017F Timer0/Timer1/Timer2 Block
+=$000160					TIMER_CTRL_REGLL = $000160 ;
+=$000161					TIMER_CTRL_REGLH = $000161 ;
+=$000162					TIMER_CTRL_REGHL = $000162 ;
+=$000163					TIMER_CTRL_REGHH = $000163 ;
+=$000240					CPU_REGISTERS    = $000240 ; Byte
+=$000240					CPUPC            = $000240 ;2 Bytes Program Counter (PC)
+=$000242					CPUPBR           = $000242 ;2 Bytes Program Bank Register (K)
+=$000244					CPUA             = $000244 ;2 Bytes Accumulator (A)
+=$000246					CPUX             = $000246 ;2 Bytes X Register (X)
+=$000248					CPUY             = $000248 ;2 Bytes Y Register (Y)
+=$00024a					CPUSTACK         = $00024A ;2 Bytes Stack Pointer (S)
+=$00024c					CPUDP            = $00024C ;2 Bytes Direct Page Register (D)
+=$00024e					CPUDBR           = $00024E ;1 Byte  Data Bank Register (B)
+=$00024f					CPUFLAGS         = $00024F ;1 Byte  Flags (P)
+=$000250					MONITOR_VARS     = $000250 ; Byte  MONITOR Variables. BASIC variables may overlap this space
+=$000250					MCMDADDR         = $000250 ;3 Bytes Address of the current line of text being processed by the command parser. Can be in display memory or a variable in memory. MONITOR will parse up to MTEXTLEN characters or to a null character.
+=$000253					MCMP_TEXT        = $000253 ;3 Bytes Address of symbol being evaluated for COMPARE routine
+=$000256					MCMP_LEN         = $000256 ;2 Bytes Length of symbol being evaluated for COMPARE routine
+=$000258					MCMD             = $000258 ;3 Bytes Address of the current command/function string
+=$00025b					MCMD_LEN         = $00025B ;2 Bytes Length of the current command/function string
+=$00025d					MARG1            = $00025D ;4 Bytes First command argument. May be data or address, depending on command
+=$000261					MARG2            = $000261 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$000265					MARG3            = $000265 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$000269					MARG4            = $000269 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$00026d					MARG5            = $00026D ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$000271					MARG6            = $000271 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$000275					MARG7            = $000275 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$000279					MARG8            = $000279 ;4 Bytes First command argument. May be data or address, depending on command. Data is 32-bit number. Address is 24-bit address and 8-bit length.
+=$000300					LOADFILE_VARS    = $000300 ; Byte
+=$000300					LOADFILE_NAME    = $000300 ;3 Bytes (addr) Name of file to load. Address in Data Page
+=$000303					LOADFILE_LEN     = $000303 ;1 Byte  Length of filename. 0=Null Terminated
+=$000304					LOADPBR          = $000304 ;1 Byte  First Program Bank of loaded file ($05 segment)
+=$000305					LOADPC           = $000305 ;2 Bytes Start address of loaded file ($05 segment)
+=$000307					LOADDBR          = $000307 ;1 Byte  First data bank of loaded file ($06 segment)
+=$000308					LOADADDR         = $000308 ;2 Bytes FIrst data address of loaded file ($06 segment)
+=$00030a					LOADFILE_TYPE    = $00030A ;3 Bytes (addr) File type string in loaded data file. Actual string data will be in Bank 1. Valid values are BIN, PRG, P16
+=$00030d					BLOCK_LEN        = $00030D ;2 Bytes Length of block being loaded
+=$00030f					BLOCK_ADDR       = $00030F ;2 Bytes (temp) Address of block being loaded
+=$000311					BLOCK_BANK       = $000311 ;1 Byte  (temp) Bank of block being loaded
+=$000312					BLOCK_COUNT      = $000312 ;2 Bytes (temp) Counter of bytes read as file is loaded
+=$000300					FDC_DRIVE        = $000300 ;1 byte - The number of the selected drive
+=$000301					FDC_HEAD         = $000301 ;1 byte - The head number (0 or 1)
+=$000302					FDC_CYLINDER     = $000302 ;1 byte - The cylinder number
+=$000303					FDC_SECTOR       = $000303 ;1 byte - The sector number
+=$000304					FDC_SECTOR_SIZE  = $000304 ;1 byte - The sector size code (2 = 512)
+=$000305					FDC_SECPERTRK    = $000305 ;1 byte - The number of sectors per track (18 for 1.44 MB floppy)
+=$000306					FDC_ST0          = $000306 ;1 byte - Status Register 0
+=$000307					FDC_ST1          = $000307 ;1 byte - Status Register 1
+=$000308					FDC_ST2          = $000308 ;1 byte - Status Register 2
+=$000309					FDC_ST3          = $000309 ;1 byte - Status Register 3
+=$00030a					FDC_PCN          = $00030A ;1 byte - Present Cylinder Number
+=$00030b					FDC_STATUS       = $00030B ;1 byte - Status of what we think is going on with the FDC:
+=$00030c					DIVIDEND         = $00030C ;4 bytes - Dividend for 32-bit division
+=$000310					DIVISOR          = $000310 ;4 bytes - Divisor for 32-bit division
+=$000314					REMAINDER        = $000314 ;4 bytes - Remainder for 32-bit division
+=$000320					SDOS_VARIABLES   = $000320
+=$000320					BIOS_STATUS      = $000320      ; 1 byte - Status of any BIOS operation
+=$000321					BIOS_DEV         = $000321      ; 1 byte - Block device number for block operations
+=$000322					BIOS_LBA         = $000322      ; 4 bytes - Address of block to read/write (this is the physical block, w/o reference to partition)
+=$000326					BIOS_BUFF_PTR    = $000326      ; 4 bytes - 24-bit pointer to memory for read/write operations
+=$00032a					BIOS_FIFO_COUNT  = $00032A      ; 2 bytes - The number of bytes read on the last block read
+=$00032c					BIOS_FLAGS       = $00032C      ; 1 byte - Flags for various BIOSy things:
+=$00032d					BIOS_TIMER       = $00032D      ; 1 byte - the number of 1/60 ticks for a time out
+=$00032e					DOS_STATUS       = $00032E      ; 1 byte - The error code describing any error with file access
+=$000330					DOS_CLUS_ID      = $000330      ; 4 bytes - The cluster desired for a DOS operation
+=$000338					DOS_DIR_PTR      = $000338      ; 4 bytes - Pointer to a directory entry (assumed to be within DOS_SECTOR)
+=$00033c					DOS_BUFF_PTR     = $00033C      ; 4 bytes - A pointer for DOS cluster read/write operations
+=$000340					DOS_FD_PTR       = $000340      ; 4 bytes - A pointer to a file descriptor
+=$000344					DOS_FAT_LBA      = $000344      ; 4 bytes - The LBA for a sector of the FAT we need to read/write
+=$000348					DOS_TEMP         = $000348      ; 4 bytes - Temporary storage for DOS operations
+=$00034c					DOS_FILE_SIZE    = $00034C      ; 4 bytes - The size of a file
+=$000350					DOS_SRC_PTR      = $000350      ; 4 bytes - Pointer for transferring data
+=$000354					DOS_DST_PTR      = $000354      ; 4 bytes - Pointer for transferring data
+=$000358					DOS_END_PTR      = $000358      ; 4 bytes - Pointer to the last byte to save
+=$00035c					DOS_RUN_PTR      = $00035C      ; 4 bytes - Pointer for starting a loaded program
+=$000360					DOS_RUN_PARAM    = $000360      ; 4 bytes - Pointer to the ASCIIZ string for arguments in loading a program
+=$000364					DOS_STR1_PTR     = $000364      ; 4 bytes - pointer to a string
+=$000368					DOS_STR2_PTR     = $000368      ; 4 bytes - pointer to a string
+=$00036b					DOS_SCRATCH      = $00036B      ; 4 bytes - general purpose short term storage
+=$000400					DOS_PATH_BUFF    = $000400      ; 256 bytes - A buffer for path names
+=$000500					FDC_PARAMETERS   = $000500      ; 16 bytes - a buffer of parameter data for the FDC
+=$000510					FDC_RESULTS      = $000510      ; 16 bytes - Buffer for results of FDC commands
+=$000530					FDC_PARAM_NUM    = $000530      ; 1 byte - The number of parameters to send to the FDC (including command)
+=$000532					FDC_RESULT_NUM   = $000532      ; 1 byte - The number of results expected
+=$000533					FDC_EXPECT_DAT   = $000533      ; 1 byte - 0 = the command expects no data, otherwise expects data
+=$000534					FDC_CMD_RETRY    = $000534      ; 1 byte - a retry counter for commands
+=$000700					CURRUART         = $000700 ; 3-bytes: the base address of the current UART
+=$000703					CHAN_OUT         = $000703 ; 1-byte: the number of the current output channel (for PUTC, etc.)
+=$000704					CHAN_IN          = $000704 ; 1-byte: the number of the current input channel (for GETCH, etc.)
+=$000705					TIMERFLAGS       = $000705 ; 1-byte: flags to indicate that one of the timer interupts has triggered
+=$80						TIMER0TRIGGER    = $80
+=$40						TIMER1TRIGGER    = $40
+=$20						TIMER2TRIGGER    = $20
+=$000f00					KEY_BUFFER       = $000F00 ; 64 Bytes keyboard buffer
+=$0080						KEY_BUFFER_SIZE  = $0080   ;128 Bytes (constant) keyboard buffer length
+=$000f7f					KEY_BUFFER_END   = $000F7F ;  1 Byte  Last byte of keyboard buffer
+=$000f83					KEY_BUFFER_CMD   = $000F83 ;  1 Byte  Indicates the Command Process Status
+=$000f84					COMMAND_SIZE_STR = $000F84 ;  1 Byte
+=$000f86					COMMAND_COMP_TMP = $000F86 ;  2 Bytes
+=$000f87					KEYBOARD_SC_FLG  = $000F87 ;  1 Bytes that indicate the Status of Left Shift, Left CTRL, Left ALT, Right Shift
+=$000f88					KEYBOARD_SC_TMP  = $000F88 ;  1 Byte, Interrupt Save Scan Code while Processing
+=$000f89					KEYBOARD_LOCKS   = $000F89 ;  1 Byte, the status of the various lock keys
+=$000f8a					KEYFLAG          = $000F8A ;  1 Byte, flag to indicate if CTRL-C has been pressed
+=$000f8b					KEY_BUFFER_RPOS  = $000F8B ;  2 Byte, position of the character to read from the KEY_BUFFER
+=$000f8d					KEY_BUFFER_WPOS  = $000F8D ;  2 Byte, position of the character to write to the KEY_BUFFER
+=$001000					KERNEL_JMP_BEGIN = $001000 ; Reserved for the Kernel jump table
+=$001fff					KERNEL_JMP_END   = $001FFF
+=$002000					TEST_BEGIN       = $002000 ;28672 Bytes Test/diagnostic code for prototype.
+=$007fff					TEST_END         = $007FFF ;0 Byte
+=$008000					STACK_BEGIN      = $008000 ;32512 Bytes The default beginning of stack space
+=$00feff					STACK_END        = $00FEFF ;0 Byte  End of stack space. Everything below this is I/O space
+=$38ff00					        ISR_BEGIN        = $38FF00 ; Byte  Beginning of CPU vectors in Direct page
+=$38ff00					        HRESET           = $38FF00 ;16 Bytes Handle RESET asserted. Reboot computer and re-initialize the kernel.
+=$38ff10					        HCOP             = $38FF10 ;16 Bytes Handle the COP instruction. Program use; not used by OS
+=$38ff20					        HBRK             = $38FF20 ;16 Bytes Handle the BRK instruction. Returns to BASIC Ready prompt.
+=$38ff30					        HABORT           = $38FF30 ;16 Bytes Handle ABORT asserted. Return to Ready prompt with an error message.
+=$38ff40					        HNMI             = $38FF40 ;32 Bytes Handle NMI
+=$38ff60					        HIRQ             = $38FF60 ;32 Bytes Handle IRQ
+=$38ff80					        Unused_FF80      = $38FF80 ;End of direct page Interrrupt handlers
+=$38ffe0					        VECTORS_BEGIN    = $38FFE0 ;0 Byte  Interrupt vectors
+=$38ffe0					        JMP_READY        = $38FFE0 ;4 Bytes Jumps to ROM READY routine. Modified whenever alternate command interpreter is loaded.
+=$38ffe4					        VECTOR_COP       = $38FFE4 ;2 Bytes Native COP Interrupt vector
+=$38ffe6					        VECTOR_BRK       = $38FFE6 ;2 Bytes Native BRK Interrupt vector
+=$38ffe8					        VECTOR_ABORT     = $38FFE8 ;2 Bytes Native ABORT Interrupt vector
+=$38ffea					        VECTOR_NMI       = $38FFEA ;2 Bytes Native NMI Interrupt vector
+=$38ffec					        VECTOR_RESET     = $38FFEC ;2 Bytes Unused (Native RESET vector)
+=$38ffee					        VECTOR_IRQ       = $38FFEE ;2 Bytes Native IRQ Vector
+=$38fff0					        RETURN           = $38FFF0 ;4 Bytes RETURN key handler. Points to BASIC or MONITOR subroutine to execute when RETURN is pressed.
+=$38fff4					        VECTOR_ECOP      = $38FFF4 ;2 Bytes Emulation mode interrupt handler
+=$38fff6					        VECTOR_EBRK      = $38FFF6 ;2 Bytes Emulation mode interrupt handler
+=$38fff8					        VECTOR_EABORT    = $38FFF8 ;2 Bytes Emulation mode interrupt handler
+=$38fffa					        VECTOR_ENMI      = $38FFFA ;2 Bytes Emulation mode interrupt handler
+=$38fffc					        VECTOR_ERESET    = $38FFFC ;2 Bytes Emulation mode interrupt handler
+=$38fffe					        VECTOR_EIRQ      = $38FFFE ;2 Bytes Emulation mode interrupt handler
+=$400000					        VECTORS_END      = $400000 ;*End of vector space
+=$00ffff					BANK0_END        = $00FFFF ;End of Bank 00 and Direct page
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/page_00_data.asm
+
+>380000		00 a0 af			                .long $AFA000       ; SCREENBEGIN, 3 bytes, Start of screen in video RAM. This is the upper-left corrner of the current video page being written to. This may not be what's being displayed by VICKY. Update this if you change VICKY's display page.
+>380003		4c 00				                .word 76            ; COLS_VISIBLE, 2 bytes, Columns visible per screen line. A virtual line can be longer than displayed, up to COLS_PER_LINE long. Default = 80
+>380005		64 00				                .word 100           ; COLS_PER_LINE, 2 bytes, Columns in memory per screen line. A virtual line can be this long. Default=128
+>380007		38 00				                .word 56            ; LINES_VISIBLE, 2 bytes, The number of rows visible on the screen. Default=25
+>380009		40 00				                .word 64            ; LINES_MAX, 2 bytes, The number of rows in memory for the screen. Default=64
+>38000b		00 a0 af			                .long $AFA000       ; CURSORPOS, 3 bytes, The next character written to the screen will be written in this location.
+>38000e		00 00				                .word 0             ; CURSORX, 2 bytes, This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
+>380010		00 00				                .word 0             ; CURSORY, 2 bytes, This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
+>380012		0f				                .byte $0F           ; CURCOLOR, 2 bytes, Color of next character to be printed to the screen.
+>380013		00				                .byte $00           ; CURATTR, 2 bytes, Attribute of next character to be printed to the screen.
+>380014		00 80				                .word STACK_BEGIN   ; STACKBOT, 2 bytes, Lowest location the stack should be allowed to write to. If SP falls below this value, the runtime should generate STACK OVERFLOW error and abort.
+>380016		ff fe				                .word STACK_END     ; STACKTOP, 2 bytes, Highest location the stack can occupy. If SP goes above this value, the runtime should generate STACK OVERFLOW error and abort.
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/page_00_code.asm
+
+.38ff00		18		clc		RHRESET         CLC
+.38ff01		fb		xce		                XCE
+.38ff02		5c 00 10 00	jmp $001000	                JML BOOT
+.38ff10						RHCOP
+.38ff10		c2 30		rep #$30	                REP #$30        ; set A&X long
+.38ff12		8b		phb		                PHB
+.38ff13		0b		phd		                PHD
+.38ff14		48		pha		                PHA
+.38ff15		da		phx		                PHX
+.38ff16		5a		phy		                PHY
+.38ff17		5c 08 10 00	jmp $001008	                JML BREAK
+.38ff20						RHBRK
+.38ff20		c2 30		rep #$30	                REP #$30        ; set A&X long
+.38ff22		8b		phb		                PHB
+.38ff23		0b		phd		                PHD
+.38ff24		48		pha		                PHA
+.38ff25		da		phx		                PHX
+.38ff26		5a		phy		                PHY
+.38ff27		5c 08 10 00	jmp $001008	                JML BREAK
+.38ff30						RHABORT
+.38ff30		c2 30		rep #$30	                REP #$30        ; set A&X long
+.38ff32		8b		phb		                PHB
+.38ff33		0b		phd		                PHD
+.38ff34		48		pha		                PHA
+.38ff35		da		phx		                PHX
+.38ff36		5a		phy		                PHY
+.38ff37		5c 08 10 00	jmp $001008	                JML BREAK
+.38ff40						 RHNMI
+.38ff40		c2 30		rep #$30	                REP #$30        ; set A&X long
+.38ff42		8b		phb		                PHB
+.38ff43		0b		phd		                PHD
+.38ff44		48		pha		                PHA
+.38ff45		da		phx		                PHX
+.38ff46		5a		phy		                PHY
+.38ff47		22 d5 18 38	jsl $3818d5	                JSL NMI_HANDLER
+.38ff4b		7a		ply		                PLY
+.38ff4c		fa		plx		                PLX
+.38ff4d		68		pla		                PLA
+.38ff4e		2b		pld		                PLD
+.38ff4f		ab		plb		                PLB
+.38ff50		40		rti		                RTI
+.38ff60						RHIRQ
+.38ff60		c2 30		rep #$30	                REP #$30        ; set A&X long
+.38ff62		8b		phb		                PHB
+.38ff63		0b		phd		                PHD
+.38ff64		48		pha		                PHA
+.38ff65		da		phx		                PHX
+.38ff66		5a		phy		                PHY
+.38ff67		22 14 17 38	jsl $381714	                JSL IRQ_HANDLER
+.38ff6b		7a		ply		                PLY
+.38ff6c		fa		plx		                PLX
+.38ff6d		68		pla		                PLA
+.38ff6e		2b		pld		                PLD
+.38ff6f		ab		plb		                PLB
+.38ff70		40		rti		                RTI
+.38ffe0		5c 04 00 3a	jmp $3a0004	JUMP_READY      JML MONITOR    ; Kernel READY routine. Rewrite this address to jump to a custom kernel.
+>38ffe4		10 ff				RVECTOR_COP     .addr HCOP     ; FFE4
+>38ffe6		20 ff				RVECTOR_BRK     .addr HBRK     ; FFE6
+>38ffe8		30 ff				RVECTOR_ABORT   .addr HABORT   ; FFE8
+>38ffea		40 ff				RVECTOR_NMI     .addr HNMI     ; FFEA
+>38ffec		00 00				                .word $0000    ; FFEC
+>38ffee		60 ff				RVECTOR_IRQ     .addr HIRQ    ; FFEE
+.38fff0		5c dd 06 39	jmp $3906dd	RRETURN         JML IRETURN
+>38fff4		10 ff				RVECTOR_ECOP    .addr HCOP     ; FFF4
+>38fff6		20 ff				RVECTOR_EBRK    .addr HBRK     ; FFF6
+>38fff8		30 ff				RVECTOR_EABORT  .addr HABORT   ; FFF8
+>38fffa		40 ff				RVECTOR_ENMI    .addr HNMI     ; FFFA
+>38fffc		00 ff				RVECTOR_ERESET  .addr HRESET   ; FFFC
+>38fffe		60 ff				RVECTOR_EIRQ    .addr HIRQ     ; FFFE
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/dram_inc.asm
+
+=$afa000					SCREEN_PAGE0     = $AFA000 ;8192 Bytes First page of display RAM. This is used at boot time to display the welcome screen and the BASIC or MONITOR command screens.
+=$afc000					SCREEN_PAGE1     = $AFC000 ;8192 Bytes Additional page of display RAM. This can be used for page flipping or to handle multiple edit buffers.
+=$b00000					SCREEN_END       = $B00000 ;End of display memory
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/fdc_inc.asm
+
+=$af13f0					SIO_FDC  = $AF13F0
+=$af13f0					SIO_FDC_SRA = $AF13F0 ; Read Only - Status Register A (not used in AT mode)
+=$af13f1					SIO_FDC_SRB = $AF13F1 ; Read Only - Status Register B (not used in AT mode)
+=$af13f2					SIO_FDC_DOR = $AF13F2 ; Read/Write - Digital Output Register
+=$01						FDC_DOR_DSEL0 = $01     ; Drive 0 Select
+=$02						FDC_DOR_DSEL1 = $02     ; Drive 1 Select
+=$04						FDC_DOR_NRESET = $04    ; Reset the FDC
+=$08						FDC_DOR_DMAEN = $08     ; Enable DMA
+=$10						FDC_DOR_MOT0  = $10     ; Turn on motor 0
+=$20						FDC_DOR_MOT1  = $20     ; Turn on motor 1
+=$40						FDC_DOR_MOT2  = $40     ; Turn on motor 2
+=$80						FDC_DOR_MOT3  = $80     ; Turn on motor 3
+=$af13f3					SIO_FDC_TSR = $AF13F3   ; Read/Write - Tape Drive Status (not used on the C256)
+=$af13f4					SIO_FDC_MSR = $AF13F4   ; Read - Main Status Register
+=$01						FDC_MSR_DRV0BSY = $01   ; Indicates if drive 0 is busy
+=$02						FDC_MSR_DRV1BSY = $02   ; Indicates if drive 1 is busy
+=$10						FDC_MSR_CMDBSY = $10    ; Indicates if a command is in progress
+=$20						FDC_MSR_NONDMA = $20    ;
+=$40						FDC_MSR_DIO = $40       ; Data direction: 1 = read, 0 = write
+=$80						FDC_MSR_RQM = $80       ; 1 = host can transfer data, 0 = host must wait
+=$af13f4					SIO_FDC_DSR = $AF13F4   ; Write - Data Select Register
+=$40						FDC_DSR_LOPWR = $40     ; Turn on low power mode
+=$80						FDC_DSR_RESET = $80     ; Software reset of the FDC
+=$af13f5					SIO_FDC_DTA = $AF13F5   ; Read/Write - Data - FIFO
+=$af13f6					SIO_FDC_RSV = $AF13F6   ; Reserved
+=$af13f7					SIO_FDC_DIR = $AF13F7   ; Read - Digital Input Register
+=$80						FDC_DIR_DSKCHG = $80    ; Indicates if the disk has changed
+=$af13f7					SIO_FDC_CCR = $AF13F7   ; Write - Configuration Control Register
+=$03						FDC_ST0_DRVSEL = $03    ; Mask for the current selected drive
+=$04						FDC_ST0_HEAD = $04      ; Bit for the current selected head
+=$08						FDC_ST0_EC = $08        ; Bit for EQUIPMENT CHECK, error in recalibrate or relative seek
+=$10						FDC_ST0_SEEKEND = $10   ; The FDC completed a seek, relative seek, or recalibrate
+=$c0						FDC_ST0_INTCODE = $C0   ; Mask for interrupt code:
+=$01						FDC_ST1_MA = $01        ; Missing address mark
+=$02						FDC_ST1_NW = $02        ; Not writable (disk is write protected)
+=$04						FDC_ST1_ND = $04        ; No data
+=$10						FDC_ST1_OR = $10        ; Overrun/underrun of the data
+=$20						FDC_ST1_DE = $20        ; Data error... a CRC check failed
+=$80						FDC_ST1_EN = $80        ; End of cylinder: tried to acess a sector not on the track
+=$01						FDC_ST2_MD = $01        ; Missing address mark: FDC cannot detect a data address mark
+=$02						FDC_ST2_BC = $02        ; Bad cylinder
+=$10						FDC_ST2_WC = $10        ; Wrong cylinder: track is not the same as expected
+=$20						FDC_ST2_DD = $20        ; Data error in field: CRC error
+=$40						FDC_ST2_CM = $40        ; Control mark
+=$03						FDC_ST3_DRVSEL = $03    ; Drive select mask
+=$04						FDC_ST3_HEAD = $04      ; Head address bit
+=$10						FDC_ST3_TRACK0 = $10    ; Track 0: Status of the TRK0 pin
+=$40						FDC_ST3_WP = $40        ; Write Protect: status of the WP pin
+=2						FDC_CMD_READ_TRACK          = 2
+=3						FDC_CMD_SPECIFY             = 3
+=4						FDC_CMD_SENSE_DRIVE_STATUS  = 4
+=5						FDC_CMD_WRITE_DATA          = 5
+=6						FDC_CMD_READ_DATA           = 6
+=7						FDC_CMD_RECALIBRATE         = 7
+=8						FDC_CMD_SENSE_INTERRUPT     = 8
+=9						FDC_CMD_WRITE_DELETED_DATA  = 9
+=10						FDC_CMD_READ_ID             = 10
+=12						FDC_CMD_READ_DELETED_DATA   = 12
+=13						FDC_CMD_FORMAT_TRACK        = 13
+=14						FDC_CMD_DUMPREG             = 14
+=15						FDC_CMD_SEEK                = 15
+=16						FDC_CMD_VERSION             = 16
+=17						FDC_CMD_SCAN_EQUAL          = 17
+=18						FDC_CMD_PERPENDICULAR_MODE  = 18
+=19						FDC_CMD_CONFIGURE           = 19
+=20						FDC_CMD_LOCK                = 20
+=22						FDC_CMD_VERIFY              = 22
+=25						FDC_CMD_SCAN_LOW_OR_EQUAL   = 25
+=29						FDC_CMD_SCAN_HIGH_OR_EQUAL  = 29
+=$80						FDC_CMD_MT = $80                    ; Command bit to turn on multi-track
+=$40						FDC_CMD_MFM = $40                   ; Command bit to operate in MFM format
+=$20						FDC_CMD_SK = $20                    ; Command bit to skip deleted sectors
+=$40						FDC_CMD_EIS = $40                   ; Command bit to turn on implied seek
+=1						FDC_DEVCMD_MOTOR_ON         = 1     ; Device code to turn the motor on
+=2						FDC_DEVCMD_MOTOR_OFF        = 2     ; Device code to turn the motor off
+=3						FDC_DEVCMD_RECAL            = 3     ; Device code to recalibrate the drive
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Includes/basic_inc.asm
+
+=$3a0000					    BASIC = $3A0000
+=3801092					    MONITOR = BASIC + 4
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\kernel_jumptable.asm
+
+.381000	1000	5c 00 04 39	jmp $390400	BOOT            JML IBOOT
+.381004	1004	5c e8 05 39	jmp $3905e8	RESTORE         JML IRESTORE
+.381008	1008	5c 7c 06 39	jmp $39067c	BREAK           JML IBREAK
+.38100c	100c	5c c3 06 39	jmp $3906c3	READY           JML IREADY
+.381010	1010	5c e7 14 39	jmp $3914e7	SCINIT          JML ISCINIT
+.381014	1014	5c e8 14 39	jmp $3914e8	IOINIT          JML IIOINIT
+.381018	1018	5c 7f 07 39	jmp $39077f	PUTC            JML IPUTC
+.38101c	101c	5c 68 07 39	jmp $390768	PUTS            JML IPUTS
+.381020	1020	5c f7 08 39	jmp $3908f7	PUTB            JML IPUTB
+.381024	1024	5c cc 3f 39	jmp $393fcc	PUTBLOCK        JML IPUTBLOCK
+.381028	1028	5c e9 14 39	jmp $3914e9	SETLFS          JML ISETLFS
+.38102c	102c	5c ea 14 39	jmp $3914ea	SETNAM          JML ISETNAM
+.381030	1030	5c eb 14 39	jmp $3914eb	OPEN            JML IOPEN
+.381034	1034	5c ec 14 39	jmp $3914ec	CLOSE           JML ICLOSE
+.381038	1038	5c de 06 39	jmp $3906de	SETIN           JML ISETIN
+.38103c	103c	5c e7 06 39	jmp $3906e7	SETOUT          JML ISETOUT
+.381040	1040	5c ed 14 39	jmp $3914ed	GETB            JML IGETB
+.381044	1044	5c 69 3f 39	jmp $393f69	GETBLOCK        JML IGETBLOCK
+.381048	1048	5c 2c 07 39	jmp $39072c	GETCH           JML IGETCH
+.38104c	104c	5c f9 06 39	jmp $3906f9	GETCHW          JML IGETCHW
+.381050	1050	5c f0 06 39	jmp $3906f0	GETCHE          JML IGETCHE
+.381054	1054	5c ee 14 39	jmp $3914ee	GETS            JML IGETS
+.381058	1058	5c ef 14 39	jmp $3914ef	GETLINE         JML IGETLINE
+.38105c	105c	5c f0 14 39	jmp $3914f0	GETFIELD        JML IGETFIELD
+.381060	1060	5c f1 14 39	jmp $3914f1	TRIM            JML ITRIM
+.381064	1064	5c f2 14 39	jmp $3914f2	PRINTC          JML IPRINTC
+.381068	1068	5c f3 14 39	jmp $3914f3	PRINTS          JML IPRINTS
+.38106c	106c	5c f8 08 39	jmp $3908f8	PRINTCR         JML IPRINTCR
+.381070	1070	5c f4 14 39	jmp $3914f4	PRINTF          JML IPRINTF
+.381074	1074	5c f5 14 39	jmp $3914f5	PRINTI          JML IPRINTI
+.381078	1078	5c b8 0a 39	jmp $390ab8	PRINTH          JML IPRINTH
+.38107c	107c	5c f6 14 39	jmp $3914f6	PRINTAI         JML IPRINTAI
+.381080	1080	5c d5 0a 39	jmp $390ad5	PRINTAH         JML IPRINTAH
+.381084	1084	5c fc 09 39	jmp $3909fc	LOCATE          JML ILOCATE
+.381088	1088	5c f7 14 39	jmp $3914f7	PUSHKEY         JML IPUSHKEY
+.38108c	108c	5c f8 14 39	jmp $3914f8	PUSHKEYS        JML IPUSHKEYS
+.381090	1090	5c 58 09 39	jmp $390958	CSRRIGHT        JML ICSRRIGHT
+.381094	1094	5c 8b 09 39	jmp $39098b	CSRLEFT         JML ICSRLEFT
+.381098	1098	5c b1 09 39	jmp $3909b1	CSRUP           JML ICSRUP
+.38109c	109c	5c d7 09 39	jmp $3909d7	CSRDOWN         JML ICSRDOWN
+.3810a0	10a0	5c 47 09 39	jmp $390947	CSRHOME         JML ICSRHOME
+.3810a4	10a4	5c 48 0a 39	jmp $390a48	SCROLLUP        JML ISCROLLUP
+.3810a8	10a8	5c 23 0b 39	jmp $390b23	CLRSCREEN       JML ICLRSCREEN
+.3810ac	10ac	5c ee 0b 39	jmp $390bee	INITCHLUT	    JML IINITCHLUT
+.3810b0	10b0	5c c4 0e 39	jmp $390ec4	INITSUPERIO	    JML IINITSUPERIO
+.3810b4	10b4	5c c3 0f 39	jmp $390fc3	INITKEYBOARD    JML IINITKEYBOARD
+.3810b8	10b8	5c 78 10 39	jmp $391078	INITMOUSE       JML IINITMOUSE
+.3810bc	10bc	5c a5 0e 39	jmp $390ea5	INITCURSOR      JML IINITCURSOR
+.3810c0	10c0	5c 6d 0e 39	jmp $390e6d	INITFONTSET     JML IINITFONTSET
+.3810c4	10c4	5c 1d 0c 39	jmp $390c1d	INITGAMMATABLE  JML IINITGAMMATABLE
+.3810c8	10c8	5c 3d 0c 39	jmp $390c3d	INITALLLUT      JML IINITALLLUT
+.3810cc	10cc	5c 03 0d 39	jmp $390d03	INITVKYTXTMODE  JML IINITVKYTXTMODE
+.3810d0	10d0	5c 34 0e 39	jmp $390e34	INITVKYGRPMODE  JML IINITVKYGRPMODE
+.3810d4	10d4	5c 6c 0e 39	jmp $390e6c	ISETDAC32KHZ    JML INOP            ; Depracated Routine Replaced by New Ones - To be Implemented
+.3810d8	10d8	5c 6c 0e 39	jmp $390e6c	ISETDAC48KHZ    JML INOP            ; Depracated Routine Replaced by New Ones - To be Implemented
+.3810dc	10dc	5c 35 11 39	jmp $391135	INITCODEC       JML IINITCODEC
+.3810e0	10e0	5c c4 11 39	jmp $3911c4	RESETCODEC      JML IRESETCODEC
+.3810e4	10e4	5c 32 12 39	jmp $391232	BMP_PARSER      JML IBMP_PARSER
+.3810e8	10e8	5c e7 11 39	jmp $3911e7	BM_FILL_SCREEN  JML IBM_FILL_SCREEN
+.3810ec	10ec	5c 75 35 39	jmp $393575	OPL2_TONE_TEST  JML IOPL2_TONE_TEST
+.3810f0	10f0	5c 46 52 39	jmp $395246	F_OPEN          JML IF_OPEN         ; open a file for reading/writing/creating
+.3810f4	10f4	5c d9 52 39	jmp $3952d9	F_CREATE        JML IF_CREATE       ; create a new file
+.3810f8	10f8	5c 13 53 39	jmp $395313	F_CLOSE         JML IF_CLOSE        ; close a file (make sure last cluster is written)
+.3810fc	10fc	5c ac 53 39	jmp $3953ac	F_WRITE         JML IF_WRITE        ; write the current cluster to the file
+.381100	1100	5c 47 53 39	jmp $395347	F_READ          JML IF_READ         ; read the next cluster from the file
+.381104	1104	5c 56 54 39	jmp $395456	F_DELETE        JML IF_DELETE       ; delete a file / directory
+.381108	1108	5c 18 54 39	jmp $395418	F_DIROPEN       JML IF_DIROPEN      ; open a directory and seek the first directory entry
+.38110c	110c	5c 52 54 39	jmp $395452	F_DIRNEXT       JML IF_DIRNEXT      ; seek to the next directory of an open directory
+.381110	1110	5c ef 54 39	jmp $3954ef	F_DIRREAD       JML IF_DIRREAD      ; Read the directory entry for the specified file
+.381114	1114	5c 16 55 39	jmp $395516	F_DIRWRITE      JML IF_DIRWRITE     ; Write any changes in the current directory cluster back to the drive
+.381118	1118	5c 1a 55 39	jmp $39551a	F_LOAD          JML IF_LOAD         ; load a binary file into memory, supports multiple file formats
+.38111c	111c	5c 0a 57 39	jmp $39570a	F_SAVE          JML IF_SAVE         ; Save memory to a binary file
+.381120	1120	5c 3f 3f 39	jmp $393f3f	CMDBLOCK        JML ICMDBLOCK       ; Send a command to a block device
+.381124	1124	5c a3 57 39	jmp $3957a3	F_RUN           JML IF_RUN          ; Load an run a binary file
+.381128	1128	5c 6a 43 39	jmp $39436a	F_MOUNT         JML DOS_MOUNT       ; Mount the designated block device
+.38112c	112c	5c 81 0d 39	jmp $390d81	SETSIZES        JML ISETSIZES
+.381130	1130	5c da 58 39	jmp $3958da	F_COPY          JML IF_COPY         ; Copy a file
+.381134	1134	5c 3c 58 39	jmp $39583c	F_ALLOCFD       JML IF_ALLOCFD      ; Allocate a file descriptor
+.381138	1138	5c 90 58 39	jmp $395890	F_FREEFD        JML IF_FREEFD       ; Free a file descriptor
+.381700	1700	5c 32 68 39	jmp $396832	VEC_INT00_SOF   JML FDC_TIME_HANDLE ; IRQ 0, 0 --- Start Of Frame interrupt
+.381704	1704	5c fb 14 39	jmp $3914fb	VEC_INT01_SOL   JML IRQHANDLESTUB   ; IRQ 0, 1 --- Start Of Line interrupt
+.381708	1708	5c fb 14 39	jmp $3914fb	VEC_INT02_TMR0  JML IRQHANDLESTUB   ; IRQ 0, 2 --- Timer 0 interrupt
+.38170c	170c	5c fb 14 39	jmp $3914fb	VEC_INT03_TMR1  JML IRQHANDLESTUB   ; IRQ 0, 3 --- Timer 1 interrupt
+.381710	1710	5c fb 14 39	jmp $3914fb	VEC_INT04_TMR2  JML IRQHANDLESTUB   ; IRQ 0, 4 --- Timer 2 interrupt
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Interrupt_Handler.asm
+
+.381714						IRQ_HANDLER
+.381714		e2 20		sep #$20	                SEP #$20        ; set A short
+.381716		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.38171a		c9 00		cmp #$00	                CMP #$00
+.38171c		f0 7d		beq $38179b	                BEQ CHECK_PENDING_REG1
+.38171e		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.381722		29 01		and #$01	                AND #FNX0_INT00_SOF
+.381724		c9 01		cmp #$01	                CMP #FNX0_INT00_SOF
+.381726		d0 09		bne $381731	                BNE SERVICE_NEXT_IRQ1
+.381728		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.38172c		20 09 18	jsr $381809	                JSR SOF_INTERRUPT
+.38172f		e2 20		sep #$20	                SEP #$20        ; set A short
+.381731						SERVICE_NEXT_IRQ1
+.381731		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.381735		29 02		and #$02	                AND #FNX0_INT01_SOL
+.381737		c9 02		cmp #$02	                CMP #FNX0_INT01_SOL
+.381739		d0 07		bne $381742	                BNE SERVICE_NEXT_IRQ2
+.38173b		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.38173f		20 1a 18	jsr $38181a	                JSR SOL_INTERRUPT
+.381742						SERVICE_NEXT_IRQ2
+.381742		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.381746		29 04		and #$04	                AND #FNX0_INT02_TMR0
+.381748		c9 04		cmp #$04	                CMP #FNX0_INT02_TMR0
+.38174a		d0 07		bne $381753	                BNE SERVICE_NEXT_IRQ3
+.38174c		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381750		20 2b 18	jsr $38182b	                JSR TIMER0_INTERRUPT
+.381753						SERVICE_NEXT_IRQ3
+.381753		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.381757		29 08		and #$08	                AND #FNX0_INT03_TMR1
+.381759		c9 08		cmp #$08	                CMP #FNX0_INT03_TMR1
+.38175b		d0 07		bne $381764	                BNE SERVICE_NEXT_IRQ4
+.38175d		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381761		20 3c 18	jsr $38183c	                JSR TIMER1_INTERRUPT
+.381764						SERVICE_NEXT_IRQ4
+.381764		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.381768		29 10		and #$10	                AND #FNX0_INT04_TMR2
+.38176a		c9 10		cmp #$10	                CMP #FNX0_INT04_TMR2
+.38176c		d0 09		bne $381777	                BNE SERVICE_NEXT_IRQ6
+.38176e		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381772		20 4d 18	jsr $38184d	                JSR TIMER2_INTERRUPT
+.381775		e2 20		sep #$20	                SEP #$20        ; set A short
+.381777						SERVICE_NEXT_IRQ6
+.381777		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.38177b		29 40		and #$40	                AND #FNX0_INT06_FDC
+.38177d		c9 40		cmp #$40	                CMP #FNX0_INT06_FDC
+.38177f		d0 09		bne $38178a	                BNE SERVICE_NEXT_IRQ7
+.381781		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381785		20 9e 18	jsr $38189e	                JSR FDC_INTERRUPT
+.381788		e2 20		sep #$20	                SEP #$20        ; set A short
+.38178a						SERVICE_NEXT_IRQ7
+.38178a		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.38178e		29 80		and #$80	                AND #FNX0_INT07_MOUSE
+.381790		c9 80		cmp #$80	                CMP #FNX0_INT07_MOUSE
+.381792		d0 07		bne $38179b	                BNE CHECK_PENDING_REG1
+.381794		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381798		20 5e 18	jsr $38185e	                JSR MOUSE_INTERRUPT
+.38179b						CHECK_PENDING_REG1
+.38179b		e2 20		sep #$20	                SEP #$20        ; set A short
+.38179d		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3817a1		c9 00		cmp #$00	                CMP #$00
+.3817a3		f0 61		beq $381806	                BEQ EXIT_IRQ_HANDLE
+.3817a5						SERVICE_NEXT_IRQ8
+.3817a5		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3817a9		29 01		and #$01	                AND #FNX1_INT00_KBD
+.3817ab		c9 01		cmp #$01	                CMP #FNX1_INT00_KBD
+.3817ad		d0 0d		bne $3817bc	                BNE SERVICE_NEXT_IRQ11
+.3817af		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3817b3		8b		phb		                PHB
+.3817b4		0b		phd		                PHD
+.3817b5		20 d6 18	jsr $3818d6	                JSR KEYBOARD_INTERRUPT
+.3817b8		2b		pld		                PLD
+.3817b9		ab		plb		                PLB
+.3817ba		e2 20		sep #$20	                SEP #$20        ; set A short
+.3817bc						SERVICE_NEXT_IRQ11
+.3817bc		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3817c0		29 08		and #$08	                AND #FNX1_INT03_COM2
+.3817c2		c9 08		cmp #$08	                CMP #FNX1_INT03_COM2
+.3817c4		d0 09		bne $3817cf	                BNE SERVICE_NEXT_IRQ12
+.3817c6		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3817ca		20 a9 18	jsr $3818a9	                JSR COM2_INTERRUPT
+.3817cd		e2 20		sep #$20	                SEP #$20        ; set A short
+.3817cf						SERVICE_NEXT_IRQ12
+.3817cf		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3817d3		29 10		and #$10	                AND #FNX1_INT04_COM1
+.3817d5		c9 10		cmp #$10	                CMP #FNX1_INT04_COM1
+.3817d7		d0 09		bne $3817e2	                BNE SERVICE_NEXT_IRQ13
+.3817d9		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3817dd		20 b4 18	jsr $3818b4	                JSR COM1_INTERRUPT
+.3817e0		e2 20		sep #$20	                SEP #$20        ; set A short
+.3817e2						SERVICE_NEXT_IRQ13
+.3817e2		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3817e6		29 20		and #$20	                AND #FNX1_INT05_MPU401
+.3817e8		c9 20		cmp #$20	                CMP #FNX1_INT05_MPU401
+.3817ea		d0 09		bne $3817f5	                BNE SERVICE_NEXT_IRQ14
+.3817ec		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3817f0		20 bf 18	jsr $3818bf	                JSR MPU401_INTERRUPT
+.3817f3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3817f5						SERVICE_NEXT_IRQ14
+.3817f5		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3817f9		29 40		and #$40	                AND #FNX1_INT06_LPT
+.3817fb		c9 40		cmp #$40	                CMP #FNX1_INT06_LPT
+.3817fd		d0 07		bne $381806	                BNE EXIT_IRQ_HANDLE
+.3817ff		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.381803		20 ca 18	jsr $3818ca	                JSR LPT1_INTERRUPT
+.381806						EXIT_IRQ_HANDLE
+.381806		c2 30		rep #$30	                REP #$30        ; set A&X long
+.381808		6b		rtl		                RTL
+.381809						SOF_INTERRUPT
+.381809		e2 20		sep #$20	                SEP #$20        ; set A short
+.38180b		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.38180f		29 01		and #$01	                AND #FNX0_INT00_SOF
+.381811		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381815		22 00 17 00	jsl $001700	                JSL VEC_INT00_SOF
+.381819		60		rts		                RTS
+.38181a						SOL_INTERRUPT
+.38181a		e2 20		sep #$20	                SEP #$20        ; set A short
+.38181c		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.381820		29 02		and #$02	                AND #FNX0_INT01_SOL
+.381822		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.381826		22 04 17 00	jsl $001704	                JSL VEC_INT01_SOL
+.38182a		60		rts		                RTS
+.38182b						TIMER0_INTERRUPT
+.38182b		e2 20		sep #$20	                SEP #$20        ; set A short
+.38182d		af 05 07 00	lda $000705	                LDA @l TIMERFLAGS               ; Flag that the interrupt has happened
+.381831		09 80		ora #$80	                ORA #TIMER0TRIGGER
+.381833		8f 05 07 00	sta $000705	                STA @l TIMERFLAGS
+.381837		22 08 17 00	jsl $001708	                JSL VEC_INT02_TMR0
+.38183b		60		rts		                RTS
+.38183c						TIMER1_INTERRUPT
+.38183c		e2 20		sep #$20	                SEP #$20        ; set A short
+.38183e		af 05 07 00	lda $000705	                LDA @l TIMERFLAGS               ; Flag that the interrupt has happened
+.381842		09 40		ora #$40	                ORA #TIMER1TRIGGER
+.381844		8f 05 07 00	sta $000705	                STA @l TIMERFLAGS
+.381848		22 0c 17 00	jsl $00170c	                JSL VEC_INT03_TMR1
+.38184c		60		rts		                RTS
+.38184d						TIMER2_INTERRUPT
+.38184d		e2 20		sep #$20	                SEP #$20        ; set A short
+.38184f		af 05 07 00	lda $000705	                LDA @l TIMERFLAGS               ; Flag that the interrupt has happened
+.381853		09 20		ora #$20	                ORA #TIMER2TRIGGER
+.381855		8f 05 07 00	sta $000705	                STA @l TIMERFLAGS
+.381859		22 10 17 00	jsl $001710	                JSL VEC_INT04_TMR2
+.38185d		60		rts		                RTS
+.38185e						MOUSE_INTERRUPT
+.38185e		e2 30		sep #$30	                SEP #$30        ; set A&X short
+.381860		af e0 00 00	lda $0000e0	                LDA @l MOUSE_PTR
+.381864		aa		tax		                TAX
+.381865		af 03 18 af	lda $af1803	                LDA @l KBD_INPT_BUF
+.381869		9f 06 07 af	sta $af0706,x	                STA @lMOUSE_PTR_BYTE0, X
+.38186d		e8		inx		                INX
+.38186e		e0 03		cpx #$03	                CPX #$03
+.381870		d0 24		bne $381896	                BNE EXIT_FOR_NEXT_VALUE
+.381872		af 02 07 af	lda $af0702	                LDA @l MOUSE_PTR_X_POS_L
+.381876		8f e1 00 00	sta $0000e1	                STA @l MOUSE_POS_X_LO
+.38187a		af 03 07 af	lda $af0703	                LDA @l MOUSE_PTR_X_POS_H
+.38187e		8f e2 00 00	sta $0000e2	                STA @l MOUSE_POS_X_HI
+.381882		af 04 07 af	lda $af0704	                LDA @l MOUSE_PTR_Y_POS_L
+.381886		8f e3 00 00	sta $0000e3	                STA @l MOUSE_POS_Y_LO
+.38188a		af 05 07 af	lda $af0705	                LDA @l MOUSE_PTR_Y_POS_H
+.38188e		8f e4 00 00	sta $0000e4	                STA @l MOUSE_POS_Y_HI
+.381892		e2 20		sep #$20	                SEP #$20        ; set A short
+.381894		a2 00		ldx #$00	                LDX #$00
+.381896						EXIT_FOR_NEXT_VALUE
+.381896		8a		txa		                TXA
+.381897		8f e0 00 00	sta $0000e0	                STA @l MOUSE_PTR
+.38189b		c2 10		rep #$10	                REP #$10        ; set X long
+.38189d		60		rts		                RTS
+.38189e						FDC_INTERRUPT
+.38189e		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.3818a2		29 40		and #$40	                AND #FNX0_INT06_FDC
+.3818a4		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.3818a8		60		rts		                RTS
+.3818a9						COM2_INTERRUPT
+.3818a9		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3818ad		29 08		and #$08	                AND #FNX1_INT03_COM2
+.3818af		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3818b3		60		rts		                RTS
+.3818b4						COM1_INTERRUPT
+.3818b4		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3818b8		29 10		and #$10	                AND #FNX1_INT04_COM1
+.3818ba		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3818be		60		rts		                RTS
+.3818bf						MPU401_INTERRUPT
+.3818bf		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3818c3		29 20		and #$20	                AND #FNX1_INT05_MPU401
+.3818c5		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3818c9		60		rts		                RTS
+.3818ca						LPT1_INTERRUPT
+.3818ca		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3818ce		29 40		and #$40	                AND #FNX1_INT06_LPT
+.3818d0		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3818d4		60		rts		                RTS
+.3818d5						NMI_HANDLER
+.3818d5		6b		rtl		                RTL
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\keyboard.asm
+
+.3818d6						KEYBOARD_INTERRUPT
+.3818d6		48		pha		                PHA             ; begin setdp macro
+.3818d7		08		php		                PHP
+.3818d8		c2 20		rep #$20	                REP #$20        ; set A long
+.3818da		a9 00 0f	lda #$0f00	                LDA #KEY_BUFFER         ; set DP to page 0
+.3818dd		5b		tcd		                TCD
+.3818de		28		plp		                PLP
+.3818df		68		pla		                PLA             ; end setdp macro
+.3818e0		a2 00 00	ldx #$0000	                ldx #$0000
+.3818e3		e2 10		sep #$10	                SEP #$10        ; set X short
+.3818e5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3818e7		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1
+.3818eb		29 01		and #$01	                AND #FNX1_INT00_KBD
+.3818ed		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1
+.3818f1						IRQ_HANDLER_FETCH
+.3818f1		af 03 18 af	lda $af1803	                LDA @lKBD_INPT_BUF      ; Get Scan Code from KeyBoard
+.3818f5		85 88		sta $0f88	                STA KEYBOARD_SC_TMP     ; Save Code Immediately
+.3818f7		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the Prefix was picked up before
+.3818f9		29 80		and #$80	                AND #$80
+.3818fb		c9 80		cmp #$80	                CMP #$80
+.3818fd		d0 10		bne $38190f	                BNE CHK_LSHIFT          ; No: do normal scan-code checks
+.3818ff		a5 87		lda $0f87	PREFIX_ON       LDA KEYBOARD_SC_FLG     ; Otherwise: clear prefix
+.381901		29 7f		and #$7f	                AND #$7F
+.381903		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.381905		a5 88		lda $0f88	                LDA KEYBOARD_SC_TMP     ; Get the prefixed scan-code's character
+.381907		aa		tax		                TAX
+.381908		bf 80 79 39	lda $397980,x	                LDA @lScanCode_Prefix_Set1, x
+.38190c		4c b2 19	jmp $3819b2	                JMP KB_WR_2_SCREEN      ; And save it
+.38190f		a5 88		lda $0f88	CHK_LSHIFT      LDA KEYBOARD_SC_TMP
+.381911		c9 2a		cmp #$2a	                CMP #$2A                ; Left Shift Pressed
+.381913		d0 03		bne $381918	                BNE NOT_KB_SET_LSHIFT
+.381915		82 ad 00	brl $3819c5	                BRL KB_SET_SHIFT
+.381918						NOT_KB_SET_LSHIFT
+.381918		c9 aa		cmp #$aa	                CMP #$AA                ; Left Shift Unpressed
+.38191a		d0 03		bne $38191f	                BNE NOT_KB_CLR_LSHIFT
+.38191c		82 af 00	brl $3819ce	                BRL KB_CLR_SHIFT
+.38191f						NOT_KB_CLR_LSHIFT
+.38191f		c9 36		cmp #$36	                CMP #$36                ; Right Shift Pressed
+.381921		d0 03		bne $381926	                BNE NOT_KB_SET_RSHIFT
+.381923		82 9f 00	brl $3819c5	                BRL KB_SET_SHIFT
+.381926						NOT_KB_SET_RSHIFT
+.381926		c9 b6		cmp #$b6	                CMP #$B6                ; Right Shift Unpressed
+.381928		d0 03		bne $38192d	                BNE NOT_KB_CLR_RSHIFT
+.38192a		82 a1 00	brl $3819ce	                BRL KB_CLR_SHIFT
+.38192d						NOT_KB_CLR_RSHIFT
+.38192d		c9 1d		cmp #$1d	                CMP #$1D                ; Left CTRL pressed
+.38192f		d0 03		bne $381934	                BNE NOT_KB_SET_CTRL
+.381931		82 a3 00	brl $3819d7	                BRL KB_SET_CTRL
+.381934						NOT_KB_SET_CTRL
+.381934		c9 9d		cmp #$9d	                CMP #$9D                ; Left CTRL Unpressed
+.381936		d0 03		bne $38193b	                BNE NOT_KB_CLR_CTRL
+.381938		82 a5 00	brl $3819e0	                BRL KB_CLR_CTRL
+.38193b						NOT_KB_CLR_CTRL
+.38193b		c9 38		cmp #$38	                CMP #$38                ; Left ALT Pressed
+.38193d		d0 03		bne $381942	                BNE NOT_KB_SET_ALT
+.38193f		82 a7 00	brl $3819e9	                BRL KB_SET_ALT
+.381942						NOT_KB_SET_ALT
+.381942		c9 b8		cmp #$b8	                CMP #$B8                ; Left ALT Unpressed
+.381944		d0 03		bne $381949	                BNE NOT_KB_CLR_ALT
+.381946		82 a9 00	brl $3819f2	                BRL KB_CLR_ALT
+.381949		c9 e0		cmp #$e0	NOT_KB_CLR_ALT  CMP #$E0                ; Prefixed scan code
+.38194b		d0 03		bne $381950	                BNE NOT_PREFIXED
+.38194d		82 ab 00	brl $3819fb	                BRL KB_SET_PREFIX
+.381950		c9 45		cmp #$45	NOT_PREFIXED    CMP #$45                ; Numlock Pressed
+.381952		d0 03		bne $381957	                BNE NOT_KB_SET_NUM
+.381954		82 b6 00	brl $381a0d	                BRL KB_TOG_NUMLOCK
+.381957		c9 46		cmp #$46	NOT_KB_SET_NUM  CMP #$46                ; Scroll Lock Pressed
+.381959		d0 03		bne $38195e	                BNE NOT_KB_SET_SCR
+.38195b		82 a6 00	brl $381a04	                BRL KB_TOG_SCRLOCK
+.38195e		c9 3a		cmp #$3a	NOT_KB_SET_SCR  CMP #$3A                ; Caps Lock Pressed
+.381960		d0 03		bne $381965	                BNE NOT_KB_CAPSLOCK
+.381962		82 bc 00	brl $381a21	                BRL KB_TOG_CAPLOCK
+.381965		c9 58		cmp #$58	NOT_KB_CAPSLOCK CMP #$58                ; F12 Pressed
+.381967		d0 09		bne $381972	                BNE KB_UNPRESSED
+.381969		a9 60		lda #$60	                LDA #KB_CREDITS         ; Yes: flag that the CREDITS key has been pressed
+.38196b		8f 8a 0f 00	sta $000f8a	                STA @lKEYFLAG
+.38196f		82 b5 00	brl $381a27	                BRL KB_CHECK_B_DONE
+.381972		29 80		and #$80	KB_UNPRESSED    AND #$80                ; See if the Scan Code is press or Depressed
+.381974		c9 80		cmp #$80	                CMP #$80                ; Depress Status - We will not do anything at this point
+.381976		d0 03		bne $38197b	                BNE KB_NORM_SC
+.381978		82 ac 00	brl $381a27	                BRL KB_CHECK_B_DONE
+.38197b		a5 88		lda $0f88	KB_NORM_SC      LDA KEYBOARD_SC_TMP       ;
+.38197d		aa		tax		                TAX
+.38197e		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the SHIFT Key is being Pushed
+.381980		29 10		and #$10	                AND #$10
+.381982		c9 10		cmp #$10	                CMP #$10
+.381984		f0 17		beq $38199d	                BEQ SHIFT_KEY_ON
+.381986		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the CTRL Key is being Pushed
+.381988		29 20		and #$20	                AND #$20
+.38198a		c9 20		cmp #$20	                CMP #$20
+.38198c		f0 16		beq $3819a4	                BEQ CTRL_KEY_ON
+.38198e		a5 87		lda $0f87	                LDA KEYBOARD_SC_FLG     ; Check to See if the ALT Key is being Pushed
+.381990		29 40		and #$40	                AND #$40
+.381992		c9 40		cmp #$40	                CMP #$40
+.381994		f0 15		beq $3819ab	                BEQ ALT_KEY_ON
+.381996		bf 00 77 39	lda $397700,x	                LDA @lScanCode_Press_Set1, x
+.38199a		82 15 00	brl $3819b2	                BRL KB_WR_2_SCREEN
+.38199d		bf 80 77 39	lda $397780,x	SHIFT_KEY_ON    LDA @lScanCode_Shift_Set1, x
+.3819a1		82 0e 00	brl $3819b2	                BRL KB_WR_2_SCREEN
+.3819a4		bf 00 78 39	lda $397800,x	CTRL_KEY_ON     LDA @lScanCode_Ctrl_Set1, x
+.3819a8		82 07 00	brl $3819b2	                BRL KB_WR_2_SCREEN
+.3819ab		bf 80 78 39	lda $397880,x	ALT_KEY_ON      LDA @lScanCode_Alt_Set1, x
+.3819af		82 00 00	brl $3819b2	                BRL KB_WR_2_SCREEN
+.3819b2		c9 18		cmp #$18	KB_WR_2_SCREEN  CMP #$18                ; Is it SysRq?
+.3819b4		d0 03		bne $3819b9	                BNE savechar
+.3819b6		4c 37 1a	jmp $381a37	                JMP programmerKey       ; Yes: trigger the programmer key
+.3819b9		48		pha		savechar        PHA
+.3819ba		c2 10		rep #$10	                REP #$10        ; set X long
+.3819bc		20 43 1a	jsr $381a43	                JSR SAVEKEY
+.3819bf		e2 20		sep #$20	                SEP #$20        ; set A short
+.3819c1		68		pla		                PLA
+.3819c2		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819c5		a5 87		lda $0f87	KB_SET_SHIFT    LDA KEYBOARD_SC_FLG
+.3819c7		09 10		ora #$10	                ORA #$10
+.3819c9		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.3819cb		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819ce		a5 87		lda $0f87	KB_CLR_SHIFT    LDA KEYBOARD_SC_FLG
+.3819d0		29 ef		and #$ef	                AND #$EF
+.3819d2		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.3819d4		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819d7		a5 87		lda $0f87	KB_SET_CTRL     LDA KEYBOARD_SC_FLG
+.3819d9		09 20		ora #$20	                ORA #$20
+.3819db		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.3819dd		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819e0		a5 87		lda $0f87	KB_CLR_CTRL     LDA KEYBOARD_SC_FLG
+.3819e2		29 df		and #$df	                AND #$DF
+.3819e4		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.3819e6		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819e9		a5 87		lda $0f87	KB_SET_ALT      LDA KEYBOARD_SC_FLG
+.3819eb		09 40		ora #$40	                ORA #$40
+.3819ed		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.3819ef		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819f2		a5 87		lda $0f87	KB_CLR_ALT      LDA KEYBOARD_SC_FLG
+.3819f4		29 bf		and #$bf	                AND #$BF
+.3819f6		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.3819f8		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.3819fb		a5 87		lda $0f87	KB_SET_PREFIX   LDA KEYBOARD_SC_FLG
+.3819fd		09 80		ora #$80	                ORA #$80
+.3819ff		85 87		sta $0f87	                STA KEYBOARD_SC_FLG
+.381a01		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.381a04		a5 89		lda $0f89	KB_TOG_SCRLOCK  LDA KEYBOARD_LOCKS
+.381a06		49 01		eor #$01	                EOR #KB_SCROLL_LOCK         ; toggle the Scroll Lock flag
+.381a08		85 89		sta $0f89	                STA KEYBOARD_LOCKS
+.381a0a		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.381a0d		a5 87		lda $0f87	KB_TOG_NUMLOCK  LDA KEYBOARD_SC_FLG         ; Check flags...
+.381a0f		29 60		and #$60	                AND #$60                    ; ... is control-alt pressed?
+.381a11		c9 60		cmp #$60	                CMP #$60
+.381a13		d0 03		bne $381a18	                BNE KB_TOG_NUMLOC2
+.381a15		82 63 ff	brl $38197b	                BRL KB_NORM_SC              ; No: treat as a BREAK key
+.381a18		a5 89		lda $0f89	KB_TOG_NUMLOC2  LDA KEYBOARD_LOCKS
+.381a1a		49 02		eor #$02	                EOR #KB_NUM_LOCK            ; toggle the Num Lock flag
+.381a1c		85 89		sta $0f89	                STA KEYBOARD_LOCKS
+.381a1e		4c 27 1a	jmp $381a27	                JMP KB_CHECK_B_DONE
+.381a21		a5 89		lda $0f89	KB_TOG_CAPLOCK  LDA KEYBOARD_LOCKS
+.381a23		49 04		eor #$04	                EOR #KB_CAPS_LOCK           ; toggle the Caps Lock flag
+.381a25		85 89		sta $0f89	                STA KEYBOARD_LOCKS
+.381a27						KB_CHECK_B_DONE
+.381a27		af 07 18 af	lda $af1807	                LDA STATUS_PORT
+.381a2b		29 01		and #$01	                AND #OUT_BUF_FULL           ; Test bit $01 (if 1, Full)
+.381a2d		c9 01		cmp #$01	                CMP #OUT_BUF_FULL           ; if Still Byte in the Buffer, fetch it out
+.381a2f		d0 03		bne $381a34	                BNE SET_LED
+.381a31		4c f1 18	jmp $3818f1	                JMP IRQ_HANDLER_FETCH
+.381a34						SET_LED
+.381a34						KB_DONE
+.381a34		c2 30		rep #$30	                REP #$30        ; set A&X long
+.381a36		60		rts		                RTS
+.381a37						programmerKey
+.381a37		c2 30		rep #$30	                REP #$30        ; set A&X long
+.381a39		68		pla		                PLA                     ; Get and throw-away the return address to the interrupt handler
+.381a3a		2b		pld		                PLD                     ; Restore the registers that were present when the handler was invoked
+.381a3b		ab		plb		                PLB
+.381a3c		7a		ply		                PLY
+.381a3d		fa		plx		                PLX
+.381a3e		68		pla		                PLA
+.381a3f		5c 08 10 00	jmp $001008	                JML BREAK               ; And go to the BRK handler directly to open the monitor
+.381a43						SAVEKEY
+.381a43		e2 20		sep #$20	                SEP #$20        ; set A short
+.381a45		48		pha		                PHA                     ; Save the character
+.381a46		a5 89		lda $0f89	                LDA KEYBOARD_LOCKS      ; Check the keyboard lock flags
+.381a48		29 04		and #$04	                AND #KB_CAPS_LOCK       ; Is CAPS lock on?
+.381a4a		f0 0d		beq $381a59	                BEQ no_caps             ; No... just use the character as-is
+.381a4c		68		pla		                PLA                     ; Get the character back
+.381a4d		c9 61		cmp #$61	                CMP #'a'                ; Is it < 'a'
+.381a4f		90 09		bcc $381a5a	                BLT check_break         ; Yes: just use as-is
+.381a51		c9 7b		cmp #$7b	                CMP #'z'+1              ; Is it > 'z'
+.381a53		b0 05		bcs $381a5a	                BGE check_break         ; Yes: just us as-is
+.381a55		29 df		and #$df	                AND #%11011111          ; Conver to upper case
+.381a57		80 01		bra $381a5a	                BRA check_break
+.381a59		68		pla		no_caps         PLA                     ; Restore the character
+.381a5a		c9 00		cmp #$00	check_break     CMP #0
+.381a5c		f0 18		beq $381a76	                BEQ done
+.381a5e		c9 03		cmp #$03	                CMP #CHAR_CTRL_C        ; Is it CTRL-C?
+.381a60		f0 15		beq $381a77	                BEQ flag_break          ; Yes: flag a break
+.381a62		a6 8d		ldx $0f8d	no_break        LDX KEY_BUFFER_WPOS     ; So the Receive Character is saved in the Buffer
+.381a64		e0 80 00	cpx #$0080	                CPX #KEY_BUFFER_SIZE    ; Make sure we haven't been overboard.
+.381a67		b0 0d		bcs $381a76	                BCS done                ; Stop storing - An error should ensue here...
+.381a69		9f 00 0f 00	sta $000f00,x	                STA @lKEY_BUFFER,X
+.381a6d		e8		inx		                INX
+.381a6e		86 8d		stx $0f8d	                STX KEY_BUFFER_WPOS
+.381a70		a9 00		lda #$00	                LDA #$00
+.381a72		9f 00 0f 00	sta $000f00,x	                STA @lKEY_BUFFER, X       ; Store a EOL in the following location for good measure
+.381a76		60		rts		done            RTS
+.381a77						flag_break
+.381a77		e2 20		sep #$20	                SEP #$20        ; set A short
+.381a79		a9 80		lda #$80	                LDA #KB_CTRL_C          ; Flag that an interrupt key has been pressed
+.381a7b		85 8a		sta $0f8a	                STA KEYFLAG             ; The interpreter should see this soon and throw a BREAK
+.381a7d		60		rts		                RTS
+.381a7e						KBD_GETCW
+.381a7e		da		phx		                PHX
+.381a7f		0b		phd		                PHD
+.381a80		08		php		                PHP
+.381a81		48		pha		                PHA             ; begin setdp macro
+.381a82		08		php		                PHP
+.381a83		c2 20		rep #$20	                REP #$20        ; set A long
+.381a85		a9 00 0f	lda #$0f00	                LDA #KEY_BUFFER         ; set DP to page 0
+.381a88		5b		tcd		                TCD
+.381a89		28		plp		                PLP
+.381a8a		68		pla		                PLA             ; end setdp macro
+.381a8b		e2 20		sep #$20	                SEP #$20        ; set A short
+.381a8d		c2 10		rep #$10	                REP #$10        ; set X long
+.381a8f		58		cli		                CLI                     ; Make sure interrupts can happen
+.381a90		af 8a 0f 00	lda $000f8a	get_wait        LDA @lKEYFLAG           ; Check the keyboard control flag
+.381a94		29 60		and #$60	                AND #KB_CREDITS         ; Are the credits flagged?
+.381a96		c9 60		cmp #$60	                CMP #KB_CREDITS
+.381a98		d0 0a		bne $381aa4	                BNE check_buffer        ; No: check the key buffer
+.381a9a		a9 00		lda #$00	                LDA #0                  ; Yes: clear the flags
+.381a9c		8f 8a 0f 00	sta $000f8a	                STA @lKEYFLAG
+.381aa0		22 a1 14 39	jsl $3914a1	                JSL SHOW_CREDITS        ; Then show the credits screen and wait for a key press
+.381aa4		a6 8b		ldx $0f8b	check_buffer    LDX KEY_BUFFER_RPOS     ; Is KEY_BUFFER_RPOS < KEY_BUFFER_WPOS
+.381aa6		e4 8d		cpx $0f8d	                CPX KEY_BUFFER_WPOS
+.381aa8		90 02		bcc $381aac	                BCC read_buff           ; Yes: a key is present, read it
+.381aaa		80 e4		bra $381a90	                BRA get_wait            ; Otherwise, keep waiting
+.381aac		78		sei		read_buff       SEI                     ; Don't interrupt me!
+.381aad		b5 00		lda $0f00,x	                LDA KEY_BUFFER,X        ; Get the key
+.381aaf		e8		inx		                INX                     ; And move to the next key
+.381ab0		e4 8d		cpx $0f8d	                CPX KEY_BUFFER_WPOS     ; Did we just read the last key?
+.381ab2		f0 07		beq $381abb	                BEQ reset_indexes       ; Yes: return to 0 position
+.381ab4		86 8b		stx $0f8b	                STX KEY_BUFFER_RPOS     ; Otherwise: Update the read index
+.381ab6		58		cli		                CLI
+.381ab7		28		plp		done            PLP                     ; Restore status and interrupts
+.381ab8		2b		pld		                PLD
+.381ab9		fa		plx		                PLX
+.381aba		6b		rtl		                RTL
+.381abb		64 8b		stz $0f8b	reset_indexes   STZ KEY_BUFFER_RPOS     ; Reset read index to the beginning
+.381abd		64 8d		stz $0f8d	                STZ KEY_BUFFER_WPOS     ; Reset the write index to the beginning
+.381abf		80 f6		bra $381ab7	                BRA done
+.381ac1						KBD_GETC
+.381ac1		da		phx		                PHX
+.381ac2		0b		phd		                PHD
+.381ac3		08		php		                PHP
+.381ac4		48		pha		                PHA             ; begin setdp macro
+.381ac5		08		php		                PHP
+.381ac6		c2 20		rep #$20	                REP #$20        ; set A long
+.381ac8		a9 00 0f	lda #$0f00	                LDA #KEY_BUFFER         ; set DP to page 0
+.381acb		5b		tcd		                TCD
+.381acc		28		plp		                PLP
+.381acd		68		pla		                PLA             ; end setdp macro
+.381ace		e2 20		sep #$20	                SEP #$20        ; set A short
+.381ad0		c2 10		rep #$10	                REP #$10        ; set X long
+.381ad2		58		cli		                CLI                     ; Make sure interrupts can happen
+.381ad3		a6 8b		ldx $0f8b	check_buffer    LDX KEY_BUFFER_RPOS     ; Is KEY_BUFFER_RPOS < KEY_BUFFER_WPOS
+.381ad5		e4 8d		cpx $0f8d	                CPX KEY_BUFFER_WPOS
+.381ad7		90 05		bcc $381ade	                BCC read_buff           ; Yes: a key is present, read it
+.381ad9		a9 00		lda #$00	                LDA #0                  ; If no key, return zero and set carry bit
+.381adb		38		sec		                SEC
+.381adc		80 0b		bra $381ae9	                BRA done
+.381ade		78		sei		read_buff       SEI                     ; Don't interrupt me!
+.381adf		b5 00		lda $0f00,x	                LDA KEY_BUFFER,X        ; Get the key
+.381ae1		e8		inx		                INX                     ; And move to the next key
+.381ae2		e4 8d		cpx $0f8d	                CPX KEY_BUFFER_WPOS     ; Did we just read the last key?
+.381ae4		f0 07		beq $381aed	                BEQ reset_indexes       ; Yes: return to 0 position
+.381ae6		86 8b		stx $0f8b	                STX KEY_BUFFER_RPOS     ; Otherwise: Update the read index
+.381ae8		58		cli		                CLI
+.381ae9		28		plp		done            PLP                     ; Restore status and interrupts
+.381aea		2b		pld		                PLD
+.381aeb		fa		plx		                PLX
+.381aec		6b		rtl		                RTL
+.381aed		64 8b		stz $0f8b	reset_indexes   STZ KEY_BUFFER_RPOS     ; Reset read index to the beginning
+.381aef		64 8d		stz $0f8d	                STZ KEY_BUFFER_WPOS     ; Reset the write index to the beginning
+.381af1		80 f6		bra $381ae9	                BRA done
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/Math_def.asm
+
+=$000100					UNSIGNED_MULT_A_LO  = $000100
+=$000101					UNSIGNED_MULT_A_HI  = $000101
+=$000102					UNSIGNED_MULT_B_LO  = $000102
+=$000103					UNSIGNED_MULT_B_HI  = $000103
+=$000104					UNSIGNED_MULT_AL_LO = $000104
+=$000105					UNSIGNED_MULT_AL_HI = $000105
+=$000106					UNSIGNED_MULT_AH_LO = $000106
+=$000107					UNSIGNED_MULT_AH_HI = $000107
+=$000108					SIGNED_MULT_A_LO    = $000108
+=$000109					SIGNED_MULT_A_HI    = $000109
+=$00010a					SIGNED_MULT_B_LO    = $00010A
+=$00010b					SIGNED_MULT_B_HI    = $00010B
+=$00010c					SIGNED_MULT_AL_LO   = $00010C
+=$00010d					SIGNED_MULT_AL_HI   = $00010D
+=$00010e					SIGNED_MULT_AH_LO   = $00010E
+=$00010f					SIGNED_MULT_AH_HI   = $00010F
+=$000110					UNSIGNED_DIV_DEM_LO = $000110
+=$000111					UNSIGNED_DIV_DEM_HI = $000111
+=$000112					UNSIGNED_DIV_NUM_LO = $000112
+=$000113					UNSIGNED_DIV_NUM_HI = $000113
+=$000114					UNSIGNED_DIV_QUO_LO = $000114
+=$000115					UNSIGNED_DIV_QUO_HI = $000115
+=$000116					UNSIGNED_DIV_REM_LO = $000116
+=$000117					UNSIGNED_DIV_REM_HI = $000117
+=$000118					SIGNED_DIV_DEM_LO   = $000118
+=$000119					SIGNED_DIV_DEM_HI   = $000119
+=$00011a					SIGNED_DIV_NUM_LO   = $00011A
+=$00011b					SIGNED_DIV_NUM_HI   = $00011B
+=$00011c					SIGNED_DIV_QUO_LO   = $00011C
+=$00011d					SIGNED_DIV_QUO_HI   = $00011D
+=$00011e					SIGNED_DIV_REM_LO   = $00011E
+=$00011f					SIGNED_DIV_REM_HI   = $00011F
+=$000120					ADDER32_A_LL        = $000120
+=$000121					ADDER32_A_LH        = $000121
+=$000122					ADDER32_A_HL        = $000122
+=$000123					ADDER32_A_HH        = $000123
+=$000124					ADDER32_B_LL        = $000124
+=$000125					ADDER32_B_LH        = $000125
+=$000126					ADDER32_B_HL        = $000126
+=$000127					ADDER32_B_HH        = $000127
+=$000128					ADDER32_R_LL        = $000128
+=$000129					ADDER32_R_LH        = $000129
+=$00012a					ADDER32_R_HL        = $00012A
+=$00012b					ADDER32_R_HH        = $00012B
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/timer_def.asm
+
+=$000160					TIMER0_CTRL_REG   = $000160 ; (Write - Control, Read Status)
+=$01						TMR0_EN     = $01
+=$02						TMR0_SCLR   = $02
+=$04						TMR0_SLOAD  = $04 ; Use SLOAD is
+=$08						TMR0_UPDWN  = $08
+=$000161					TIMER0_CHARGE_L   = $000161 ; Use if you want to Precharge and countdown
+=$000162					TIMER0_CHARGE_M   = $000162 ;
+=$000163					TIMER0_CHARGE_H   = $000163 ;
+=$000164					TIMER0_CMP_REG    = $000164 ;
+=$01						TMR0_CMP_RECLR     = $01 ; set to one for it to cycle when Counting up
+=$02						TMR0_CMP_RELOAD    = $02 ; Set to one for it to reload when Counting Down
+=$000165					TIMER0_CMP_L      = $000165 ; Load this Value for Countup
+=$000166					TIMER0_CMP_M      = $000166 ;
+=$000167					TIMER0_CMP_H      = $000167 ;
+=$000168					TIMER1_CTRL_REG   = $000168 ;
+=$01						TMR1_EN     = $01
+=$02						TMR1_SCLR   = $02
+=$04						TMR1_SLOAD  = $04
+=$08						TMR1_UPDWN  = $08 ; 1 = Up, 0 = Down
+=$000169					TIMER1_CHARGE_L   = $000169 ; Use if you want to Precharge and countdown
+=$00016a					TIMER1_CHARGE_M   = $00016A ;
+=$00016b					TIMER1_CHARGE_H   = $00016B ;
+=$00016c					TIMER1_CMP_REG    = $00016C ;
+=$01						TMR1_CMP_RECLR     = $01 ; set to one for it to cycle when Counting up
+=$02						TMR1_CMP_RELOAD    = $02 ; Set to one for it to reload when Counting Down
+=$00016d					TIMER1_CMP_L      = $00016D ;
+=$00016e					TIMER1_CMP_M      = $00016E ;
+=$00016f					TIMER1_CMP_H      = $00016F ;
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/interrupt_def.asm
+
+=$000140					INT_PENDING_REG0 = $000140 ;
+=$000141					INT_PENDING_REG1 = $000141 ;
+=$000142					INT_PENDING_REG2 = $000142 ;
+=$000143					INT_PENDING_REG3 = $000143 ; FMX Model
+=$000144					INT_POL_REG0     = $000144 ;
+=$000145					INT_POL_REG1     = $000145 ;
+=$000146					INT_POL_REG2     = $000146 ;
+=$000147					INT_POL_REG7     = $000147 ; FMX Model
+=$000148					INT_EDGE_REG0    = $000148 ;
+=$000149					INT_EDGE_REG1    = $000149 ;
+=$00014a					INT_EDGE_REG2    = $00014A ;
+=$00014b					INT_EDGE_REG3    = $00014B ; FMX Model
+=$00014c					INT_MASK_REG0    = $00014C ;
+=$00014d					INT_MASK_REG1    = $00014D ;
+=$00014e					INT_MASK_REG2    = $00014E ;
+=$00014f					INT_MASK_REG3    = $00014F ; FMX Model
+=$01						FNX0_INT00_SOF        = $01  ;Start of Frame @ 60FPS
+=$02						FNX0_INT01_SOL        = $02  ;Start of Line (Programmable)
+=$04						FNX0_INT02_TMR0       = $04  ;Timer 0 Interrupt
+=$08						FNX0_INT03_TMR1       = $08  ;Timer 1 Interrupt
+=$10						FNX0_INT04_TMR2       = $10  ;Timer 2 Interrupt
+=$20						FNX0_INT05_RTC        = $20  ;Real-Time Clock Interrupt
+=$40						FNX0_INT06_FDC        = $40  ;Floppy Disk Controller
+=$80						FNX0_INT07_MOUSE      = $80  ; Mouse Interrupt (INT12 in SuperIO IOspace)
+=$01						FNX1_INT00_KBD        = $01  ;Keyboard Interrupt
+=$02						FNX1_INT01_COL0       = $02  ;VICKY_II (INT2) Sprite Collision
+=$04						FNX1_INT02_COL1       = $04  ;VICKY_II (INT3) Bitmap Collision
+=$08						FNX1_INT03_COM2       = $08  ;Serial Port 2
+=$10						FNX1_INT04_COM1       = $10  ;Serial Port 1
+=$20						FNX1_INT05_MPU401     = $20  ;Midi Controller Interrupt
+=$40						FNX1_INT06_LPT        = $40  ;Parallel Port
+=$80						FNX1_INT07_SDCARD     = $80  ;SD Card Controller Interrupt (CH376S)
+=$01						FNX2_INT00_OPL3       = $01  ;OPl3
+=$02						FNX2_INT01_GABE_INT0  = $02  ;GABE (INT0) - TBD
+=$04						FNX2_INT02_GABE_INT1  = $04  ;GABE (INT1) - TBD
+=$08						FNX2_INT03_VDMA       = $08  ;VICKY_II (INT4) - VDMA Interrupt
+=$10						FNX2_INT04_COL2       = $10  ;VICKY_II (INT5) Tile Collision
+=$20						FNX2_INT05_GABE_INT2  = $20  ;GABE (INT2) - TBD
+=$40						FNX2_INT06_EXT        = $40  ;External Expansion
+=$80						FNX2_INT07_SDCARD_INS = $80  ; SDCARD Insertion
+=$01						FNX3_INT00_OPN2       = $01  ;OPN2
+=$02						FNX3_INT01_OPM        = $02  ;OPM
+=$04						FNX3_INT02_IDE        = $04  ;HDD IDE INTERRUPT
+=$08						FNX3_INT03_TBD        = $08  ;TBD
+=$10						FNX3_INT04_TBD        = $10  ;TBD
+=$20						FNX3_INT05_TBD        = $20  ;GABE (INT2) - TBD
+=$40						FNX3_INT06_TBD        = $40  ;External Expansion
+=$80						FNX3_INT07_TBD        = $80  ; SDCARD Insertion
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/super_io_def.asm
+
+=$af1100					PME_STS_REG     = $AF1100
+=$af1102					PME_EN_REG		  = $AF1102
+=$af1104					PME_STS1_REG		= $AF1104
+=$af1105					PME_STS2_REG		= $AF1105
+=$af1106					PME_STS3_REG		= $AF1106
+=$af1107					PME_STS4_REG		= $AF1107
+=$af1108					PME_STS5_REG		= $AF1108
+=$af110a					PME_EN1_REG     = $AF110A
+=$af110b					PME_EN2_REG     = $AF110B
+=$af110c					PME_EN3_REG     = $AF110C
+=$af110d					PME_EN4_REG     = $AF110D
+=$af110e					PME_EN5_REG     = $AF110E
+=$af1110					SMI_STS1_REG		= $AF1110
+=$af1111					SMI_STS2_REG		= $AF1111
+=$af1112					SMI_STS3_REG		= $AF1112
+=$af1113					SMI_STS4_REG		= $AF1113
+=$af1114					SMI_STS5_REG		= $AF1114
+=$af1116					SMI_EN1_REG     = $AF1116
+=$af1117					SMI_EN2_REG     = $AF1117
+=$af1118					SMI_EN3_REG     = $AF1118
+=$af1119					SMI_EN4_REG     = $AF1119
+=$af111a					SMI_EN5_REG     = $AF111A
+=$af111c					MSC_ST_REG      = $AF111C
+=$af111e					FORCE_DISK_CHANGE       = $AF111E
+=$af111f					FLOPPY_DATA_RATE        = $AF111F
+=$af1120					UART1_FIFO_CTRL_SHDW    = $AF1120
+=$af1121					UART2_FIFO_CTRL_SHDW    = $AF1121
+=$af1122					DEV_DISABLE_REG         = $AF1122
+=$af1123					GP10_REG    		= $AF1123
+=$af1124					GP11_REG    		= $AF1124
+=$af1125					GP12_REG    		= $AF1125
+=$af1126					GP13_REG    		= $AF1126
+=$af1127					GP14_REG    		= $AF1127
+=$af1128					GP15_REG    		= $AF1128
+=$af1129					GP16_REG    		= $AF1129
+=$af112a					GP17_REG    		= $AF112A
+=$af112b					GP20_REG    		= $AF112B
+=$af112c					GP21_REG    		= $AF112C
+=$af112d					GP22_REG		= $AF112D
+=$af112f					GP24_REG		= $AF112F
+=$af1130					GP25_REG		= $AF1130
+=$af1131					GP26_REG		= $AF1131
+=$af1132					GP27_REG		= $AF1132
+=$af1133					GP30_REG		= $AF1133
+=$af1134					GP31_REG		= $AF1134
+=$af1135					GP32_REG		= $AF1135
+=$af1136					GP33_REG		= $AF1136
+=$af1137					GP34_REG		= $AF1137
+=$af1138					GP35_REG		= $AF1138
+=$af1139					GP36_REG		= $AF1139
+=$af113a					GP37_REG		= $AF113A
+=$af113b					GP40_REG		= $AF113B
+=$af113c					GP41_REG		= $AF113C
+=$af113d					GP42_REG		= $AF113D
+=$af113e					GP43_REG		= $AF113E
+=$af113f					GP50_REG		= $AF113F
+=$af1140					GP51_REG		= $AF1140
+=$af1141					GP52_REG		= $AF1141
+=$af1142					GP53_REG		= $AF1142
+=$af1143					GP54_REG		= $AF1143
+=$af1144					GP55_REG		= $AF1144
+=$af1145					GP56_REG		= $AF1145
+=$af1146					GP57_REG		= $AF1146
+=$af1147					GP60_REG		= $AF1147
+=$af1148					GP61_REG		= $AF1148
+=$af114b					GP1_REG			= $AF114B
+=$af114c					GP2_REG			= $AF114C
+=$af114d					GP3_REG			= $AF114D
+=$af114e					GP4_REG			= $AF114E
+=$af114f					GP5_REG			= $AF114F
+=$af1150					GP6_REG			= $AF1150
+=$af1156					FAN1_REG		        = $AF1156
+=$af1157					FAN2_REG            = $AF1157
+=$af1158					FAN_CTRL_REG  	    = $AF1158
+=$af1159					FAN1_TACH_REG       = $AF1159
+=$af115a					FAN2_TACH_REG       = $AF115A
+=$af115b					FAN1_PRELOAD_REG    = $AF115B
+=$af115c					FAN2_PRELOAD_REG    = $AF115C
+=$af115d					LED1_REG    		    = $AF115D
+=$af115e					LED2_REG    		    = $AF115E
+=$af115f					KEYBOARD_SCAN_CODE	= $AF115F
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/keyboard_def.asm
+
+=$af1807					    STATUS_PORT 	= $AF1807
+=$af1807					    KBD_CMD_BUF		= $AF1807
+=$af1803					    KBD_OUT_BUF 	= $AF1803
+=$af1803					    KBD_INPT_BUF	= $AF1803
+=$af1803					    KBD_DATA_BUF	= $AF1803
+=$af180a					    PORT_A		    = $AF180A   ;This is a Timing Register, the value is hard coded, so there is no need to use those
+=$af180b					    PORT_B			= $AF180B   ;This is a Timing Register, the value is hard coded, so there is no need to use those
+=$01						OUT_BUF_FULL    = $01
+=$02						INPT_BUF_FULL	= $02
+=$04						SYS_FLAG		= $04
+=$08						CMD_DATA		= $08
+=$10						KEYBD_INH       = $10
+=$20						TRANS_TMOUT	    = $20
+=$40						RCV_TMOUT		= $40
+=$80						PARITY_EVEN		= $80
+=$10						INH_KEYBOARD	= $10
+=$ae						KBD_ENA			= $AE
+=$ad						KBD_DIS			= $AD
+=$f1						KB_MENU			= $F1
+=$f4						KB_ENABLE		= $F4
+=$f7						KB_MAKEBREAK    = $F7
+=$fe						KB_ECHO			= $FE
+=$ff						KB_RESET		= $FF
+=$ed						KB_LED_CMD		= $ED
+=$aa						KB_OK			= $AA
+=$fa						KB_ACK			= $FA
+=$ff						KB_OVERRUN		= $FF
+=$fe						KB_RESEND		= $FE
+=$f0						KB_BREAK		= $F0
+=$10						KB_FA			= $10
+=$20						KB_FE			= $20
+=$40						KB_PR_LED		= $40
+=$01						KB_SCROLL_LOCK  = $01
+=$02						KB_NUM_LOCK     = $02
+=$04						KB_CAPS_LOCK    = $04
+=$80						KB_CTRL_C = $80             ; CTRL-C was pressed
+=$60						KB_CREDITS = $60            ; Credits key was pressed
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/RTC_def.asm
+
+=$af0800					RTC_SEC       = $AF0800 ;Seconds Register
+=$af0801					RTC_SEC_ALARM = $AF0801 ;Seconds Alarm Register
+=$af0802					RTC_MIN       = $AF0802 ;Minutes Register
+=$af0803					RTC_MIN_ALARM = $AF0803 ;Minutes Alarm Register
+=$af0804					RTC_HRS       = $AF0804 ;Hours Register
+=$af0805					RTC_HRS_ALARM = $AF0805 ;Hours Alarm Register
+=$af0806					RTC_DAY       = $AF0806 ;Day Register
+=$af0807					RTC_DAY_ALARM = $AF0807 ;Day Alarm Register
+=$af0808					RTC_DOW       = $AF0808 ;Day of Week Register
+=$af0809					RTC_MONTH     = $AF0809 ;Month Register
+=$af080a					RTC_YEAR      = $AF080A ;Year Register
+=$af080b					RTC_RATES     = $AF080B ;Rates Register
+=$af080c					RTC_ENABLE    = $AF080C ;Enables Register
+=$af080d					RTC_FLAGS     = $AF080D ;Flags Register
+=$af080e					RTC_CTRL      = $AF080E ;Control Register
+=$af080f					RTC_CENTURY   = $AF080F ;Century Register
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/io_def.asm
+
+=0						CHAN_CONSOLE  = 0           ; ID for screen and keyboard access
+=1						CHAN_COM1     = 1           ; ID for serial access on COM1 (external port)
+=2						CHAN_COM2     = 2           ; ID for serial access on COM2 (internal port)
+=3						CHAN_LPT      = 3           ; ID for parallel port
+=$afe810					SDCARD_DATA   = $AFE810     ;(R/W) SDCARD (CH376S) Data PORT_A (A0 = 0)
+=$afe811					SDCARD_CMD    = $AFE811     ;(R/W) SDCARD (CH376S) CMD/STATUS Port (A0 = 1)
+=$afe812					SDCARD_STAT   = $AFE812     ;(R) SDCARD (Bit[0] = CD, Bit[1] = WP)
+=$afe900					CODEC_DATA_LO = $AFE900     ;(W) LSB of Add/Data Reg to Control CODEC See WM8776 Spec
+=$afe901					CODEC_DATA_HI = $AFE901     ;(W) MSB od Add/Data Reg to Control CODEC See WM8776 Spec
+=$afe902					CODEC_WR_CTRL = $AFE902     ;(W) Bit[0] = 1 -> Start Writing the CODEC Control Register
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/Trinity_CFP9301_def.asm
+
+=$afe800					JOYSTICK0           = $AFE800   ;(R) Joystick 0 - J7 (next to SD Card)
+=$afe801					JOYSTICK1           = $AFE801   ;(R) Joystick 1 - J8
+=$afe802					JOYSTICK2           = $AFE802   ;(R) Joystick 2 - J9
+=$afe803					JOYSTICK3           = $AFE803   ;(R) Joystick 3 - J10 (Next to Buzzer)
+=$afe804					JOYSTICK_MODE       = $AFE804
+=$01						NES_SNES_EN0        = $01       ; Enable the NES/SNES Mode on Port 0
+=$02						NES_SNES_EN1        = $02       ; Enable the NES/SNES Mode on Port 1
+=$04						NES_SNES_JOY        = $04       ; 0 = NES, 1 = SNES
+=$40						NES_SNES_DONE       = $40       ; Poll to see if the Deserializer is done
+=$80						NES_SNES_TRIG       = $80       ; Set to start the Serializer
+=$afe805					REVOFPCB_C          = $AFE805   ; You should read the ASCCII for "C"
+=$afe806					REVOFPCB_4          = $AFE806   ; You should read the ASCCII for "4"
+=$afe807					REVOFPCB_A          = $AFE807   ; You should read the ASCCII for "A"
+=$afe808					NES_SNES0_DAT_LO    = $AFE808   ; Contains the 8bits From NES and SNES
+=$afe809					SNES0_DAT_HI0       = $AFE809   ; Contains the extra 4 bit from the SNES Controller
+=$afe80a					NES_SNES1_DAT_LO    = $AFE80A
+=$afe80b					SNES1_DAT_HI0       = $AFE80B
+=$afe80c					CFP9301_REV         = $AFE80C   ; Hardware Revision of the CPLD Code
+=$afe80d					DIP_USER            = $AFE80D   ; Dip Switch 3/4/5 can be user Defined
+=$afe80e					DIP_BOOTMODE        = $AFE80E
+=$01						BOOT_MODE0          = $01
+=$02						BOOT_MODE1          = $02
+=$80						HD_INSTALLED        = $80
+=$00						DIP_BOOT_IDE        = $00
+=$01						DIP_BOOT_SDCARD     = $01
+=$02						DIP_BOOT_FLOPPY     = $02
+=$03						DIP_BOOT_BASIC      = $03
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/Unity_CFP9307_def.asm
+
+=$afe830					IDE_DATA      = $AFE830 ; 8-Bit Access here Only
+=$afe831					IDE_ERROR     = $AFE831 ; Error Information register (only read when there is an error ) - Probably clears Error Bits
+=$afe832					IDE_SECT_CNT  = $AFE832 ; Sector Count Register (also used to pass parameter for timeout for IDLE modus Command)
+=$afe833					IDE_SECT_SRT  = $AFE833 ; Start Sector Register (0 = 256), so start @ 1
+=$afe834					IDE_CLDR_LO   = $AFE834 ; Low Byte of Cylinder Numnber {7:0}
+=$afe835					IDE_CLDR_HI   = $AFE835 ;  Hi Byte of Cylinder Number {9:8} (1023-0).
+=$afe836					IDE_HEAD      = $AFE836 ; Head, device select, {3:0} HEad Number, 4 -> 0:Master, 1:Slave, {7:5} = 101 (legacy);
+=$afe837					IDE_CMD_STAT  = $AFE837 ; Command/Status Register - Reading this will clear the Interrupt Registers
+=$afe838					IDE_DATA_LO   = $AFE838 ; 16-bit access here
+=$afe839					IDE_DATA_HI   = $AFE839 ;
+=$01						IDE_ERR_AMNF = $01      ; Error: Address mark not found
+=$02						IDE_ERR_TKZNF = $02     ; Error: Track 0 not found
+=$04						IDE_ERR_ABRT = $04      ; Error: Aborted command
+=$08						IDE_ERR_MCR = $08       ; Error: Media change request
+=$10						IDE_ERR_IDNF = $10      ; Error: ID not found
+=$20						IDE_ERR_MC = $20        ; Error: Media change
+=$40						IDE_ERR_UNC = $40       ; Error: Uncorrectable data error
+=$80						IDE_ERR_BBK = $80       ; Error: Bad block detected
+=$80						IDE_STAT_BSY = $80      ; BSY (Busy) is set whenever the device has control of the command Block Registers.
+=$40						IDE_STAT_DRDY = $40     ; DRDY (Device Ready) is set to indicate that the device is capable of accepting all command codes.
+=$20						IDE_STAT_DF = $20       ; DF (Device Fault) indicates a device fault error has been detected.
+=$10						IDE_STAT_DSC = $10      ; DSC (Device Seek Complete) indicates that the device heads are settled over a track.
+=$08						IDE_STAT_DRQ = $08      ; DRQ (Data Request) indicates that the device is ready to transfer a word or byte of data between
+=$04						IDE_STAT_CORR = $04     ; CORR (Corrected Data) is used to indicate a correctable data error.
+=$02						IDE_STAT_IDX = $02      ; Vendor specific bit
+=$01						IDE_STAT_ERR = $01      ; ERR (Error) indicates that an error occurred during execution of the previous command.
+=$ec						IDE_CMD_IDENTIFY = $EC      ; Get device identification data
+=$21						IDE_CMD_READ_SECTOR = $21   ; Read 1 or more sectors
+=$30						IDE_CMD_WRITE_SECTOR = $30  ; Write 1 or more sectors
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/GABE_Control_Registers_def.asm
+
+=$afe880					GABE_MSTR_CTRL      = $AFE880
+=$01						GABE_CTRL_PWR_LED   = $01     ; Controls the LED in the Front of the case (Next to the reset button)
+=$02						GABE_CTRL_SDC_LED   = $02     ; Controls the LED in the Front of the Case (Next to SDCard)
+=$04						GABE_CTRL_STS_LED0  = $04     ; Control Status LED0 (General Use) - C256 Foenix U Only
+=$08						GABE_CTRL_STS_LED1  = $08     ; Control Status LED0 (General Use) - C256 Foenix U Only
+=$10						GABE_CTRL_BUZZER    = $10     ; Controls the Buzzer
+=$80						GABE_CTRL_WRM_RST   = $80     ; Warm Reset (needs to Setup other registers)
+=$afe881					GABE_LED_FLASH_CTRL = $AFE881  ; Flashing LED Control
+=$01						GABE_LED0_FLASH_CTRL = $01     ; 0- Automatic Flash 1 - Bypass Flash Timer (Use GABE_CTRL_STS_LED0 to manually control)
+=$02						GABE_LED1_FLASH_CTRL = $02     ; 0- Automatic Flash 1 - Bypass Flash Timer (Use GABE_CTRL_STS_LED1 to manually control)
+=$10						GABE_LD0_FLASH_FRQ0   = $10     ; 1 - Bypass Flash Timer (Use GABE_CTRL_STS_LED0 to manually control)
+=$20						GABE_LD0_FLASH_FRQ1   = $20     ; 1 - Bypass Flash Timer (Use GABE_CTRL_STS_LED0 to manually control)
+=$40						GABE_LD1_FLASH_FRQ0   = $40     ; 1 - Bypass Flash Timer (Use GABE_CTRL_STS_LED0 to manually control)
+=$80						GABE_LD1_FLASH_FRQ1   = $80     ; 1 - Bypass Flash Timer (Use GABE_CTRL_STS_LED0 to manually control)
+=$afe882					GABE_RST_AUTH0      = $AFE882 ; Must Contain the BYTE $AD for Reset to Activate
+=$afe883					GABE_RST_AUTH1      = $AFE883 ; Must Contain the BYTE $DE for Reset to Activate
+=$afe884					GABE_RNG_DAT_LO     = $AFE884 ; Low Part of 16Bit RNG Generator
+=$afe885					GABE_RNG_DAT_HI     = $AFE885 ; Hi Part of 16Bit RNG Generator
+=$afe884					GABE_RNG_SEED_LO    = $AFE884 ; Low Part of 16Bit RNG Generator
+=$afe885					GABE_RNG_SEED_HI    = $AFE885 ; Hi Part of 16Bit RNG Generator
+=$afe886					GABE_RNG_STAT       = $AFE886 ;
+=$80						GABE_RNG_LFSR_DONE  = $80     ; indicates that Output = SEED Database
+=$afe886					GABE_RNG_CTRL       = $AFE886 ;
+=$01						GABE_RNG_CTRL_EN    = $01     ; Enable the LFSR BLOCK_LEN
+=$02						GABE_RNG_CTRL_DV    = $02     ; After Setting the Seed Value, Toggle that Bit for it be registered
+=$afe887					GABE_SYS_STAT       = $AFE887 ;
+=$01						GABE_SYS_STAT_MID0  = $01     ; Machine ID -- LSB
+=$02						GABE_SYS_STAT_MID1  = $02     ; Machine ID --
+=$04						GABE_SYS_STAT_MID2  = $04     ; Machine ID -- MSB
+=$10						GABE_SYS_STAT_EXP   = $10     ; if Zero, there is an Expansion Card Preset
+=$40						GABE_SYS_STAT_CPUA  = $40     ; Indicates the (8bit/16bit) Size of the Accumulator - Not Implemented
+=$80						GABE_SYS_STAT_CPUX  = $80     ; Indicates the (8bit/16bit) Size of the Accumulator - Not Implemented
+=$afe88a					GABE_SUBVERSION_LO  = $AFE88A
+=$afe88b					GABE_SUBVERSION_HI  = $AFE88B
+=$afe88c					GABE_VERSION_LO     = $AFE88C
+=$afe88d					GABE_VERSION_HI     = $AFE88D
+=$afe88e					GABE_MODEL_LO       = $AFE88E
+=$afe88f					GABE_MODEL_HI       = $AFE88F
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/SID_def.asm
+
+=$afe400					SID0_V1_FREQ_LO    = $AFE400 ;SID - L - Voice 1 (Write Only) - FREQ LOW
+=$afe401					SID0_V1_FREQ_HI    = $AFE401 ;SID - L - Voice 1 (Write Only) - FREQ HI
+=$afe402					SID0_V1_PW_LO      = $AFE402 ;SID - L - Voice 1 (Write Only) - PW LOW
+=$afe403					SID0_V1_PW_HI      = $AFE403 ;SID - L - Voice 1 (Write Only) - PW HI
+=$afe404					SID0_V1_CTRL       = $AFE404 ;SID - L - Voice 1 (Write Only) - CTRL REG
+=$afe405					SID0_V1_ATCK_DECY  = $AFE405 ;SID - L - Voice 1 (Write Only) - ATTACK / DECAY
+=$afe406					SID0_V1_SSTN_RLSE  = $AFE406 ;SID - L - Voice 1 (Write Only) - SUSTAIN / RELEASE
+=$afe407					SID0_V2_FREQ_LO    = $AFE407 ;SID - L - Voice 2 (Write Only) - FREQ LOW
+=$afe408					SID0_V2_FREQ_HI    = $AFE408 ;SID - L - Voice 2 (Write Only) - FREQ HI
+=$afe409					SID0_V2_PW_LO      = $AFE409 ;SID - L - Voice 2 (Write Only) - PW LOW
+=$afe40a					SID0_V2_PW_HI      = $AFE40A ;SID - L - Voice 2 (Write Only) - PW HI
+=$afe40b					SID0_V2_CTRL       = $AFE40B ;SID - L - Voice 2 (Write Only) - CTRL REG
+=$afe40c					SID0_V2_ATCK_DECY  = $AFE40C ;SID - L - Voice 2 (Write Only) - ATTACK / DECAY
+=$afe40d					SID0_V2_SSTN_RLSE  = $AFE40D ;SID - L - Voice 2 (Write Only) - SUSTAIN / RELEASE
+=$afe40e					SID0_V3_FREQ_LO    = $AFE40E ;SID - L - Voice 3 (Write Only) - FREQ LOW
+=$afe40f					SID0_V3_FREQ_HI    = $AFE40F ;SID - L - Voice 3 (Write Only) - FREQ HI
+=$afe410					SID0_V3_PW_LO      = $AFE410 ;SID - L - Voice 3 (Write Only) - PW LOW
+=$afe411					SID0_V3_PW_HI      = $AFE411 ;SID - L - Voice 3 (Write Only) - PW HI
+=$afe412					SID0_V3_CTRL       = $AFE412 ;SID - L - Voice 3 (Write Only) - CTRL REG
+=$afe413					SID0_V3_ATCK_DECY  = $AFE413 ;SID - L - Voice 3 (Write Only) - ATTACK / DECAY
+=$afe414					SID0_V3_SSTN_RLSE  = $AFE414 ;SID - L - Voice 3 (Write Only) - SUSTAIN / RELEASE
+=$afe415					SID0_FC_LO         = $AFE415 ;SID - L - Filter (Write Only) - FC LOW
+=$afe416					SID0_FC_HI         = $AFE416 ;SID - L - Filter (Write Only) - FC HI
+=$afe417					SID0_RES_FILT      = $AFE417 ;SID - L - Filter (Write Only) - RES / FILT
+=$afe418					SID0_MODE_VOL      = $AFE418 ;SID - L - Filter (Write Only) - MODE / VOL
+=$afe419					SID0_POT_X         = $AFE419 ;SID - L - Misc (Read Only) - POT X (C256 - NOT USED)
+=$afe41a					SID0_POT_Y         = $AFE41A ;SID - L - Misc (Read Only) - POT Y (C256 - NOT USED)
+=$afe41b					SID0_OSC3_RND      = $AFE41B ;SID - L - Misc (Read Only) - OSC3 / RANDOM
+=$afe41c					SID0_ENV3          = $AFE41C ;SID - L - Misc (Read Only)  - ENV3
+=$afe41d					SID0_NOT_USED0     = $AFE41D ;SID - L - NOT USED
+=$afe41e					SID0_NOT_USED1     = $AFE41E ;SID - L - NOT USED
+=$afe41f					SID0_NOT_USED2     = $AFE41F ;SID - L - NOT USED
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_GENERAL_def.asm
+
+=$af0000					MASTER_CTRL_REG_L	      = $AF0000
+=$01						Mstr_Ctrl_Text_Mode_En  = $01       ; Enable the Text Mode
+=$02						Mstr_Ctrl_Text_Overlay  = $02       ; Enable the Overlay of the text mode on top of Graphic Mode (the Background Color is ignored)
+=$04						Mstr_Ctrl_Graph_Mode_En = $04       ; Enable the Graphic Mode
+=$08						Mstr_Ctrl_Bitmap_En     = $08       ; Enable the Bitmap Module In Vicky
+=$10						Mstr_Ctrl_TileMap_En    = $10       ; Enable the Tile Module in Vicky
+=$20						Mstr_Ctrl_Sprite_En     = $20       ; Enable the Sprite Module in Vicky
+=$40						Mstr_Ctrl_GAMMA_En      = $40       ; this Enable the GAMMA correction - The Analog and DVI have different color value, the GAMMA is great to correct the difference
+=$80						Mstr_Ctrl_Disable_Vid   = $80       ; This will disable the Scanning of the Video hence giving 100% bandwith to the CPU
+=$af0001					MASTER_CTRL_REG_H       = $AF0001
+=$01						Mstr_Ctrl_Video_Mode0   = $01       ; 0 - 640x480 (Clock @ 25.175Mhz), 1 - 800x600 (Clock @ 40Mhz)
+=$02						Mstr_Ctrl_Video_Mode1   = $02       ; 0 - No Pixel Doubling, 1- Pixel Doubling (Reduce the Pixel Resolution by 2)
+=$af0002					GAMMA_CTRL_REG          = $AF0002
+=$01						GAMMA_Ctrl_Input        = $01 ; 0 = DipSwitch Chooses GAMMA on/off , 1- Software Control
+=$02						GAMMA_Ctrl_Soft         = $02 ; 0 = GAMMA Table is not Applied, 1 = GAMMA Table is Applied
+=$08						GAMMA_DP_SW_VAL         = $08 ; READ ONLY - Actual DIP Switch Value
+=$10						HIRES_DP_SW_VAL         = $10 ; READ ONLY - 0 = Hi-Res on BOOT ON, 1 = Hi-Res on BOOT OFF
+=$af0003					VKY_RESERVED_01         = $AF0003
+=$01						Border_Ctrl_Enable      = $01
+=$af0004					BORDER_CTRL_REG         = $AF0004 ; Bit[0] - Enable (1 by default)  Bit[4..6]: X Scroll Offset ( Will scroll Left) (Acceptable Value: 0..7)
+=$af0005					BORDER_COLOR_B          = $AF0005
+=$af0006					BORDER_COLOR_G          = $AF0006
+=$af0007					BORDER_COLOR_R          = $AF0007
+=$af0008					BORDER_X_SIZE           = $AF0008; X-  Values: 0 - 32 (Default: 32)
+=$af0009					BORDER_Y_SIZE           = $AF0009; Y- Values 0 -32 (Default: 32)
+=$af000d					BACKGROUND_COLOR_B      = $AF000D ; When in Graphic Mode, if a pixel is "0" then the Background pixel is chosen
+=$af000e					BACKGROUND_COLOR_G      = $AF000E
+=$af000f					BACKGROUND_COLOR_R      = $AF000F ;
+=$af0010					VKY_TXT_CURSOR_CTRL_REG = $AF0010   ;[0]  Enable Text Mode
+=$01						Vky_Cursor_Enable       = $01
+=$02						Vky_Cursor_Flash_Rate0  = $02       ; 00 - 1/Sec, 01 - 2/Sec, 10 - 4/Sec, 11 - 5/Sec
+=$04						Vky_Cursor_Flash_Rate1  = $04
+=$08						Vky_Cursor_FONT_Page0   = $08       ; Pick Font Page 0 or Font Page 1
+=$10						Vky_Cursor_FONT_Page1   = $10       ; Pick Font Page 0 or Font Page 1
+=$af0011					VKY_TXT_START_ADD_PTR   = $AF0011   ; This is an offset to change the Starting address of the Text Mode Buffer (in x)
+=$af0012					VKY_TXT_CURSOR_CHAR_REG = $AF0012
+=$af0013					VKY_TXT_CURSOR_COLR_REG = $AF0013
+=$af0014					VKY_TXT_CURSOR_X_REG_L  = $AF0014
+=$af0015					VKY_TXT_CURSOR_X_REG_H  = $AF0015
+=$af0016					VKY_TXT_CURSOR_Y_REG_L  = $AF0016
+=$af0017					VKY_TXT_CURSOR_Y_REG_H  = $AF0017
+=$af001b					VKY_LINE_IRQ_CTRL_REG   = $AF001B ;[0] - Enable Line 0, [1] -Enable Line 1
+=$af001c					VKY_LINE0_CMP_VALUE_LO  = $AF001C ;Write Only [7:0]
+=$af001d					VKY_LINE0_CMP_VALUE_HI  = $AF001D ;Write Only [3:0]
+=$af001e					VKY_LINE1_CMP_VALUE_LO  = $AF001E ;Write Only [7:0]
+=$af001f					VKY_LINE1_CMP_VALUE_HI  = $AF001F ;Write Only [3:0]
+=$af001c					VKY_INFO_CHIP_NUM_L     = $AF001C
+=$af001d					VKY_INFO_CHIP_NUM_H     = $AF001D
+=$af001e					VKY_INFO_CHIP_VER_L     = $AF001E
+=$af001f					VKY_INFO_CHIP_VER_H     = $AF001F
+=$af0500					MOUSE_PTR_GRAP0_START    = $AF0500 ; 16 x 16 = 256 Pixels (Grey Scale) 0 = Transparent, 1 = Black , 255 = White
+=$af05ff					MOUSE_PTR_GRAP0_END      = $AF05FF ; Pointer 0
+=$af0600					MOUSE_PTR_GRAP1_START    = $AF0600 ;
+=$af06ff					MOUSE_PTR_GRAP1_END      = $AF06FF ; Pointer 1
+=$af0700					MOUSE_PTR_CTRL_REG_L    = $AF0700 ; Bit[0] Enable, Bit[1] = 0  ( 0 = Pointer0, 1 = Pointer1)
+=$af0701					MOUSE_PTR_CTRL_REG_H    = $AF0701 ;
+=$af0702					MOUSE_PTR_X_POS_L       = $AF0702 ; X Position (0 - 639) (Can only read now) Writing will have no effect
+=$af0703					MOUSE_PTR_X_POS_H       = $AF0703 ;
+=$af0704					MOUSE_PTR_Y_POS_L       = $AF0704 ; Y Position (0 - 479) (Can only read now) Writing will have no effect
+=$af0705					MOUSE_PTR_Y_POS_H       = $AF0705 ;
+=$af0706					MOUSE_PTR_BYTE0         = $AF0706 ; Byte 0 of Mouse Packet (you must write 3 Bytes)
+=$af0707					MOUSE_PTR_BYTE1         = $AF0707 ; Byte 1 of Mouse Packet (if you don't, then )
+=$af0708					MOUSE_PTR_BYTE2         = $AF0708 ; Byte 2 of Mouse Packet (state Machine will be jammed in 1 state)
+=$af070b					C256F_MODEL_MAJOR       = $AF070B ;
+=$af070c					C256F_MODEL_MINOR       = $AF070C ;
+=$af070d					FPGA_DOR                = $AF070D ;
+=$af070e					FPGA_MOR                = $AF070E ;
+=$af070f					FPGA_YOR                = $AF070F ;
+=$af0900					VMEM2CPU_CTRL_REG      = $AF0900  ;
+=$01						VMEM2CPU_Clear_FIFO    = $01        ; Setting this to 1 will flush (Reset) the FIFO, clear it after to return to normal function
+=$02						VMEM2CPU_Intterupt     = $02        ; This is not implemented because there is not enough Interrupt line on the FMX
+=$af0901					VMEM2CPU_Data_Port     = $AF0901    ; This is a Byte Port of the data that you have requested. (Output of the FIFO)
+=$af0902					VMEM2CPU_Fifo_Count_LO = $AF0902    ; FIFO Count Lo (number of byte in the FIFO) FIFO Count is 10bits, Count_Bit0 to Count_Bit7 of Count
+=$af0903					VMEM2CPU_Fifo_Count_HI = $AF0903    ; FIFO Count Hi, Bit 0 = Count_Bit8, Bit 1 = Count_Bit9
+=$80						VMEM2CPU_Fifo_Empty    = $80        ; Bit 7 of VMEM2CPU_Fifo_Count_HI, when 1, the FIFO is empty.
+=$af1f40					FG_CHAR_LUT_PTR         = $AF1F40
+=$af1f80					BG_CHAR_LUT_PTR		    = $AF1F80
+=$af2000					GRPH_LUT0_PTR		    = $AF2000
+=$af2400					GRPH_LUT1_PTR		    = $AF2400
+=$af2800					GRPH_LUT2_PTR		    = $AF2800
+=$af2c00					GRPH_LUT3_PTR		    = $AF2C00
+=$af3000					GRPH_LUT4_PTR		    = $AF3000
+=$af3400					GRPH_LUT5_PTR		    = $AF3400
+=$af3800					GRPH_LUT6_PTR		    = $AF3800
+=$af3c00					GRPH_LUT7_PTR		    = $AF3C00
+=$af4000					GAMMA_B_LUT_PTR		    = $AF4000
+=$af4100					GAMMA_G_LUT_PTR		    = $AF4100
+=$af4200					GAMMA_R_LUT_PTR		    = $AF4200
+=$af8000					FONT_MEMORY_BANK0       = $AF8000     ;$AF8000 - $AF87FF
+=$afa000					CS_TEXT_MEM_PTR         = $AFA000
+=$afc000					CS_COLOR_MEM_PTR        = $AFC000
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_SDMA_def.asm
+
+=$af0420					SDMA_CTRL_REG0           = $AF0420
+=$01						SDMA_CTRL0_Enable        = $01
+=$02						SDMA_CTRL0_1D_2D         = $02     ; 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer
+=$04						SDMA_CTRL0_TRF_Fill      = $04     ; 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write"
+=$08						SDMA_CTRL0_Int_Enable    = $08     ; Set to 1 to Enable the Generation of Interrupt when the Transfer is over.
+=$10						SDMA_CTRL0_SysRAM_Src    = $10     ; Set to 1 to Indicate that the Source is the System Ram Memory
+=$20						SDMA_CTRL0_SysRAM_Dst    = $20     ; Set to 1 to Indicate that the Destination is the System Ram Memory
+=$40						SDMA_CTLR0_RSVD          = $40     ;
+=$80						SDMA_CTRL0_Start_TRF     = $80     ; Set to 1 To Begin Process, Need to Cleared before, you can start another
+=$af0421					SDMA_CTRL_REG1           = $AF0421 ; Write Only - Byte to Write in the Fill Function
+=$01						SDMA_CTRL1_IO_Src			   = $01		 ; 1 = Source is an IO Address (ADC, SuperIO, IDE)
+=$02						SDMA_CTRL1_IO_Src16		   = $02		 ; 0 = Src 8Bits Transfer / 1= 16Bits Transfer
+=$04						SDMA_CTRL1_IO_Dst			   = $04		 ; 1 = Destination is an IO Address (DAC, SuperIO, IDE)
+=$08						SDMA_CTRL1_IO_Dst16      = $08     ; 0 = Dst 8bits Transfer / 1= 16bits
+=$af0422					SDMA_SRC_ADDY_L         = $AF0422 ; Pointer to the Source of the Data to be stransfered
+=$af0423					SDMA_SRC_ADDY_M         = $AF0423 ; This needs to be within Vicky's Range ($00_0000 - $3F_0000)
+=$af0424					SDMA_SRC_ADDY_H         = $AF0424
+=$af0425					SDMA_DST_ADDY_L         = $AF0425 ; Destination Pointer within Vicky's video memory Range
+=$af0426					SDMA_DST_ADDY_M         = $AF0426 ; ($00_0000 - $3F_0000)
+=$af0427					SDMA_DST_ADDY_H         = $AF0427
+=$af0428					SDMA_SIZE_L             = $AF0428 ; Maximum Value: $40:0000 (4Megs)
+=$af0429					SDMA_SIZE_M             = $AF0429
+=$af042a					SDMA_SIZE_H             = $AF042A
+=$af042b					SDMA_IGNORED            = $AF042B
+=$af0428					SDMA_X_SIZE_L           = $AF0428 ; Maximum Value: 65535
+=$af0429					SDMA_X_SIZE_H           = $AF0429
+=$af042a					SDMA_Y_SIZE_L           = $AF042A ; Maximum Value: 65535
+=$af042b					SDMA_Y_SIZE_H           = $AF042B
+=$af042c					SDMA_SRC_STRIDE_L       = $AF042C ; Always use an Even Number ( The Engine uses Even Ver of that value)
+=$af042d					SDMA_SRC_STRIDE_H       = $AF042D ;
+=$af042e					SDMA_DST_STRIDE_L       = $AF042E ; Always use an Even Number ( The Engine uses Even Ver of that value)
+=$af042f					SDMA_DST_STRIDE_H       = $AF042F ;
+=$af0430					SDMA_BYTE_2_WRITE       = $AF0430 ; Write Only - Byte to Write in the Fill Function
+=$af0430					SDMA_STATUS_REG         = $AF0430 ; Read only
+=$01						SDMA_STAT_Size_Err       = $01     ; If Set to 1, Overall Size is Invalid
+=$02						SDMA_STAT_Dst_Add_Err    = $02     ; If Set to 1, Destination Address Invalid
+=$04						SDMA_STAT_Src_Add_Err    = $04     ; If Set to 1, Source Address Invalid
+=$08						SDMA_STAT_TimeOut_Err    = $08     ; will be set to 1 if a Timeout occur when transfering between data from and to VRAM
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_VDMA_def.asm
+
+=$af0400					VDMA_CONTROL_REG        = $AF0400
+=$01						VDMA_CTRL_Enable        = $01
+=$02						VDMA_CTRL_1D_2D         = $02     ; 0 - 1D (Linear) Transfer , 1 - 2D (Block) Transfer
+=$04						VDMA_CTRL_TRF_Fill      = $04     ; 0 - Transfer Src -> Dst, 1 - Fill Destination with "Byte2Write"
+=$08						VDMA_CTRL_Int_Enable    = $08     ; Set to 1 to Enable the Generation of Interrupt when the Transfer is over.
+=$10						VDMA_CTRL_SysRAM_Src    = $10     ; Set to 1 to Indicate that the Source is the System Ram Memory
+=$20						VDMA_CTRL_SysRAM_Dst    = $20     ; Set to 1 to Indicate that the Destination is the System Ram Memory
+=$80						VDMA_CTRL_Start_TRF     = $80     ; Set to 1 To Begin Process, Need to Cleared before, you can start another
+=$af0401					VDMA_BYTE_2_WRITE       = $AF0401 ; Write Only - Byte to Write in the Fill Function
+=$af0401					VDMA_STATUS_REG         = $AF0401 ; Read only
+=$01						VDMA_STAT_Size_Err      = $01     ; If Set to 1, Overall Size is Invalid
+=$02						VDMA_STAT_Dst_Add_Err   = $02     ; If Set to 1, Destination Address Invalid
+=$04						VDMA_STAT_Src_Add_Err   = $04     ; If Set to 1, Source Address Invalid
+=$80						VDMA_STAT_VDMA_IPS      = $80     ; If Set to 1, VDMA Transfer in Progress (this Inhibit CPU Access to Mem)
+=$af0402					VDMA_SRC_ADDY_L         = $AF0402 ; Pointer to the Source of the Data to be stransfered
+=$af0403					VDMA_SRC_ADDY_M         = $AF0403 ; This needs to be within Vicky's Range ($00_0000 - $3F_0000)
+=$af0404					VDMA_SRC_ADDY_H         = $AF0404
+=$af0405					VDMA_DST_ADDY_L         = $AF0405 ; Destination Pointer within Vicky's video memory Range
+=$af0406					VDMA_DST_ADDY_M         = $AF0406 ; ($00_0000 - $3F_0000)
+=$af0407					VDMA_DST_ADDY_H         = $AF0407
+=$af0408					VDMA_SIZE_L             = $AF0408 ; Maximum Value: $40:0000 (4Megs)
+=$af0409					VDMA_SIZE_M             = $AF0409
+=$af040a					VDMA_SIZE_H             = $AF040A
+=$af040b					VDMA_IGNORED            = $AF040B
+=$af0408					VDMA_X_SIZE_L           = $AF0408 ; Maximum Value: 65535
+=$af0409					VDMA_X_SIZE_H           = $AF0409
+=$af040a					VDMA_Y_SIZE_L           = $AF040A ; Maximum Value: 65535
+=$af040b					VDMA_Y_SIZE_H           = $AF040B
+=$af040c					VDMA_SRC_STRIDE_L       = $AF040C ; Always use an Even Number ( The Engine uses Even Ver of that value)
+=$af040d					VDMA_SRC_STRIDE_H       = $AF040D ;
+=$af040e					VDMA_DST_STRIDE_L       = $AF040E ; Always use an Even Number ( The Engine uses Even Ver of that value)
+=$af040f					VDMA_DST_STRIDE_H       = $AF040F ;
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_BITMAP_def.asm
+
+=$01						BM_Enable             = $01
+=$00						BM_LUT0               = $00 ;
+=$02						BM_LUT1               = $02 ;
+=$04						BM_LUT2               = $04 ;
+=$06						BM_LUT3               = $06 ;
+=$08						BM_LUT4               = $08 ;
+=$0a						BM_LUT5               = $0A ;
+=$0c						BM_LUT6               = $0C ;
+=$0e						BM_LUT7               = $0E ;
+=$40						BM_Collision_On       = $40 ;
+=$af0100					BM0_CONTROL_REG     = $AF0100
+=$af0101					BM0_START_ADDY_L    = $AF0101
+=$af0102					BM0_START_ADDY_M    = $AF0102
+=$af0103					BM0_START_ADDY_H    = $AF0103
+=$af0104					BM0_X_OFFSET        = $AF0104   ; Not Implemented
+=$af0105					BM0_Y_OFFSET        = $AF0105   ; Not Implemented
+=$af0106					BM0_RESERVED_6      = $AF0106
+=$af0107					BM0_RESERVED_7      = $AF0107
+=$af0108					BM1_CONTROL_REG     = $AF0108
+=$af0109					BM1_START_ADDY_L    = $AF0109
+=$af010a					BM1_START_ADDY_M    = $AF010A
+=$af010b					BM1_START_ADDY_H    = $AF010B
+=$af010c					BM1_X_OFFSET        = $AF010C   ; Not Implemented
+=$af010d					BM1_Y_OFFSET        = $AF010D   ; Not Implemented
+=$af010e					BM1_RESERVED_6      = $AF010E
+=$af010f					BM1_RESERVED_7      = $AF010F
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_TILEMAP_def.asm
+
+=$01						TILE_Enable             = $01
+=$40						TILE_Collision_On       = $40           ; Enable
+=$af0200					TL0_CONTROL_REG         = $AF0200       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
+=$af0201					TL0_START_ADDY_L        = $AF0201       ; Not USed right now - Starting Address to where is the MAP
+=$af0202					TL0_START_ADDY_M        = $AF0202
+=$af0203					TL0_START_ADDY_H        = $AF0203
+=$af0204					TL0_TOTAL_X_SIZE_L      = $AF0204       ; Size of the Map in X Tile Count [9:0] (1024 Max)
+=$af0205					TL0_TOTAL_X_SIZE_H      = $AF0205
+=$af0206					TL0_TOTAL_Y_SIZE_L      = $AF0206       ; Size of the Map in Y Tile Count [9:0]
+=$af0207					TL0_TOTAL_Y_SIZE_H      = $AF0207
+=$af0208					TL0_WINDOW_X_POS_L      = $AF0208       ; Top Left Corner Position of the TileMAp Window in X + Scroll
+=$af0209					TL0_WINDOW_X_POS_H      = $AF0209       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
+=$af020a					TL0_WINDOW_Y_POS_L      = $AF020A       ; Top Left Corner Position of the TileMAp Window in Y
+=$af020b					TL0_WINDOW_Y_POS_H      = $AF020B       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
+=$af020c					TL1_CONTROL_REG         = $AF020C       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
+=$af020d					TL1_START_ADDY_L        = $AF020D       ; Not USed right now - Starting Address to where is the MAP
+=$af020e					TL1_START_ADDY_M        = $AF020E
+=$af020f					TL1_START_ADDY_H        = $AF020F
+=$af0210					TL1_TOTAL_X_SIZE_L      = $AF0210       ; Size of the Map in X Tile Count [9:0] (1024 Max)
+=$af0211					TL1_TOTAL_X_SIZE_H      = $AF0211
+=$af0212					TL1_TOTAL_Y_SIZE_L      = $AF0212       ; Size of the Map in Y Tile Count [9:0]
+=$af0213					TL1_TOTAL_Y_SIZE_H      = $AF0213
+=$af0214					TL1_WINDOW_X_POS_L      = $AF0214       ; Top Left Corner Position of the TileMAp Window in X + Scroll
+=$af0215					TL1_WINDOW_X_POS_H      = $AF0215       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
+=$af0216					TL1_WINDOW_Y_POS_L      = $AF0216       ; Top Left Corner Position of the TileMAp Window in Y
+=$af0217					TL1_WINDOW_Y_POS_H      = $AF0217       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
+=$af0218					TL2_CONTROL_REG         = $AF0218       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
+=$af0219					TL2_START_ADDY_L        = $AF0219       ; Not USed right now - Starting Address to where is the MAP
+=$af021a					TL2_START_ADDY_M        = $AF021A
+=$af021b					TL2_START_ADDY_H        = $AF021B
+=$af021c					TL2_TOTAL_X_SIZE_L      = $AF021C       ; Size of the Map in X Tile Count [9:0] (1024 Max)
+=$af021d					TL2_TOTAL_X_SIZE_H      = $AF021D
+=$af021e					TL2_TOTAL_Y_SIZE_L      = $AF021E       ; Size of the Map in Y Tile Count [9:0]
+=$af021f					TL2_TOTAL_Y_SIZE_H      = $AF021F
+=$af0220					TL2_WINDOW_X_POS_L      = $AF0220       ; Top Left Corner Position of the TileMAp Window in X + Scroll
+=$af0221					TL2_WINDOW_X_POS_H      = $AF0221       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
+=$af0222					TL2_WINDOW_Y_POS_L      = $AF0222       ; Top Left Corner Position of the TileMAp Window in Y
+=$af0223					TL2_WINDOW_Y_POS_H      = $AF0223       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
+=$af0224					TL3_CONTROL_REG         = $AF0224       ; Bit[0] - Enable, Bit[3:1] - LUT Select,
+=$af0225					TL3_START_ADDY_L        = $AF0225       ; Not USed right now - Starting Address to where is the MAP
+=$af0226					TL3_START_ADDY_M        = $AF0226
+=$af0227					TL3_START_ADDY_H        = $AF0227
+=$af0228					TL3_TOTAL_X_SIZE_L      = $AF0228       ; Size of the Map in X Tile Count [9:0] (1024 Max)
+=$af0229					TL3_TOTAL_X_SIZE_H      = $AF0229
+=$af022a					TL3_TOTAL_Y_SIZE_L      = $AF022A       ; Size of the Map in Y Tile Count [9:0]
+=$af022b					TL3_TOTAL_Y_SIZE_H      = $AF022B
+=$af022c					TL3_WINDOW_X_POS_L      = $AF022C       ; Top Left Corner Position of the TileMAp Window in X + Scroll
+=$af022d					TL3_WINDOW_X_POS_H      = $AF022D       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in X
+=$af022e					TL3_WINDOW_Y_POS_L      = $AF022E       ; Top Left Corner Position of the TileMAp Window in Y
+=$af022f					TL3_WINDOW_Y_POS_H      = $AF022F       ; Direction: [14] Scroll: [13:10] Pos: [9:0] in Y
+=$af0280					TILESET0_ADDY_L         = $AF0280   ; Pointer to Tileset 0 [21:0]
+=$af0281					TILESET0_ADDY_M         = $AF0281
+=$af0282					TILESET0_ADDY_H         = $AF0282
+=$af0283					TILESET0_ADDY_CFG       = $AF0283   ; [3] - TileStride256x256
+=$af0284					TILESET1_ADDY_L         = $AF0284
+=$af0285					TILESET1_ADDY_M         = $AF0285
+=$af0286					TILESET1_ADDY_H         = $AF0286
+=$af0287					TILESET1_ADDY_CFG       = $AF0287
+=$af0288					TILESET2_ADDY_L         = $AF0288
+=$af0289					TILESET2_ADDY_M         = $AF0289
+=$af028a					TILESET2_ADDY_H         = $AF028A
+=$af028b					TILESET2_ADDY_CFG       = $AF028B
+=$af028c					TILESET3_ADDY_L         = $AF028C
+=$af028d					TILESET3_ADDY_M         = $AF028D
+=$af028e					TILESET3_ADDY_H         = $AF028E
+=$af028f					TILESET3_ADDY_CFG       = $AF028F
+=$af0290					TILESET4_ADDY_L         = $AF0290
+=$af0291					TILESET4_ADDY_M         = $AF0291
+=$af0292					TILESET4_ADDY_H         = $AF0292
+=$af0293					TILESET4_ADDY_CFG       = $AF0293
+=$af0294					TILESET5_ADDY_L         = $AF0294
+=$af0295					TILESET5_ADDY_M         = $AF0295
+=$af0296					TILESET5_ADDY_H         = $AF0296
+=$af0297					TILESET5_ADDY_CFG       = $AF0297
+=$af0298					TILESET6_ADDY_L         = $AF0298
+=$af0299					TILESET6_ADDY_M         = $AF0299
+=$af029a					TILESET6_ADDY_H         = $AF029A
+=$af029b					TILESET6_ADDY_CFG       = $AF029B
+=$af029c					TILESET7_ADDY_L         = $AF029C
+=$af029d					TILESET7_ADDY_M         = $AF029D
+=$af029e					TILESET7_ADDY_H         = $AF029E
+=$af029f					TILESET7_ADDY_CFG       = $AF029F
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_SPRITE_def.asm
+
+=$01						SPRITE_Enable             = $01
+=$00						SPRITE_LUT0               = $00 ; This is the LUT that the Sprite will use
+=$02						SPRITE_LUT1               = $02
+=$04						SPRITE_LUT2               = $04
+=$06						SPRITE_LUT3               = $06
+=$08						SPRITE_LUT4               = $08
+=$0a						SPRITE_LUT5               = $0A
+=$0c						SPRITE_LUT6               = $0C
+=$0e						SPRITE_LUT7               = $0E
+=$00						SPRITE_DEPTH0             = $00
+=$10						SPRITE_DEPTH1             = $10
+=$20						SPRITE_DEPTH2             = $20
+=$30						SPRITE_DEPTH3             = $30
+=$40						SPRITE_DEPTH4             = $40
+=$50						SPRITE_DEPTH5             = $50
+=$60						SPRITE_DEPTH6             = $60
+=$80						SPRITE_Collision_On       = $80 ; Enable the Collision Detection
+=$af0c00					SP00_CONTROL_REG        = $AF0C00
+=$af0c01					SP00_ADDY_PTR_L         = $AF0C01
+=$af0c02					SP00_ADDY_PTR_M         = $AF0C02
+=$af0c03					SP00_ADDY_PTR_H         = $AF0C03
+=$af0c04					SP00_X_POS_L            = $AF0C04
+=$af0c05					SP00_X_POS_H            = $AF0C05
+=$af0c06					SP00_Y_POS_L            = $AF0C06
+=$af0c07					SP00_Y_POS_H            = $AF0C07
+=$af0c08					SP01_CONTROL_REG        = $AF0C08
+=$af0c09					SP01_ADDY_PTR_L         = $AF0C09
+=$af0c0a					SP01_ADDY_PTR_M         = $AF0C0A
+=$af0c0b					SP01_ADDY_PTR_H         = $AF0C0B
+=$af0c0c					SP01_X_POS_L            = $AF0C0C
+=$af0c0d					SP01_X_POS_H            = $AF0C0D
+=$af0c0e					SP01_Y_POS_L            = $AF0C0E
+=$af0c0f					SP01_Y_POS_H            = $AF0C0F
+=$af0c10					SP02_CONTROL_REG        = $AF0C10
+=$af0c11					SP02_ADDY_PTR_L         = $AF0C11
+=$af0c12					SP02_ADDY_PTR_M         = $AF0C12
+=$af0c13					SP02_ADDY_PTR_H         = $AF0C13
+=$af0c14					SP02_X_POS_L            = $AF0C14
+=$af0c15					SP02_X_POS_H            = $AF0C15
+=$af0c16					SP02_Y_POS_L            = $AF0C16
+=$af0c17					SP02_Y_POS_H            = $AF0C17
+=$af0c18					SP03_CONTROL_REG        = $AF0C18
+=$af0c19					SP03_ADDY_PTR_L         = $AF0C19
+=$af0c1a					SP03_ADDY_PTR_M         = $AF0C1A
+=$af0c1b					SP03_ADDY_PTR_H         = $AF0C1B
+=$af0c1c					SP03_X_POS_L            = $AF0C1C
+=$af0c1d					SP03_X_POS_H            = $AF0C1D
+=$af0c1e					SP03_Y_POS_L            = $AF0C1E
+=$af0c1f					SP03_Y_POS_H            = $AF0C1F
+=$af0c20					SP04_CONTROL_REG        = $AF0C20
+=$af0c21					SP04_ADDY_PTR_L         = $AF0C21
+=$af0c22					SP04_ADDY_PTR_M         = $AF0C22
+=$af0c23					SP04_ADDY_PTR_H         = $AF0C23
+=$af0c24					SP04_X_POS_L            = $AF0C24
+=$af0c25					SP04_X_POS_H            = $AF0C25
+=$af0c26					SP04_Y_POS_L            = $AF0C26
+=$af0c27					SP04_Y_POS_H            = $AF0C27
+=$af0c28					SP05_CONTROL_REG        = $AF0C28
+=$af0c29					SP05_ADDY_PTR_L         = $AF0C29
+=$af0c2a					SP05_ADDY_PTR_M         = $AF0C2A
+=$af0c2b					SP05_ADDY_PTR_H         = $AF0C2B
+=$af0c2c					SP05_X_POS_L            = $AF0C2C
+=$af0c2d					SP05_X_POS_H            = $AF0C2D
+=$af0c2e					SP05_Y_POS_L            = $AF0C2E
+=$af0c2f					SP05_Y_POS_H            = $AF0C2F
+=$af0c30					SP06_CONTROL_REG        = $AF0C30
+=$af0c31					SP06_ADDY_PTR_L         = $AF0C31
+=$af0c32					SP06_ADDY_PTR_M         = $AF0C32
+=$af0c33					SP06_ADDY_PTR_H         = $AF0C33
+=$af0c34					SP06_X_POS_L            = $AF0C34
+=$af0c35					SP06_X_POS_H            = $AF0C35
+=$af0c36					SP06_Y_POS_L            = $AF0C36
+=$af0c37					SP06_Y_POS_H            = $AF0C37
+=$af0c38					SP07_CONTROL_REG        = $AF0C38
+=$af0c39					SP07_ADDY_PTR_L         = $AF0C39
+=$af0c3a					SP07_ADDY_PTR_M         = $AF0C3A
+=$af0c3b					SP07_ADDY_PTR_H         = $AF0C3B
+=$af0c3c					SP07_X_POS_L            = $AF0C3C
+=$af0c3d					SP07_X_POS_H            = $AF0C3D
+=$af0c3e					SP07_Y_POS_L            = $AF0C3E
+=$af0c3f					SP07_Y_POS_H            = $AF0C3F
+=$af0c40					SP08_CONTROL_REG        = $AF0C40
+=$af0c41					SP08_ADDY_PTR_L         = $AF0C41
+=$af0c42					SP08_ADDY_PTR_M         = $AF0C42
+=$af0c43					SP08_ADDY_PTR_H         = $AF0C43
+=$af0c44					SP08_X_POS_L            = $AF0C44
+=$af0c45					SP08_X_POS_H            = $AF0C45
+=$af0c46					SP08_Y_POS_L            = $AF0C46
+=$af0c47					SP08_Y_POS_H            = $AF0C47
+=$af0c48					SP09_CONTROL_REG        = $AF0C48
+=$af0c49					SP09_ADDY_PTR_L         = $AF0C49
+=$af0c4a					SP09_ADDY_PTR_M         = $AF0C4A
+=$af0c4b					SP09_ADDY_PTR_H         = $AF0C4B
+=$af0c4c					SP09_X_POS_L            = $AF0C4C
+=$af0c4d					SP09_X_POS_H            = $AF0C4D
+=$af0c4e					SP09_Y_POS_L            = $AF0C4E
+=$af0c4f					SP09_Y_POS_H            = $AF0C4F
+=$af0c50					SP10_CONTROL_REG        = $AF0C50
+=$af0c51					SP10_ADDY_PTR_L         = $AF0C51
+=$af0c52					SP10_ADDY_PTR_M         = $AF0C52
+=$af0c53					SP10_ADDY_PTR_H         = $AF0C53
+=$af0c54					SP10_X_POS_L            = $AF0C54
+=$af0c55					SP10_X_POS_H            = $AF0C55
+=$af0c56					SP10_Y_POS_L            = $AF0C56
+=$af0c57					SP10_Y_POS_H            = $AF0C57
+=$af0c58					SP11_CONTROL_REG        = $AF0C58
+=$af0c59					SP11_ADDY_PTR_L         = $AF0C59
+=$af0c5a					SP11_ADDY_PTR_M         = $AF0C5A
+=$af0c5b					SP11_ADDY_PTR_H         = $AF0C5B
+=$af0c5c					SP11_X_POS_L            = $AF0C5C
+=$af0c5d					SP11_X_POS_H            = $AF0C5D
+=$af0c5e					SP11_Y_POS_L            = $AF0C5E
+=$af0c5f					SP11_Y_POS_H            = $AF0C5F
+=$af0c60					SP12_CONTROL_REG        = $AF0C60
+=$af0c61					SP12_ADDY_PTR_L         = $AF0C61
+=$af0c62					SP12_ADDY_PTR_M         = $AF0C62
+=$af0c63					SP12_ADDY_PTR_H         = $AF0C63
+=$af0c64					SP12_X_POS_L            = $AF0C64
+=$af0c65					SP12_X_POS_H            = $AF0C65
+=$af0c66					SP12_Y_POS_L            = $AF0C66
+=$af0c67					SP12_Y_POS_H            = $AF0C67
+=$af0c68					SP13_CONTROL_REG        = $AF0C68
+=$af0c69					SP13_ADDY_PTR_L         = $AF0C69
+=$af0c6a					SP13_ADDY_PTR_M         = $AF0C6A
+=$af0c6b					SP13_ADDY_PTR_H         = $AF0C6B
+=$af0c6c					SP13_X_POS_L            = $AF0C6C
+=$af0c6d					SP13_X_POS_H            = $AF0C6D
+=$af0c6e					SP13_Y_POS_L            = $AF0C6E
+=$af0c6f					SP13_Y_POS_H            = $AF0C6F
+=$af0c70					SP14_CONTROL_REG        = $AF0C70
+=$af0c71					SP14_ADDY_PTR_L         = $AF0C71
+=$af0c72					SP14_ADDY_PTR_M         = $AF0C72
+=$af0c73					SP14_ADDY_PTR_H         = $AF0C73
+=$af0c74					SP14_X_POS_L            = $AF0C74
+=$af0c75					SP14_X_POS_H            = $AF0C75
+=$af0c76					SP14_Y_POS_L            = $AF0C76
+=$af0c77					SP14_Y_POS_H            = $AF0C77
+=$af0c78					SP15_CONTROL_REG        = $AF0C78
+=$af0c79					SP15_ADDY_PTR_L         = $AF0C79
+=$af0c7a					SP15_ADDY_PTR_M         = $AF0C7A
+=$af0c7b					SP15_ADDY_PTR_H         = $AF0C7B
+=$af0c7c					SP15_X_POS_L            = $AF0C7C
+=$af0c7d					SP15_X_POS_H            = $AF0C7D
+=$af0c7e					SP15_Y_POS_L            = $AF0C7E
+=$af0c7f					SP15_Y_POS_H            = $AF0C7F
+=$af0c80					SP16_CONTROL_REG        = $AF0C80
+=$af0c81					SP16_ADDY_PTR_L         = $AF0C81
+=$af0c82					SP16_ADDY_PTR_M         = $AF0C82
+=$af0c83					SP16_ADDY_PTR_H         = $AF0C83
+=$af0c84					SP16_X_POS_L            = $AF0C84
+=$af0c85					SP16_X_POS_H            = $AF0C85
+=$af0c86					SP16_Y_POS_L            = $AF0C86
+=$af0c87					SP16_Y_POS_H            = $AF0C87
+=$af0c88					SP17_CONTROL_REG        = $AF0C88
+=$af0c89					SP17_ADDY_PTR_L         = $AF0C89
+=$af0c8a					SP17_ADDY_PTR_M         = $AF0C8A
+=$af0c8b					SP17_ADDY_PTR_H         = $AF0C8B
+=$af0c8c					SP17_X_POS_L            = $AF0C8C
+=$af0c8d					SP17_X_POS_H            = $AF0C8D
+=$af0c8e					SP17_Y_POS_L            = $AF0C8E
+=$af0c8f					SP17_Y_POS_H            = $AF0C8F
+=$af0c90					SP18_CONTROL_REG        = $AF0C90
+=$af0c91					SP18_ADDY_PTR_L         = $AF0C91
+=$af0c92					SP18_ADDY_PTR_M         = $AF0C92
+=$af0c93					SP18_ADDY_PTR_H         = $AF0C93
+=$af0c94					SP18_X_POS_L            = $AF0C94
+=$af0c95					SP18_X_POS_H            = $AF0C95
+=$af0c96					SP18_Y_POS_L            = $AF0C96
+=$af0c97					SP18_Y_POS_H            = $AF0C97
+=$af0c98					SP19_CONTROL_REG        = $AF0C98
+=$af0c99					SP19_ADDY_PTR_L         = $AF0C99
+=$af0c9a					SP19_ADDY_PTR_M         = $AF0C9A
+=$af0c9b					SP19_ADDY_PTR_H         = $AF0C9B
+=$af0c9c					SP19_X_POS_L            = $AF0C9C
+=$af0c9d					SP19_X_POS_H            = $AF0C9D
+=$af0c9e					SP19_Y_POS_L            = $AF0C9E
+=$af0c9f					SP19_Y_POS_H            = $AF0C9F
+=$af0ca0					SP20_CONTROL_REG        = $AF0CA0
+=$af0ca1					SP20_ADDY_PTR_L         = $AF0CA1
+=$af0ca2					SP20_ADDY_PTR_M         = $AF0CA2
+=$af0ca3					SP20_ADDY_PTR_H         = $AF0CA3
+=$af0ca4					SP20_X_POS_L            = $AF0CA4
+=$af0ca5					SP20_X_POS_H            = $AF0CA5
+=$af0ca6					SP20_Y_POS_L            = $AF0CA6
+=$af0ca7					SP20_Y_POS_H            = $AF0CA7
+=$af0ca8					SP21_CONTROL_REG        = $AF0CA8
+=$af0ca9					SP21_ADDY_PTR_L         = $AF0CA9
+=$af0caa					SP21_ADDY_PTR_M         = $AF0CAA
+=$af0cab					SP21_ADDY_PTR_H         = $AF0CAB
+=$af0cac					SP21_X_POS_L            = $AF0CAC
+=$af0cad					SP21_X_POS_H            = $AF0CAD
+=$af0cae					SP21_Y_POS_L            = $AF0CAE
+=$af0caf					SP21_Y_POS_H            = $AF0CAF
+=$af0cb0					SP22_CONTROL_REG        = $AF0CB0
+=$af0cb1					SP22_ADDY_PTR_L         = $AF0CB1
+=$af0cb2					SP22_ADDY_PTR_M         = $AF0CB2
+=$af0cb3					SP22_ADDY_PTR_H         = $AF0CB3
+=$af0cb4					SP22_X_POS_L            = $AF0CB4
+=$af0cb5					SP22_X_POS_H            = $AF0CB5
+=$af0cb6					SP22_Y_POS_L            = $AF0CB6
+=$af0cb7					SP22_Y_POS_H            = $AF0CB7
+=$af0cb8					SP23_CONTROL_REG        = $AF0CB8
+=$af0cb9					SP23_ADDY_PTR_L         = $AF0CB9
+=$af0cba					SP23_ADDY_PTR_M         = $AF0CBA
+=$af0cbb					SP23_ADDY_PTR_H         = $AF0CBB
+=$af0cbc					SP23_X_POS_L            = $AF0CBC
+=$af0cbd					SP23_X_POS_H            = $AF0CBD
+=$af0cbe					SP23_Y_POS_L            = $AF0CBE
+=$af0cbf					SP23_Y_POS_H            = $AF0CBF
+=$af0cc0					SP24_CONTROL_REG        = $AF0CC0
+=$af0cc1					SP24_ADDY_PTR_L         = $AF0CC1
+=$af0cc2					SP24_ADDY_PTR_M         = $AF0CC2
+=$af0cc3					SP24_ADDY_PTR_H         = $AF0CC3
+=$af0cc4					SP24_X_POS_L            = $AF0CC4
+=$af0cc5					SP24_X_POS_H            = $AF0CC5
+=$af0cc6					SP24_Y_POS_L            = $AF0CC6
+=$af0cc7					SP24_Y_POS_H            = $AF0CC7
+=$af0cc8					SP25_CONTROL_REG        = $AF0CC8
+=$af0cc9					SP25_ADDY_PTR_L         = $AF0CC9
+=$af0cca					SP25_ADDY_PTR_M         = $AF0CCA
+=$af0ccb					SP25_ADDY_PTR_H         = $AF0CCB
+=$af0ccc					SP25_X_POS_L            = $AF0CCC
+=$af0ccd					SP25_X_POS_H            = $AF0CCD
+=$af0cce					SP25_Y_POS_L            = $AF0CCE
+=$af0ccf					SP25_Y_POS_H            = $AF0CCF
+=$af0cd0					SP26_CONTROL_REG        = $AF0CD0
+=$af0cd1					SP26_ADDY_PTR_L         = $AF0CD1
+=$af0cd2					SP26_ADDY_PTR_M         = $AF0CD2
+=$af0cd3					SP26_ADDY_PTR_H         = $AF0CD3
+=$af0cd4					SP26_X_POS_L            = $AF0CD4
+=$af0cd5					SP26_X_POS_H            = $AF0CD5
+=$af0cd6					SP26_Y_POS_L            = $AF0CD6
+=$af0cd7					SP26_Y_POS_H            = $AF0CD7
+=$af0cd8					SP27_CONTROL_REG        = $AF0CD8
+=$af0cd9					SP27_ADDY_PTR_L         = $AF0CD9
+=$af0cda					SP27_ADDY_PTR_M         = $AF0CDA
+=$af0cdb					SP27_ADDY_PTR_H         = $AF0CDB
+=$af0cdc					SP27_X_POS_L            = $AF0CDC
+=$af0cdd					SP27_X_POS_H            = $AF0CDD
+=$af0cde					SP27_Y_POS_L            = $AF0CDE
+=$af0cdf					SP27_Y_POS_H            = $AF0CDF
+=$af0ce0					SP28_CONTROL_REG        = $AF0CE0
+=$af0ce1					SP28_ADDY_PTR_L         = $AF0CE1
+=$af0ce2					SP28_ADDY_PTR_M         = $AF0CE2
+=$af0ce3					SP28_ADDY_PTR_H         = $AF0CE3
+=$af0ce4					SP28_X_POS_L            = $AF0CE4
+=$af0ce5					SP28_X_POS_H            = $AF0CE5
+=$af0ce6					SP28_Y_POS_L            = $AF0CE6
+=$af0ce7					SP28_Y_POS_H            = $AF0CE7
+=$af0ce8					SP29_CONTROL_REG        = $AF0CE8
+=$af0ce9					SP29_ADDY_PTR_L         = $AF0CE9
+=$af0cea					SP29_ADDY_PTR_M         = $AF0CEA
+=$af0ceb					SP29_ADDY_PTR_H         = $AF0CEB
+=$af0cec					SP29_X_POS_L            = $AF0CEC
+=$af0ced					SP29_X_POS_H            = $AF0CED
+=$af0cee					SP29_Y_POS_L            = $AF0CEE
+=$af0cef					SP29_Y_POS_H            = $AF0CEF
+=$af0cf0					SP30_CONTROL_REG        = $AF0CF0
+=$af0cf1					SP30_ADDY_PTR_L         = $AF0CF1
+=$af0cf2					SP30_ADDY_PTR_M         = $AF0CF2
+=$af0cf3					SP30_ADDY_PTR_H         = $AF0CF3
+=$af0cf4					SP30_X_POS_L            = $AF0CF4
+=$af0cf5					SP30_X_POS_H            = $AF0CF5
+=$af0cf6					SP30_Y_POS_L            = $AF0CF6
+=$af0cf7					SP30_Y_POS_H            = $AF0CF7
+=$af0cf8					SP31_CONTROL_REG        = $AF0CF8
+=$af0cf9					SP31_ADDY_PTR_L         = $AF0CF9
+=$af0cfa					SP31_ADDY_PTR_M         = $AF0CFA
+=$af0cfb					SP31_ADDY_PTR_H         = $AF0CFB
+=$af0cfc					SP31_X_POS_L            = $AF0CFC
+=$af0cfd					SP31_X_POS_H            = $AF0CFD
+=$af0cfe					SP31_Y_POS_L            = $AF0CFE
+=$af0cff					SP31_Y_POS_H            = $AF0CFF
+=$af0d00					SP32_CONTROL_REG        = $AF0D00
+=$af0d01					SP32_ADDY_PTR_L         = $AF0D01
+=$af0d02					SP32_ADDY_PTR_M         = $AF0D02
+=$af0d03					SP32_ADDY_PTR_H         = $AF0D03
+=$af0d04					SP32_X_POS_L            = $AF0D04
+=$af0d05					SP32_X_POS_H            = $AF0D05
+=$af0d06					SP32_Y_POS_L            = $AF0D06
+=$af0d07					SP32_Y_POS_H            = $AF0D07
+=$af0d08					SP33_CONTROL_REG        = $AF0D08
+=$af0d09					SP33_ADDY_PTR_L         = $AF0D09
+=$af0d0a					SP33_ADDY_PTR_M         = $AF0D0A
+=$af0d0b					SP33_ADDY_PTR_H         = $AF0D0B
+=$af0d0c					SP33_X_POS_L            = $AF0D0C
+=$af0d0d					SP33_X_POS_H            = $AF0D0D
+=$af0d0e					SP33_Y_POS_L            = $AF0D0E
+=$af0d0f					SP33_Y_POS_H            = $AF0D0F
+=$af0d10					SP34_CONTROL_REG        = $AF0D10
+=$af0d11					SP34_ADDY_PTR_L         = $AF0D11
+=$af0d12					SP34_ADDY_PTR_M         = $AF0D12
+=$af0d13					SP34_ADDY_PTR_H         = $AF0D13
+=$af0d14					SP34_X_POS_L            = $AF0D14
+=$af0d15					SP34_X_POS_H            = $AF0D15
+=$af0d16					SP34_Y_POS_L            = $AF0D16
+=$af0d17					SP34_Y_POS_H            = $AF0D17
+=$af0d18					SP35_CONTROL_REG        = $AF0D18
+=$af0d19					SP35_ADDY_PTR_L         = $AF0D19
+=$af0d1a					SP35_ADDY_PTR_M         = $AF0D1A
+=$af0d1b					SP35_ADDY_PTR_H         = $AF0D1B
+=$af0d1c					SP35_X_POS_L            = $AF0D1C
+=$af0d1d					SP35_X_POS_H            = $AF0D1D
+=$af0d1e					SP35_Y_POS_L            = $AF0D1E
+=$af0d1f					SP35_Y_POS_H            = $AF0D1F
+=$af0d20					SP36_CONTROL_REG        = $AF0D20
+=$af0d21					SP36_ADDY_PTR_L         = $AF0D21
+=$af0d22					SP36_ADDY_PTR_M         = $AF0D22
+=$af0d23					SP36_ADDY_PTR_H         = $AF0D23
+=$af0d24					SP36_X_POS_L            = $AF0D24
+=$af0d25					SP36_X_POS_H            = $AF0D25
+=$af0d26					SP36_Y_POS_L            = $AF0D26
+=$af0d27					SP36_Y_POS_H            = $AF0D27
+=$af0d28					SP37_CONTROL_REG        = $AF0D28
+=$af0d29					SP37_ADDY_PTR_L         = $AF0D29
+=$af0d2a					SP37_ADDY_PTR_M         = $AF0D2A
+=$af0d2b					SP37_ADDY_PTR_H         = $AF0D2B
+=$af0d2c					SP37_X_POS_L            = $AF0D2C
+=$af0d2d					SP37_X_POS_H            = $AF0D2D
+=$af0d2e					SP37_Y_POS_L            = $AF0D2E
+=$af0d2f					SP37_Y_POS_H            = $AF0D2F
+=$af0d30					SP38_CONTROL_REG        = $AF0D30
+=$af0d31					SP38_ADDY_PTR_L         = $AF0D31
+=$af0d32					SP38_ADDY_PTR_M         = $AF0D32
+=$af0d33					SP38_ADDY_PTR_H         = $AF0D33
+=$af0d34					SP38_X_POS_L            = $AF0D34
+=$af0d35					SP38_X_POS_H            = $AF0D35
+=$af0d36					SP38_Y_POS_L            = $AF0D36
+=$af0d37					SP38_Y_POS_H            = $AF0D37
+=$af0d38					SP39_CONTROL_REG        = $AF0D38
+=$af0d39					SP39_ADDY_PTR_L         = $AF0D39
+=$af0d3a					SP39_ADDY_PTR_M         = $AF0D3A
+=$af0d3b					SP39_ADDY_PTR_H         = $AF0D3B
+=$af0d3c					SP39_X_POS_L            = $AF0D3C
+=$af0d3d					SP39_X_POS_H            = $AF0D3D
+=$af0d3e					SP39_Y_POS_L            = $AF0D3E
+=$af0d3f					SP39_Y_POS_H            = $AF0D3F
+=$af0d40					SP40_CONTROL_REG        = $AF0D40
+=$af0d41					SP40_ADDY_PTR_L         = $AF0D41
+=$af0d42					SP40_ADDY_PTR_M         = $AF0D42
+=$af0d43					SP40_ADDY_PTR_H         = $AF0D43
+=$af0d44					SP40_X_POS_L            = $AF0D44
+=$af0d45					SP40_X_POS_H            = $AF0D45
+=$af0d46					SP40_Y_POS_L            = $AF0D46
+=$af0d47					SP40_Y_POS_H            = $AF0D47
+=$af0d48					SP41_CONTROL_REG        = $AF0D48
+=$af0d49					SP41_ADDY_PTR_L         = $AF0D49
+=$af0d4a					SP41_ADDY_PTR_M         = $AF0D4A
+=$af0d4b					SP41_ADDY_PTR_H         = $AF0D4B
+=$af0d4c					SP41_X_POS_L            = $AF0D4C
+=$af0d4d					SP41_X_POS_H            = $AF0D4D
+=$af0d4e					SP41_Y_POS_L            = $AF0D4E
+=$af0d4f					SP41_Y_POS_H            = $AF0D4F
+=$af0d50					SP42_CONTROL_REG        = $AF0D50
+=$af0d51					SP42_ADDY_PTR_L         = $AF0D51
+=$af0d52					SP42_ADDY_PTR_M         = $AF0D52
+=$af0d53					SP42_ADDY_PTR_H         = $AF0D53
+=$af0d54					SP42_X_POS_L            = $AF0D54
+=$af0d55					SP42_X_POS_H            = $AF0D55
+=$af0d56					SP42_Y_POS_L            = $AF0D56
+=$af0d57					SP42_Y_POS_H            = $AF0D57
+=$af0d58					SP43_CONTROL_REG        = $AF0D58
+=$af0d59					SP43_ADDY_PTR_L         = $AF0D59
+=$af0d5a					SP43_ADDY_PTR_M         = $AF0D5A
+=$af0d5b					SP43_ADDY_PTR_H         = $AF0D5B
+=$af0d5c					SP43_X_POS_L            = $AF0D5C
+=$af0d5d					SP43_X_POS_H            = $AF0D5D
+=$af0d5e					SP43_Y_POS_L            = $AF0D5E
+=$af0d5f					SP43_Y_POS_H            = $AF0D5F
+=$af0d60					SP44_CONTROL_REG        = $AF0D60
+=$af0d61					SP44_ADDY_PTR_L         = $AF0D61
+=$af0d62					SP44_ADDY_PTR_M         = $AF0D62
+=$af0d63					SP44_ADDY_PTR_H         = $AF0D63
+=$af0d64					SP44_X_POS_L            = $AF0D64
+=$af0d65					SP44_X_POS_H            = $AF0D65
+=$af0d66					SP44_Y_POS_L            = $AF0D66
+=$af0d67					SP44_Y_POS_H            = $AF0D67
+=$af0d68					SP45_CONTROL_REG        = $AF0D68
+=$af0d69					SP45_ADDY_PTR_L         = $AF0D69
+=$af0d6a					SP45_ADDY_PTR_M         = $AF0D6A
+=$af0d6b					SP45_ADDY_PTR_H         = $AF0D6B
+=$af0d6c					SP45_X_POS_L            = $AF0D6C
+=$af0d6d					SP45_X_POS_H            = $AF0D6D
+=$af0d6e					SP45_Y_POS_L            = $AF0D6E
+=$af0d6f					SP45_Y_POS_H            = $AF0D6F
+=$af0d70					SP46_CONTROL_REG        = $AF0D70
+=$af0d71					SP46_ADDY_PTR_L         = $AF0D71
+=$af0d72					SP46_ADDY_PTR_M         = $AF0D72
+=$af0d73					SP46_ADDY_PTR_H         = $AF0D73
+=$af0d74					SP46_X_POS_L            = $AF0D74
+=$af0d75					SP46_X_POS_H            = $AF0D75
+=$af0d76					SP46_Y_POS_L            = $AF0D76
+=$af0d77					SP46_Y_POS_H            = $AF0D77
+=$af0d78					SP47_CONTROL_REG        = $AF0D78
+=$af0d79					SP47_ADDY_PTR_L         = $AF0D79
+=$af0d7a					SP47_ADDY_PTR_M         = $AF0D7A
+=$af0d7b					SP47_ADDY_PTR_H         = $AF0D7B
+=$af0d7c					SP47_X_POS_L            = $AF0D7C
+=$af0d7d					SP47_X_POS_H            = $AF0D7D
+=$af0d7e					SP47_Y_POS_L            = $AF0D7E
+=$af0d7f					SP47_Y_POS_H            = $AF0D7F
+=$af0d80					SP48_CONTROL_REG        = $AF0D80
+=$af0d81					SP48_ADDY_PTR_L         = $AF0D81
+=$af0d82					SP48_ADDY_PTR_M         = $AF0D82
+=$af0d83					SP48_ADDY_PTR_H         = $AF0D83
+=$af0d84					SP48_X_POS_L            = $AF0D84
+=$af0d85					SP48_X_POS_H            = $AF0D85
+=$af0d86					SP48_Y_POS_L            = $AF0D86
+=$af0d87					SP48_Y_POS_H            = $AF0D87
+=$af0d88					SP49_CONTROL_REG        = $AF0D88
+=$af0d89					SP49_ADDY_PTR_L         = $AF0D89
+=$af0d8a					SP49_ADDY_PTR_M         = $AF0D8A
+=$af0d8b					SP49_ADDY_PTR_H         = $AF0D8B
+=$af0d8c					SP49_X_POS_L            = $AF0D8C
+=$af0d8d					SP49_X_POS_H            = $AF0D8D
+=$af0d8e					SP49_Y_POS_L            = $AF0D8E
+=$af0d8f					SP49_Y_POS_H            = $AF0D8F
+=$af0d90					SP50_CONTROL_REG        = $AF0D90
+=$af0d91					SP50_ADDY_PTR_L         = $AF0D91
+=$af0d92					SP50_ADDY_PTR_M         = $AF0D92
+=$af0d93					SP50_ADDY_PTR_H         = $AF0D93
+=$af0d94					SP50_X_POS_L            = $AF0D94
+=$af0d95					SP50_X_POS_H            = $AF0D95
+=$af0d96					SP50_Y_POS_L            = $AF0D96
+=$af0d97					SP50_Y_POS_H            = $AF0D97
+=$af0d98					SP51_CONTROL_REG        = $AF0D98
+=$af0d99					SP51_ADDY_PTR_L         = $AF0D99
+=$af0d9a					SP51_ADDY_PTR_M         = $AF0D9A
+=$af0d9b					SP51_ADDY_PTR_H         = $AF0D9B
+=$af0d9c					SP51_X_POS_L            = $AF0D9C
+=$af0d9d					SP51_X_POS_H            = $AF0D9D
+=$af0d9e					SP51_Y_POS_L            = $AF0D9E
+=$af0d9f					SP51_Y_POS_H            = $AF0D9F
+=$af0da0					SP52_CONTROL_REG        = $AF0DA0
+=$af0da1					SP52_ADDY_PTR_L         = $AF0DA1
+=$af0da2					SP52_ADDY_PTR_M         = $AF0DA2
+=$af0da3					SP52_ADDY_PTR_H         = $AF0DA3
+=$af0da4					SP52_X_POS_L            = $AF0DA4
+=$af0da5					SP52_X_POS_H            = $AF0DA5
+=$af0da6					SP52_Y_POS_L            = $AF0DA6
+=$af0da7					SP52_Y_POS_H            = $AF0DA7
+=$af0da8					SP53_CONTROL_REG        = $AF0DA8
+=$af0da9					SP53_ADDY_PTR_L         = $AF0DA9
+=$af0daa					SP53_ADDY_PTR_M         = $AF0DAA
+=$af0dab					SP53_ADDY_PTR_H         = $AF0DAB
+=$af0dac					SP53_X_POS_L            = $AF0DAC
+=$af0dad					SP53_X_POS_H            = $AF0DAD
+=$af0dae					SP53_Y_POS_L            = $AF0DAE
+=$af0daf					SP53_Y_POS_H            = $AF0DAF
+=$af0db0					SP54_CONTROL_REG        = $AF0DB0
+=$af0db1					SP54_ADDY_PTR_L         = $AF0DB1
+=$af0db2					SP54_ADDY_PTR_M         = $AF0DB2
+=$af0db3					SP54_ADDY_PTR_H         = $AF0DB3
+=$af0db4					SP54_X_POS_L            = $AF0DB4
+=$af0db5					SP54_X_POS_H            = $AF0DB5
+=$af0db6					SP54_Y_POS_L            = $AF0DB6
+=$af0db7					SP54_Y_POS_H            = $AF0DB7
+=$af0db8					SP55_CONTROL_REG        = $AF0DB8
+=$af0db9					SP55_ADDY_PTR_L         = $AF0DB9
+=$af0dba					SP55_ADDY_PTR_M         = $AF0DBA
+=$af0dbb					SP55_ADDY_PTR_H         = $AF0DBB
+=$af0dbc					SP55_X_POS_L            = $AF0DBC
+=$af0dbd					SP55_X_POS_H            = $AF0DBD
+=$af0dbe					SP55_Y_POS_L            = $AF0DBE
+=$af0dbf					SP55_Y_POS_H            = $AF0DBF
+=$af0dc0					SP56_CONTROL_REG        = $AF0DC0
+=$af0dc1					SP56_ADDY_PTR_L         = $AF0DC1
+=$af0dc2					SP56_ADDY_PTR_M         = $AF0DC2
+=$af0dc3					SP56_ADDY_PTR_H         = $AF0DC3
+=$af0dc4					SP56_X_POS_L            = $AF0DC4
+=$af0dc5					SP56_X_POS_H            = $AF0DC5
+=$af0dc6					SP56_Y_POS_L            = $AF0DC6
+=$af0dc7					SP56_Y_POS_H            = $AF0DC7
+=$af0dc8					SP57_CONTROL_REG        = $AF0DC8
+=$af0dc9					SP57_ADDY_PTR_L         = $AF0DC9
+=$af0dca					SP57_ADDY_PTR_M         = $AF0DCA
+=$af0dcb					SP57_ADDY_PTR_H         = $AF0DCB
+=$af0dcc					SP57_X_POS_L            = $AF0DCC
+=$af0dcd					SP57_X_POS_H            = $AF0DCD
+=$af0dce					SP57_Y_POS_L            = $AF0DCE
+=$af0dcf					SP57_Y_POS_H            = $AF0DCF
+=$af0dd0					SP58_CONTROL_REG        = $AF0DD0
+=$af0dd1					SP58_ADDY_PTR_L         = $AF0DD1
+=$af0dd2					SP58_ADDY_PTR_M         = $AF0DD2
+=$af0dd3					SP58_ADDY_PTR_H         = $AF0DD3
+=$af0dd4					SP58_X_POS_L            = $AF0DD4
+=$af0dd5					SP58_X_POS_H            = $AF0DD5
+=$af0dd6					SP58_Y_POS_L            = $AF0DD6
+=$af0dd7					SP58_Y_POS_H            = $AF0DD7
+=$af0dd8					SP59_CONTROL_REG        = $AF0DD8
+=$af0dd9					SP59_ADDY_PTR_L         = $AF0DD9
+=$af0dda					SP59_ADDY_PTR_M         = $AF0DDA
+=$af0ddb					SP59_ADDY_PTR_H         = $AF0DDB
+=$af0ddc					SP59_X_POS_L            = $AF0DDC
+=$af0ddd					SP59_X_POS_H            = $AF0DDD
+=$af0dde					SP59_Y_POS_L            = $AF0DDE
+=$af0ddf					SP59_Y_POS_H            = $AF0DDF
+=$af0de0					SP60_CONTROL_REG        = $AF0DE0
+=$af0de1					SP60_ADDY_PTR_L         = $AF0DE1
+=$af0de2					SP60_ADDY_PTR_M         = $AF0DE2
+=$af0de3					SP60_ADDY_PTR_H         = $AF0DE3
+=$af0de4					SP60_X_POS_L            = $AF0DE4
+=$af0de5					SP60_X_POS_H            = $AF0DE5
+=$af0de6					SP60_Y_POS_L            = $AF0DE6
+=$af0de7					SP60_Y_POS_H            = $AF0DE7
+=$af0de8					SP61_CONTROL_REG        = $AF0DE8
+=$af0de9					SP61_ADDY_PTR_L         = $AF0DE9
+=$af0dea					SP61_ADDY_PTR_M         = $AF0DEA
+=$af0deb					SP61_ADDY_PTR_H         = $AF0DEB
+=$af0dec					SP61_X_POS_L            = $AF0DEC
+=$af0ded					SP61_X_POS_H            = $AF0DED
+=$af0dee					SP61_Y_POS_L            = $AF0DEE
+=$af0def					SP61_Y_POS_H            = $AF0DEF
+=$af0df0					SP62_CONTROL_REG        = $AF0DF0
+=$af0df1					SP62_ADDY_PTR_L         = $AF0DF1
+=$af0df2					SP62_ADDY_PTR_M         = $AF0DF2
+=$af0df3					SP62_ADDY_PTR_H         = $AF0DF3
+=$af0df4					SP62_X_POS_L            = $AF0DF4
+=$af0df5					SP62_X_POS_H            = $AF0DF5
+=$af0df6					SP62_Y_POS_L            = $AF0DF6
+=$af0df7					SP62_Y_POS_H            = $AF0DF7
+=$af0df8					SP63_CONTROL_REG        = $AF0DF8
+=$af0df9					SP63_ADDY_PTR_L         = $AF0DF9
+=$af0dfa					SP63_ADDY_PTR_M         = $AF0DFA
+=$af0dfb					SP63_ADDY_PTR_H         = $AF0DFB
+=$af0dfc					SP63_X_POS_L            = $AF0DFC
+=$af0dfd					SP63_X_POS_H            = $AF0DFD
+=$af0dfe					SP63_Y_POS_L            = $AF0DFE
+=$af0dff					SP63_Y_POS_H            = $AF0DFF
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/VKYII_CFP9553_COLLISION_def.asm
+
+=$0001						COL_STAT_SP0 = $0001
+=$0002						COL_STAT_SP1 = $0002
+=$0004						COL_STAT_SP2 = $0004
+=$0008						COL_STAT_SP3 = $0008
+=$0010						COL_STAT_SP4 = $0010
+=$0020						COL_STAT_SP5 = $0020
+=$0040						COL_STAT_SP6 = $0040
+=$0080						COL_STAT_BM0 = $0080
+=$0100						COL_STAT_BM1 = $0100
+=$0200						COL_STAT_COL = $0200
+=$0400						COL_STAT_TL0 = $0400
+=$0800						COL_STAT_TL1 = $0800
+=$1000						COL_STAT_TL2 = $1000
+=$2000						COL_STAT_TL3 = $2000
+=$4000						COL_RESERVE0 = $4000    ; Reserved
+=$8000						COL_RESERVE1 = $8000    ; Reserved
+=$af0300					COLLISION_SPRITE_L0_L   = $AF0300
+=$af0301					COLLISION_SPRITE_L0_H   = $AF0301
+=$af0302					COLLISION_SPRITE_L1_L   = $AF0302
+=$af0303					COLLISION_SPRITE_L1_H   = $AF0303
+=$af0304					COLLISION_SPRITE_L2_L   = $AF0304
+=$af0305					COLLISION_SPRITE_L2_H   = $AF0305
+=$af0306					COLLISION_SPRITE_L3_L   = $AF0306
+=$af0307					COLLISION_SPRITE_L3_H   = $AF0307
+=$af0308					COLLISION_SPRITE_L4_L   = $AF0308
+=$af0309					COLLISION_SPRITE_L4_H   = $AF0309
+=$af030a					COLLISION_SPRITE_L5_L   = $AF030A
+=$af030b					COLLISION_SPRITE_L5_H   = $AF030B
+=$af030c					COLLISION_SPRITE_L6_L   = $AF030C
+=$af030d					COLLISION_SPRITE_L6_H   = $AF030D
+=$af030e					COLLISION_BITMAP_L0_L   = $AF030E
+=$af030f					COLLISION_BITMAP_L0_H   = $AF030F
+=$af0310					COLLISION_BITMAP_L1_L   = $AF0310
+=$af0311					COLLISION_BITMAP_L1_H   = $AF0311
+=$af0312					COLLISION_COLMAP_L0_L   = $AF0312 ; Collision Bitmap - Not Implemented yet
+=$af0313					COLLISION_COLMAP_L0_H   = $AF0313
+=$af0314					COLLISION_TILEMAP_L0_L  = $AF0314
+=$af0315					COLLISION_TILEMAP_L0_H  = $AF0315
+=$af0316					COLLISION_TILEMAP_L1_L  = $AF0316
+=$af0317					COLLISION_TILEMAP_L1_H  = $AF0317
+=$af0318					COLLISION_TILEMAP_L2_L  = $AF0318
+=$af0319					COLLISION_TILEMAP_L2_H  = $AF0319
+=$af031a					COLLISION_TILEMAP_L3_L  = $AF031A
+=$af031b					COLLISION_TILEMAP_L3_H  = $AF031B
+=$af031c					COLLISION_PXL_VALUE_SP  = $AF031C
+=$af031d					COLLISION_SPRITE_NUMBER = $AF031D
+=$af031e					COLLISION_PXL_VALUE_BM0 = $AF031E
+=$af031f					COLLISION_PXL_VALUE_BM1 = $AF031F
+=$af0320					COLLISION_PXL_VALUE_COL = $AF0320
+=$af0321					COLLISION_PXL_VALUE_TL0 = $AF0321
+=$af0322					COLLISION_PXL_VALUE_TL1 = $AF0322
+=$af0323					COLLISION_PXL_VALUE_TL2 = $AF0323
+=$af0324					COLLISION_PXL_VALUE_TL3 = $AF0324
+=$af0326					COLLISION_SPRITE_COORD_X_LO = $AF0326
+=$af0327					COLLISION_SPRITE_COORD_X_HI = $AF0327
+=$af0328					COLLISION_BITMAP_COORD_X_LO = $AF0328
+=$af0329					COLLISION_BITMAP_COORD_X_HI = $AF0329
+=$af032a					COLLISION_TILES_COORD_X_LO  = $AF032A
+=$af032b					COLLISION_TILES_COORD_X_HI  = $AF032B
+=$af032c					COLLISION_COORD_Y_LO        = $AF032C
+=$af032d					COLLISION_COORD_Y_HI        = $AF032D
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/EXP_C100_ESID_def.asm
+
+=$ae0000					ESID_EXP_CARD_INFO      = $AE0000    ; Read Only (32 Bytes Card ID - READ ONLY)
+=$ae0000					ESID_ID_NAME_ASCII      = $AE0000    ; 15 Characters + $00
+=$ae0010					ESID_ID_VENDOR_ID_Lo    = $AE0010    ; Foenix Project Reserved ID: $F0E1
+=$ae0011					ESID_ID_VENDOR_ID_Hi    = $AE0011
+=$ae0012					ESID_ID_CARD_ID_Lo      = $AE0012    ; $9172 - C100-ESID
+=$ae0013					ESID_ID_CARD_ID_Hi      = $AE0013
+=$ae0014					ESID_ID_CARD_CLASS_Lo   = $AE0014    ; TBD
+=$ae0015					ESID_ID_CARD_CLASS_Hi   = $AE0015    ; TBD
+=$ae0016					ESID_ID_CARD_SUBCLSS_Lo = $AE0016    ; TBD
+=$ae0017					ESID_ID_CARD_SUBCLSS_Hi = $AE0017    ; TBD
+=$ae0018					ESID_ID_CARD_UNDEFINED0 = $AE0018    ; TBD
+=$ae0019					ESID_ID_CARD_UNDEFINED1 = $AE0019    ; TBD
+=$ae001a					ESID_ID_CARD_HW_Rev     = $AE001A    ; 00 - in Hex
+=$ae001b					ESID_ID_CARD_FPGA_Rev   = $AE001B    ; 00 - in Hex
+=$ae001c					ESID_ID_CARD_UNDEFINED2 = $AE001C    ; TBD
+=$ae001d					ESID_ID_CARD_UNDEFINED3 = $AE001D    ; TBD
+=$ae001e					ESID_ID_CARD_CHKSUM0    = $AE001E    ; Not Supported Yet
+=$ae001f					ESID_ID_CARD_CHKSUM1    = $AE001F    ; Not Supported Yet
+=$aed000					ESID_SIDL_V1_FREQ_LO    = $AED000 ;SID - L - Voice 1 (Write Only) - FREQ LOW
+=$aed001					ESID_SIDL_V1_FREQ_HI    = $AED001 ;SID - L - Voice 1 (Write Only) - FREQ HI
+=$aed002					ESID_SIDL_V1_PW_LO      = $AED002 ;SID - L - Voice 1 (Write Only) - PW LOW
+=$aed003					ESID_SIDL_V1_PW_HI      = $AED003 ;SID - L - Voice 1 (Write Only) - PW HI
+=$aed004					ESID_SIDL_V1_CTRL       = $AED004 ;SID - L - Voice 1 (Write Only) - CTRL REG
+=$aed005					ESID_SIDL_V1_ATCK_DECY  = $AED005 ;SID - L - Voice 1 (Write Only) - ATTACK / DECAY
+=$aed006					ESID_SIDL_V1_SSTN_RLSE  = $AED006 ;SID - L - Voice 1 (Write Only) - SUSTAIN / RELEASE
+=$aed007					ESID_SIDL_V2_FREQ_LO    = $AED007 ;SID - L - Voice 2 (Write Only) - FREQ LOW
+=$aed008					ESID_SIDL_V2_FREQ_HI    = $AED008 ;SID - L - Voice 2 (Write Only) - FREQ HI
+=$aed009					ESID_SIDL_V2_PW_LO      = $AED009 ;SID - L - Voice 2 (Write Only) - PW LOW
+=$aed00a					ESID_SIDL_V2_PW_HI      = $AED00A ;SID - L - Voice 2 (Write Only) - PW HI
+=$aed00b					ESID_SIDL_V2_CTRL       = $AED00B ;SID - L - Voice 2 (Write Only) - CTRL REG
+=$aed00c					ESID_SIDL_V2_ATCK_DECY  = $AED00C ;SID - L - Voice 2 (Write Only) - ATTACK / DECAY
+=$aed00d					ESID_SIDL_V2_SSTN_RLSE  = $AED00D ;SID - L - Voice 2 (Write Only) - SUSTAIN / RELEASE
+=$aed00e					ESID_SIDL_V3_FREQ_LO    = $AED00E ;SID - L - Voice 3 (Write Only) - FREQ LOW
+=$aed00f					ESID_SIDL_V3_FREQ_HI    = $AED00F ;SID - L - Voice 3 (Write Only) - FREQ HI
+=$aed010					ESID_SIDL_V3_PW_LO      = $AED010 ;SID - L - Voice 3 (Write Only) - PW LOW
+=$aed011					ESID_SIDL_V3_PW_HI      = $AED011 ;SID - L - Voice 3 (Write Only) - PW HI
+=$aed012					ESID_SIDL_V3_CTRL       = $AED012 ;SID - L - Voice 3 (Write Only) - CTRL REG
+=$aed013					ESID_SIDL_V3_ATCK_DECY  = $AED013 ;SID - L - Voice 3 (Write Only) - ATTACK / DECAY
+=$aed014					ESID_SIDL_V3_SSTN_RLSE  = $AED014 ;SID - L - Voice 3 (Write Only) - SUSTAIN / RELEASE
+=$aed015					ESID_SIDL_FC_LO         = $AED015 ;SID - L - Filter (Write Only) - FC LOW
+=$aed016					ESID_SIDL_FC_HI         = $AED016 ;SID - L - Filter (Write Only) - FC HI
+=$aed017					ESID_SIDL_RES_FILT      = $AED017 ;SID - L - Filter (Write Only) - RES / FILT
+=$aed018					ESID_SIDL_MODE_VOL      = $AED018 ;SID - L - Filter (Write Only) - MODE / VOL
+=$aed019					ESID_SIDL_POT_X         = $AED019 ;SID - L - Misc (Read Only) - POT X (C256 - NOT USED)
+=$aed01a					ESID_SIDL_POT_Y         = $AED01A ;SID - L - Misc (Read Only) - POT Y (C256 - NOT USED)
+=$aed01b					ESID_SIDL_OSC3_RND      = $AED01B ;SID - L - Misc (Read Only) - OSC3 / RANDOM
+=$aed01c					ESID_SIDL_ENV3          = $AED01C ;SID - L - Misc (Read Only)  - ENV3
+=$aed01d					ESID_SIDL_NOT_USED0     = $AED01D ;SID - L - NOT USED
+=$aed01e					ESID_SIDL_NOT_USED1     = $AED01E ;SID - L - NOT USED
+=$aed01f					ESID_SIDL_NOT_USED2     = $AED01F ;SID - L - NOT USED
+=$aed100					ESID_SIDR_V1_FREQ_LO    = $AED100 ;SID - L - Voice 1 (Write Only) - FREQ LOW
+=$aed101					ESID_SIDR_V1_FREQ_HI    = $AED101 ;SID - L - Voice 1 (Write Only) - FREQ HI
+=$aed102					ESID_SIDR_V1_PW_LO      = $AED102 ;SID - L - Voice 1 (Write Only) - PW LOW
+=$aed103					ESID_SIDR_V1_PW_HI      = $AED103 ;SID - L - Voice 1 (Write Only) - PW HI
+=$aed104					ESID_SIDR_V1_CTRL       = $AED104 ;SID - L - Voice 1 (Write Only) - CTRL REG
+=$aed105					ESID_SIDR_V1_ATCK_DECY  = $AED105 ;SID - L - Voice 1 (Write Only) - ATTACK / DECAY
+=$aed106					ESID_SIDR_V1_SSTN_RLSE  = $AED106 ;SID - L - Voice 1 (Write Only) - SUSTAIN / RELEASE
+=$aed107					ESID_SIDR_V2_FREQ_LO    = $AED107 ;SID - L - Voice 2 (Write Only) - FREQ LOW
+=$aed108					ESID_SIDR_V2_FREQ_HI    = $AED108 ;SID - L - Voice 2 (Write Only) - FREQ HI
+=$aed109					ESID_SIDR_V2_PW_LO      = $AED109 ;SID - L - Voice 2 (Write Only) - PW LOW
+=$aed10a					ESID_SIDR_V2_PW_HI      = $AED10A ;SID - L - Voice 2 (Write Only) - PW HI
+=$aed10b					ESID_SIDR_V2_CTRL       = $AED10B ;SID - L - Voice 2 (Write Only) - CTRL REG
+=$aed10c					ESID_SIDR_V2_ATCK_DECY  = $AED10C ;SID - L - Voice 2 (Write Only) - ATTACK / DECAY
+=$aed10d					ESID_SIDR_V2_SSTN_RLSE  = $AED10D ;SID - L - Voice 2 (Write Only) - SUSTAIN / RELEASE
+=$aed10e					ESID_SIDR_V3_FREQ_LO    = $AED10E ;SID - L - Voice 3 (Write Only) - FREQ LOW
+=$aed10f					ESID_SIDR_V3_FREQ_HI    = $AED10F ;SID - L - Voice 3 (Write Only) - FREQ HI
+=$aed110					ESID_SIDR_V3_PW_LO      = $AED110 ;SID - L - Voice 3 (Write Only) - PW LOW
+=$aed111					ESID_SIDR_V3_PW_HI      = $AED111 ;SID - L - Voice 3 (Write Only) - PW HI
+=$aed112					ESID_SIDR_V3_CTRL       = $AED112 ;SID - L - Voice 3 (Write Only) - CTRL REG
+=$aed113					ESID_SIDR_V3_ATCK_DECY  = $AED113 ;SID - L - Voice 3 (Write Only) - ATTACK / DECAY
+=$aed114					ESID_SIDR_V3_SSTN_RLSE  = $AED114 ;SID - L - Voice 3 (Write Only) - SUSTAIN / RELEASE
+=$aed115					ESID_SIDR_FC_LO         = $AED115 ;SID - L - Filter (Write Only) - FC LOW
+=$aed116					ESID_SIDR_FC_HI         = $AED116 ;SID - L - Filter (Write Only) - FC HI
+=$aed117					ESID_SIDR_RES_FILT      = $AED117 ;SID - L - Filter (Write Only) - RES / FILT
+=$aed118					ESID_SIDR_MODE_VOL      = $AED118 ;SID - L - Filter (Write Only) - MODE / VOL
+=$aed119					ESID_SIDR_POT_X         = $AED119 ;SID - L - Misc (Read Only) - POT X (C256 - NOT USED)
+=$aed11a					ESID_SIDR_POT_Y         = $AED11A ;SID - L - Misc (Read Only) - POT Y (C256 - NOT USED)
+=$aed11b					ESID_SIDR_OSC3_RND      = $AED11B ;SID - L - Misc (Read Only) - OSC3 / RANDOM
+=$aed11c					ESID_SIDR_ENV3          = $AED11C ;SID - L - Misc (Read Only)  - ENV3
+=$aed11d					ESID_SIDR_NOT_USED0     = $AED11D ;SID - L - NOT USED
+=$aed11e					ESID_SIDR_NOT_USED1     = $AED11E ;SID - L - NOT USED
+=$aed11f					ESID_SIDR_NOT_USED2     = $AED11F ;SID - L - NOT USED
+=$aee000					ESID_ETHERNET_REG       = $AEE000
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/EXP_C200_EVID_def.asm
+
+=$ae0000					EVID_EXP_CARD_INFO      = $AE0000    ; Read Only (32 Bytes Card ID - READ ONLY)
+=$ae0000					EVID_ID_NAME_ASCII      = $AE0000    ; 15 Characters + $00
+=$ae0010					EVID_ID_VENDOR_ID_Lo    = $AE0010    ; Foenix Project Reserved ID: $F0E1
+=$ae0011					EVID_ID_VENDOR_ID_Hi    = $AE0011
+=$ae0012					EVID_ID_CARD_ID_Lo      = $AE0012      ; $9236 - C200-EVID
+=$ae0013					EVID_ID_CARD_ID_Hi      = $AE0013
+=$ae0014					EVID_ID_CARD_CLASS_Lo   = $AE0014    ; TBD
+=$ae0015					EVID_ID_CARD_CLASS_Hi   = $AE0015    ; TBD
+=$ae0016					EVID_ID_CARD_SUBCLSS_Lo = $AE0016    ; TBD
+=$ae0017					EVID_ID_CARD_SUBCLSS_Hi = $AE0017    ; TBD
+=$ae0018					EVID_ID_CARD_UNDEFINED0 = $AE0018    ; TBD
+=$ae0019					EVID_ID_CARD_UNDEFINED1 = $AE0019    ; TBD
+=$ae001a					EVID_ID_CARD_HW_Rev     = $AE001A    ; 00 - in Hex
+=$ae001b					EVID_ID_CARD_FPGA_Rev   = $AE001B    ; 00 - in Hex
+=$ae001c					EVID_ID_CARD_UNDEFINED2 = $AE001C    ; TBD
+=$ae001d					EVID_ID_CARD_UNDEFINED3 = $AE001D    ; TBD
+=$ae001e					EVID_ID_CARD_CHKSUM0    = $AE001E    ; Not Supported Yet
+=$ae001f					EVID_ID_CARD_CHKSUM1    = $AE001F    ; Not Supported Yet
+=$ae1000					EVID_FONT_MEM      = $AE1000
+=$ae1b00					EVID_FG_LUT        = $AE1B00
+=$ae1b40					EVID_BG_LUT        = $AE1B40
+=$ae1e00					EVID_MSTR_CTRL_REG_L	= $AE1E00
+=$01						EVID_Ctrl_Text_Mode_En  = $01       ; Enable the Text Mode
+=$ae1e01					EVID_MSTR_CTRL_REG_H    = $AE1E01
+=$01						EVID_800x600ModeEnable   = $01       ; 0 - 640x480 (Clock @ 25.175Mhz), 1 - 800x600 (Clock @ 40Mhz)
+=$01						EVID_Border_Ctrl_Enable = $01
+=$ae1e04					EVID_BORDER_CTRL_REG    = $AE1E04 ; Bit[0] - Enable (1 by default)  Bit[4..6]: X Scroll Offset ( Will scroll Left) (Acceptable Value: 0..7)
+=$ae1e05					EVID_BORDER_COLOR_B     = $AE1E05
+=$ae1e06					EVID_BORDER_COLOR_G     = $AE1E06
+=$ae1e07					EVID_BORDER_COLOR_R     = $AE1E07
+=$ae1e08					EVID_BORDER_X_SIZE      = $AE1E08; X-  Values: 0 - 32 (Default: 32)
+=$ae1e09					EVID_BORDER_Y_SIZE      = $AE1E09; Y- Values 0 -32 (Default: 32)
+=$ae1e10					EVID_TXT_CURSOR_CTRL_REG = $AE1E10   ;[0]  Enable Text Mode
+=$01						EVID_Cursor_Enable       = $01
+=$02						EVID_Cursor_Flash_Rate0  = $02       ; 00 - 1/Sec, 01 - 2/Sec, 10 - 4/Sec, 11 - 5/Sec
+=$04						EVID_Cursor_Flash_Rate1  = $04
+=$08						EVID_Cursor_FONT_Page0   = $08       ; Pick Font Page 0 or Font Page 1
+=$10						EVID_Cursor_FONT_Page1   = $10       ; Pick Font Page 0 or Font Page 1
+=$ae1e12					EVID_TXT_CURSOR_CHAR_REG = $AE1E12
+=$ae1e13					EVID_TXT_CURSOR_COLR_REG = $AE1E13
+=$ae1e14					EVID_TXT_CURSOR_X_REG_L  = $AE1E14
+=$ae1e15					EVID_TXT_CURSOR_X_REG_H  = $AE1E15
+=$ae1e16					EVID_TXT_CURSOR_Y_REG_L  = $AE1E16
+=$ae1e17					EVID_TXT_CURSOR_Y_REG_H  = $AE1E17
+=$ae1e1c					EVID_INFO_CHIP_NUM_L     = $AE1E1C
+=$ae1e1d					EVID_INFO_CHIP_NUM_H     = $AE1E1D
+=$ae1e1e					EVID_INFO_CHIP_VER_L     = $AE1E1E
+=$ae1e1f					EVID_INFO_CHIP_VER_H     = $AE1E1F
+=$ae2000					EVID_TEXT_MEM            = $AE2000
+=$ae4000					EVID_COLOR_MEM           = $AE4000
+=$aee000					EVID_ETHERNET_REG        = $AEE000
+
+;******  Return to file: src\kernel.asm
+
+.390400						IBOOT
+.390400		18		clc		                CLC               ; clear the carry flag
+.390401		fb		xce		                XCE               ; move carry to emulation flag.
+.390402		78		sei		                SEI               ; Disable interrupts
+.390403		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390405		a9 ff fe	lda #$feff	                LDA #STACK_END    ; initialize stack pointer
+.390408		1b		tcs		                TAS
+.390409		a2 00 10	ldx #$1000	                LDX #<>BOOT       ; Copy the kernel jump table to bank 0
+.39040c		a0 00 10	ldy #$1000	                LDY #<>BOOT       ; Ordinarily, this is done by GAVIN, but
+.39040f		a9 00 20	lda #$2000	                LDA #$2000        ; this is ensures it can be reloaded in case of errors
+.390412		54 00 38	mvn $38,$00	                MVN $38,$00       ; Or during soft loading of the kernel from the debug port
+.390415		48		pha		                PHA             ; begin setdp macro
+.390416		08		php		                PHP
+.390417		c2 20		rep #$20	                REP #$20        ; set A long
+.390419		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.39041c		5b		tcd		                TCD
+.39041d		28		plp		                PLP
+.39041e		68		pla		                PLA             ; end setdp macro
+.39041f		e2 20		sep #$20	                SEP #$20        ; set A short
+.390421		a2 00 00	ldx #$0000	                LDX #$0000
+.390424		a9 00		lda #$00	                LDA #$00
+.390426						CLEAR_MEM_LOOP
+.390426		95 00		sta $00,x	                STA $0000, X
+.390428		e8		inx		                INX
+.390429		e0 00 01	cpx #$0100	                CPX #$0100
+.39042c		d0 f8		bne $390426	                BNE CLEAR_MEM_LOOP
+.39042e		ea		nop		                NOP
+.39042f		a9 ff		lda #$ff	                LDA #$FF
+.390431		8f 48 01 00	sta $000148	                STA @lINT_EDGE_REG0
+.390435		8f 49 01 00	sta $000149	                STA @lINT_EDGE_REG1
+.390439		8f 4a 01 00	sta $00014a	                STA @lINT_EDGE_REG2
+.39043d		8f 4b 01 00	sta $00014b	                STA @lINT_EDGE_REG3
+.390441		8f 4c 01 00	sta $00014c	                STA @lINT_MASK_REG0
+.390445		8f 4d 01 00	sta $00014d	                STA @lINT_MASK_REG1
+.390449		8f 4e 01 00	sta $00014e	                STA @lINT_MASK_REG2
+.39044d		8f 4f 01 00	sta $00014f	                STA @lINT_MASK_REG3
+.390451		22 1a 11 39	jsl $39111a	                JSL INITRTC               ; Initialize the RTC
+.390455		e2 20		sep #$20	                SEP #$20        ; set A short
+.390457		af 87 e8 af	lda $afe887	                LDA @L GABE_SYS_STAT      ; Let's check the Presence of an Expansion Card here
+.39045b		29 10		and #$10	                AND #GABE_SYS_STAT_EXP    ; When there is a Card the Value is 1
+.39045d		c9 10		cmp #$10	                CMP #GABE_SYS_STAT_EXP
+.39045f		d0 1e		bne $39047f	                BNE SkipInitExpC100C200
+.390461		c2 20		rep #$20	                REP #$20        ; set A long
+.390463		af 12 00 ae	lda $ae0012	                LDA @L ESID_ID_CARD_ID_Lo    ; Load the Card ID and check for C100 or C200
+.390467		c9 64 00	cmp #$0064	                CMP #$0064
+.39046a		f0 0f		beq $39047b	                BEQ InitC100ESID
+.39046c		c9 c8 00	cmp #$00c8	                CMP #$00C8
+.39046f		d0 0e		bne $39047f	                BNE SkipInitExpC100C200
+.390471		22 38 6c 39	jsl $396c38	                JSL SIMPLE_INIT_ETHERNET_CTRL
+.390475		22 43 70 39	jsl $397043	                JSL INIT_EVID_VID_MODE
+.390479		80 04		bra $39047f	                BRA SkipInitExpC100C200
+.39047b						InitC100ESID:
+.39047b		22 38 6c 39	jsl $396c38	                JSL SIMPLE_INIT_ETHERNET_CTRL
+.39047f						SkipInitExpC100C200:
+.39047f		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390481		a2 48 00	ldx #$0048	                LDX #72                   ; Set these by default, but they will be changed later by Init Vicky Text Mode
+.390484		86 0f		stx $0f		                STX COLS_VISIBLE
+.390486		a0 34 00	ldy #$0034	                LDY #52
+.390489		84 13		sty $13		                STY LINES_VISIBLE
+.39048b		a2 80 00	ldx #$0080	                LDX #128
+.39048e		86 11		stx $11		                STX COLS_PER_LINE
+.390490		a0 40 00	ldy #$0040	                LDY #64
+.390493		84 15		sty $15		                STY LINES_MAX
+.390495		a9 00 a0	lda #$a000	                LDA #<>SCREEN_PAGE0      ; store the initial screen buffer location
+.390498		85 0c		sta $0c		                STA SCREENBEGIN
+.39049a		85 17		sta $17		                STA CURSORPOS
+.39049c		a9 00 c0	lda #$c000	                LDA #<>CS_COLOR_MEM_PTR   ; Set the initial COLOR cursor position
+.39049f		85 1f		sta $1f		                STA COLORPOS
+.3904a1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3904a3		a9 af		lda #$af	                LDA #`SCREEN_PAGE0
+.3904a5		85 0e		sta $0e		                STA SCREENBEGIN+2
+.3904a7		85 19		sta $19		                STA CURSORPOS+2
+.3904a9		a9 af		lda #$af	                LDA #`CS_COLOR_MEM_PTR    ; Set the initial COLOR cursor position
+.3904ab		85 21		sta $21		                STA COLORPOS+2
+.3904ad		a9 00		lda #$00	                LDA #$00
+.3904af		8d 87 0f	sta $0f87	                STA KEYBOARD_SC_FLG     ; Clear the Keyboard Flag
+.3904b2		a9 9f		lda #$9f	                LDA #$9F ; Channel Two - No Atteniation
+.3904b4		8f 00 f1 af	sta $aff100	                STA $AFF100
+.3904b8		a9 bf		lda #$bf	                LDA #$BF ; Channel Two - No Atteniation
+.3904ba		8f 00 f1 af	sta $aff100	                STA $AFF100
+.3904be		a9 df		lda #$df	                LDA #$DF ; Channel Two - No Atteniation
+.3904c0		8f 00 f1 af	sta $aff100	                STA $AFF100
+.3904c4		a9 ff		lda #$ff	                LDA #$FF ; Channel Two - No Atteniation
+.3904c6		8f 00 f1 af	sta $aff100	                STA $AFF100
+.3904ca		a9 ed		lda #$ed	                LDA #$ED                  ; Set the default text color to light gray on dark gray
+.3904cc		85 1e		sta $1e		                STA CURCOLOR
+.3904ce		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H
+.3904d2		29 01		and #$01	                AND #$01
+.3904d4		c9 01		cmp #$01	                CMP #$01
+.3904d6		d0 14		bne $3904ec	                BNE Alreadyin640480Mode
+.3904d8		af 01 00 af	lda $af0001	                LDA @L MASTER_CTRL_REG_H
+.3904dc		29 fc		and #$fc	                AND #$FC
+.3904de		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
+.3904e2		af 01 00 af	lda $af0001	                LDA @L MASTER_CTRL_REG_H
+.3904e6		09 01		ora #$01	                ORA #$01
+.3904e8		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
+.3904ec						Alreadyin640480Mode
+.3904ec		af 01 00 af	lda $af0001	                LDA @L MASTER_CTRL_REG_H
+.3904f0		29 fc		and #$fc	                AND #$FC
+.3904f2		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H ; Set it to 640x480 for real
+.3904f6		22 dc 10 00	jsl $0010dc	                JSL INITCODEC
+.3904fa		22 c4 10 00	jsl $0010c4	                JSL INITGAMMATABLE
+.3904fe		22 c8 10 00	jsl $0010c8	                JSL INITALLLUT
+.390502		22 ac 10 00	jsl $0010ac	                JSL INITCHLUT
+.390506		22 86 0e 39	jsl $390e86	                JSL INITMOUSEPOINTER
+.39050a		22 bc 10 00	jsl $0010bc	                JSL INITCURSOR
+.39050e		a9 00		lda #$00	                LDA #0
+.390510		22 38 10 00	jsl $001038	                JSL SETIN
+.390514		22 3c 10 00	jsl $00103c	                JSL SETOUT
+.390518		c2 20		rep #$20	                REP #$20        ; set A long
+.39051a		48		pha		                PHA             ; begin setdp macro
+.39051b		08		php		                PHP
+.39051c		c2 20		rep #$20	                REP #$20        ; set A long
+.39051e		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.390521		5b		tcd		                TCD
+.390522		28		plp		                PLP
+.390523		68		pla		                PLA             ; end setdp macro
+.390524		22 b4 10 00	jsl $0010b4	                JSL INITKEYBOARD ;
+.390528		22 b8 10 00	jsl $0010b8	                JSL INITMOUSE;  // I Seperated them
+.39052c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39052e		c2 10		rep #$10	                REP #$10        ; set X long
+.390530		a9 9f		lda #$9f	                LDA #$9F ; Channel Two - No Atteniation
+.390532		8f 00 f1 af	sta $aff100	                STA $AFF100
+.390536		a9 bf		lda #$bf	                LDA #$BF ; Channel Two - No Atteniation
+.390538		8f 00 f1 af	sta $aff100	                STA $AFF100
+.39053c		a9 df		lda #$df	                LDA #$DF ; Channel Two - No Atteniation
+.39053e		8f 00 f1 af	sta $aff100	                STA $AFF100
+.390542		a9 ff		lda #$ff	                LDA #$FF ; Channel Two - No Atteniation
+.390544		8f 00 f1 af	sta $aff100	                STA $AFF100
+.390548		a9 83		lda #$83	                LDA #$83 ; Channel Zero - No Atteniation
+.39054a		8f 00 f1 af	sta $aff100	                STA $AFF100
+.39054e		a9 12		lda #$12	                LDA #$12 ; Channel Zero - No Atteniation
+.390550		8f 00 f1 af	sta $aff100	                STA $AFF100
+.390554		a9 90		lda #$90	                LDA #$90 ; Channel One - No Atteniation
+.390556		8f 00 f1 af	sta $aff100	                STA $AFF100
+.39055a		a2 00 40	ldx #$4000	                LDX #16384      ; 400ms
+.39055d		22 2f 14 39	jsl $39142f	                JSL ILOOP_MS
+.390561		a9 9f		lda #$9f	                LDA #$9F ; Channel Two - No Atteniation
+.390563		8f 00 f1 af	sta $aff100	                STA $AFF100
+.390567		58		cli		                CLI                   ; Make sure no Interrupt will come and fuck up Init before this point.
+.390568		e2 20		sep #$20	                SEP #$20        ; set A short
+.39056a		c2 10		rep #$10	                REP #$10        ; set X long
+.39056c		48		pha		                PHA             ; begin setdbr macro
+.39056d		08		php		                PHP
+.39056e		e2 20		sep #$20	                SEP #$20        ; set A short
+.390570		a9 39		lda #$39	                LDA #`greet_msg
+.390572		48		pha		                PHA
+.390573		ab		plb		                PLB
+.390574		28		plp		                PLP
+.390575		68		pla		                PLA             ; end setdbr macro
+.390576		a2 00 00	ldx #$0000	                LDX #0
+.390579		bf 00 10 00	lda $001000,x	jmpcopy         LDA @l BOOT,X
+.39057d		9f 00 10 00	sta $001000,x	                STA @l $001000,X
+.390581		e8		inx		                INX
+.390582		e0 00 10	cpx #$1000	                CPX #$1000
+.390585		d0 f2		bne $390579	                BNE jmpcopy
+.390587						retry_boot
+.390587		22 98 42 39	jsl $394298	                JSL DOS_INIT          ; Initialize the "disc operating system"
+.39058b		22 00 00 3e	jsl $3e0000	                JSL BOOT_MENU           ; Show the splash screen / boot menu and wait for key presses
+.39058f		22 23 0b 39	jsl $390b23	                JSL ICLRSCREEN  ; Clear Screen and Set a standard color in Color Memory
+.390593		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390595		a2 00 00	ldx #$0000	                LDX #0
+.390598		a0 00 00	ldy #$0000	                LDY #0
+.39059b		22 fc 09 39	jsl $3909fc	                JSL ILOCATE
+.39059f						greet
+.39059f		48		pha		                PHA             ; begin setdbr macro
+.3905a0		08		php		                PHP
+.3905a1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3905a3		a9 39		lda #$39	                LDA #`greet_msg
+.3905a5		48		pha		                PHA
+.3905a6		ab		plb		                PLB
+.3905a7		28		plp		                PLP
+.3905a8		68		pla		                PLA             ; end setdbr macro
+.3905a9		a2 a4 71	ldx #$71a4	                LDX #<>greet_msg
+.3905ac		22 5f 07 39	jsl $39075f	                JSL IPRINT       ; print the first line
+.3905b0		22 6e 0b 39	jsl $390b6e	                JSL ICOLORFLAG  ; This is to set the Color Memory for the TExt Logo
+.3905b4		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3905b6		a9 ff fe	lda #$feff	                LDA #STACK_END    ; We are the root, let's make sure from now on, that we start clean
+.3905b9		1b		tcs		                TAS
+.3905ba		e2 20		sep #$20	                SEP #$20        ; set A short
+.3905bc		c2 10		rep #$10	                REP #$10        ; set X long
+.3905be		af 08 00 00	lda $000008	                LDA @l KRNL_BOOT_MENU_K ; Get the Value of the Keyboard Boot Choice
+.3905c2		c9 20		cmp #$20	                CMP #CHAR_SP          ; Did the user press SPACE?
+.3905c4		f0 10		beq $3905d6	                BEQ BOOT_DIP          ; Yes: boot via the DIP switches
+.3905c6		c9 0d		cmp #$0d	                CMP #CHAR_CR          ; Did the user press RETURN?
+.3905c8		f0 1e		beq $3905e8	                BEQ BOOTBASIC         ; Yes: go straight to BASIC
+.3905ca		c9 81		cmp #$81	                CMP #CHAR_F1          ; Did the user press F1?
+.3905cc		f0 62		beq $390630	                BEQ BOOTFLOPPY        ; Yes: boot via the floppy
+.3905ce		c9 82		cmp #$82	                CMP #CHAR_F2          ; Did the user press F2?
+.3905d0		f0 1d		beq $3905ef	                BEQ BOOTSDC           ; Yes: boot via the SDC
+.3905d2		c9 83		cmp #$83	                CMP #CHAR_F3          ; Did the user press F3?
+.3905d4		f0 39		beq $39060f	                BEQ BOOTIDE           ; Yes: boot via the IDE
+.3905d6		af 0e e8 af	lda $afe80e	BOOT_DIP        LDA @lDIP_BOOTMODE    ; {HD_INSTALLED, 5'b0_0000, BOOT_MODE[1], BOOT_MODE[0]}
+.3905da		29 03		and #$03	                AND #%00000011        ; Look at the mode bits
+.3905dc		c9 00		cmp #$00	                CMP #DIP_BOOT_IDE     ; DIP set for IDE?
+.3905de		f0 2f		beq $39060f	                BEQ BOOTIDE           ; Yes: Boot from the IDE
+.3905e0		c9 01		cmp #$01	                CMP #DIP_BOOT_SDCARD  ; DIP set for SD card?
+.3905e2		f0 0b		beq $3905ef	                BEQ BOOTSDC           ; Yes: try to boot from the SD card
+.3905e4		c9 02		cmp #$02	                CMP #DIP_BOOT_FLOPPY  ; DIP set for floppy?
+.3905e6		f0 48		beq $390630	                BEQ BOOTFLOPPY        ; Yes: try to boot from the floppy
+.3905e8						IRESTORE
+.3905e8		5c 00 00 3a	jmp $3a0000	BOOTBASIC       JML BASIC             ; Cold start of the BASIC interpreter (or its replacement)
+.3905ec		ea		nop		CREDIT_LOCK     NOP
+.3905ed		80 fd		bra $3905ec	                BRA CREDIT_LOCK
+.3905ef		a2 02 76	ldx #$7602	BOOTSDC         LDX #<>sdc_boot
+.3905f2		22 5f 07 39	jsl $39075f	                JSL IPRINT
+.3905f6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3905f8		a9 02		lda #$02	                LDA #BIOS_DEV_SD
+.3905fa		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
+.3905fe		22 6a 43 39	jsl $39436a	                JSL DOS_MOUNT         ; Mount the SDC
+.390602		90 06		bcc $39060a	                BCC sdc_error         ; Print an error message if couldn't get anything
+.390604		22 25 45 39	jsl $394525	                JSL DOS_TESTBOOT      ; Try to boot from the SDC's MBR
+.390608		80 de		bra $3905e8	                BRA BOOTBASIC         ; If we couldn't fall, into BASIC
+.39060a		a2 86 75	ldx #$7586	sdc_error       LDX #<>sdc_err_boot   ; Print a message saying SD card booting is not implemented
+.39060d		80 40		bra $39064f	                BRA PR_BOOT_ERROR
+.39060f		a2 19 76	ldx #$7619	BOOTIDE         LDX #<>ide_boot
+.390612		22 5f 07 39	jsl $39075f	                JSL IPRINT
+.390616		e2 20		sep #$20	                SEP #$20        ; set A short
+.390618		a9 06		lda #$06	                LDA #BIOS_DEV_HD0
+.39061a		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
+.39061e		22 6a 43 39	jsl $39436a	                JSL DOS_MOUNT         ; Mount the IDE drive
+.390622		90 07		bcc $39062b	                BCC hdc_error         ; Print an error message if couldn't get anything
+.390624		22 25 45 39	jsl $394525	                JSL DOS_TESTBOOT      ; Try to boot from the IDE's MBR
+.390628		82 bd ff	brl $3905e8	                BRL BOOTBASIC         ; If we couldn't fall, into BASIC
+.39062b		a2 a2 75	ldx #$75a2	hdc_error       LDX #<>ide_err_boot   ; Print a message saying SD card booting is not implemented
+.39062e		80 1f		bra $39064f	                BRA PR_BOOT_ERROR
+.390630		a2 eb 75	ldx #$75eb	BOOTFLOPPY      LDX #<>fdc_boot
+.390633		22 5f 07 39	jsl $39075f	                JSL IPRINT
+.390637		e2 20		sep #$20	                SEP #$20        ; set A short
+.390639		a9 00		lda #$00	                LDA #BIOS_DEV_FDC
+.39063b		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
+.39063f		22 cb 65 39	jsl $3965cb	                JSL FDC_MOUNT         ; Mount the floppy drive
+.390643		90 07		bcc $39064c	                BCC fdc_error         ; Print an error message if couldn't get anything
+.390645		22 25 45 39	jsl $394525	                JSL DOS_TESTBOOT      ; Try to boot from the FDC's MBR
+.390649		82 9c ff	brl $3905e8	                BRL BOOTBASIC         ; If we couldn't, fall into BASIC
+.39064c		a2 c5 75	ldx #$75c5	fdc_error       LDX #<>fdc_err_boot   ; Print a message saying SD card booting is not implemented
+.39064f		22 5f 07 39	jsl $39075f	PR_BOOT_ERROR   JSL IPRINT            ; Print the error message in X
+.390653		a2 61 75	ldx #$7561	                LDX #<>boot_retry     ; Print the boot retry prompt
+.390656		22 5f 07 39	jsl $39075f	                JSL IPRINT
+.39065a		22 f9 06 39	jsl $3906f9	boot_wait_key   JSL IGETCHW           ; Wait for a keypress
+.39065e		c9 52		cmp #$52	                CMP #'R'              ; Was "R" pressed?
+.390660		d0 03		bne $390665	                BNE chk_r_lc
+.390662		82 22 ff	brl $390587	                BRL retry_boot        ; Yes: retry the boot sequence
+.390665		c9 72		cmp #$72	chk_r_lc        CMP #'r'
+.390667		d0 03		bne $39066c	                BNE chk_b_lc
+.390669		82 1b ff	brl $390587	                BRL retry_boot
+.39066c		c9 62		cmp #$62	chk_b_lc        CMP #'b'              ; Was "B" pressed?
+.39066e		d0 03		bne $390673	                BNE chk_b_lc_not         ; Yes: try going to BASIC
+.390670		82 75 ff	brl $3905e8	                BRL BOOTBASIC
+.390673						chk_b_lc_not:
+.390673		c9 42		cmp #$42	                CMP #'B'
+.390675		d0 03		bne $39067a	                BNE chk_b_lc_not0
+.390677		82 6e ff	brl $3905e8	                BRL BOOTBASIC
+.39067a						chk_b_lc_not0:
+.39067a		80 de		bra $39065a	                BRA boot_wait_key     ; No: keep waiting
+.39067c						IBREAK
+.39067c		48		pha		                PHA             ; begin setdp macro
+.39067d		08		php		                PHP
+.39067e		c2 20		rep #$20	                REP #$20        ; set A long
+.390680		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.390683		5b		tcd		                TCD
+.390684		28		plp		                PLP
+.390685		68		pla		                PLA             ; end setdp macro
+.390686		68		pla		                PLA             ; Pull .Y and stuff it in the CPUY variable
+.390687		8f 48 02 00	sta $000248	                STA CPUY
+.39068b		68		pla		                PLA             ; Pull .X and stuff it in the CPUY variable
+.39068c		8f 46 02 00	sta $000246	                STA CPUX
+.390690		68		pla		                PLA             ; Pull .A and stuff it in the CPUY variable
+.390691		8f 44 02 00	sta $000244	                STA CPUA
+.390695		68		pla		                PLA
+.390696		8f 4c 02 00	sta $00024c	                STA CPUDP       ; Pull Direct page
+.39069a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39069c		68		pla		                PLA             ; Pull Data Bank (8 bits)
+.39069d		8f 4e 02 00	sta $00024e	                STA CPUDBR
+.3906a1		68		pla		                PLA             ; Pull Flags (8 bits)
+.3906a2		8f 4f 02 00	sta $00024f	                STA CPUFLAGS
+.3906a6		c2 20		rep #$20	                REP #$20        ; set A long
+.3906a8		68		pla		                PLA             ; Pull Program Counter (16 bits)
+.3906a9		8f 40 02 00	sta $000240	                STA CPUPC
+.3906ad		e2 20		sep #$20	                SEP #$20        ; set A short
+.3906af		68		pla		                PLA             ; Pull Program Bank (8 bits)
+.3906b0		8f 42 02 00	sta $000242	                STA CPUPBR
+.3906b4		c2 20		rep #$20	                REP #$20        ; set A long
+.3906b6		3b		tsc		                TSA             ; Get the stack
+.3906b7		8f 4a 02 00	sta $00024a	                STA CPUSTACK    ; Store the stack at immediately before the interrupt was asserted
+.3906bb		a9 ff fe	lda #$feff	                LDA #<>STACK_END   ; initialize stack pointer back to the bootup value
+.3906be		1b		tcs		                TAS
+.3906bf		5c 04 00 3a	jmp $3a0004	                JML MONITOR
+.3906c3						IREADY
+.3906c3		48		pha		                PHA             ; begin setdbr macro
+.3906c4		08		php		                PHP
+.3906c5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3906c7		a9 39		lda #$39	                LDA #`ready_msg
+.3906c9		48		pha		                PHA
+.3906ca		ab		plb		                PLB
+.3906cb		28		plp		                PLP
+.3906cc		68		pla		                PLA             ; end setdbr macro
+.3906cd		e2 20		sep #$20	                SEP #$20        ; set A short
+.3906cf		a2 34 76	ldx #$7634	                LDX #<>ready_msg
+.3906d2		22 5f 07 39	jsl $39075f	                JSL IPRINT
+.3906d6						IREADYWAIT
+.3906d6		22 f0 06 39	jsl $3906f0	                JSL IGETCHE
+.3906da		80 fa		bra $3906d6	                BRA IREADYWAIT
+.3906dc		db		stp		IKEYDOWN        STP             ; Keyboard key pressed
+.3906dd		db		stp		IRETURN         STP
+.3906de		08		php		ISETIN          PHP
+.3906df		e2 20		sep #$20	                SEP #$20        ; set A short
+.3906e1		8f 04 07 00	sta $000704	                STA @lCHAN_IN   ; Save the channel number
+.3906e5		28		plp		                PLP
+.3906e6		6b		rtl		                RTL
+.3906e7		08		php		ISETOUT         PHP
+.3906e8		e2 20		sep #$20	                SEP #$20        ; set A short
+.3906ea		8f 03 07 00	sta $000703	                STA @lCHAN_OUT  ; Save the channel number
+.3906ee		28		plp		                PLP
+.3906ef		6b		rtl		                RTL
+.3906f0		22 f9 06 39	jsl $3906f9	IGETCHE         JSL IGETCHW
+.3906f4		22 7f 07 39	jsl $39077f	                JSL IPUTC
+.3906f8		6b		rtl		                RTL
+.3906f9						IGETCHW
+.3906f9		da		phx		                PHX
+.3906fa		5a		phy		                PHY
+.3906fb		8b		phb		                PHB
+.3906fc		0b		phd		                PHD
+.3906fd		08		php		                PHP
+.3906fe		e2 20		sep #$20	                SEP #$20        ; set A short
+.390700		af 04 07 00	lda $000704	                LDA @lCHAN_IN       ; Get the current input channel
+.390704		f0 1b		beq $390721	                BEQ getc_keyboard   ; If it's keyboard, read from the key buffer
+.390706		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
+.390708		f0 0d		beq $390717	                BEQ getc_uart       ; Yes: handle reading from the UART
+.39070a		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
+.39070c		f0 09		beq $390717	                BEQ getc_uart       ; Yes: handle reading from the UART
+.39070e		a9 00		lda #$00	                LDA #0              ; Return 0 if no valid device
+.390710		28		plp		                PLP
+.390711		38		sec		                SEC                 ; And return carry set
+.390712		2b		pld		                PLD
+.390713		ab		plb		                PLB
+.390714		7a		ply		                PLY
+.390715		fa		plx		                PLX
+.390716		6b		rtl		                RTL
+.390717		22 f1 59 39	jsl $3959f1	getc_uart       JSL UART_SELECT     ; Select the correct COM port
+.39071b		22 a5 5a 39	jsl $395aa5	                JSL UART_GETC       ; Get the charater from the COM port
+.39071f		80 04		bra $390725	                BRA done
+.390721		22 7e 1a 38	jsl $381a7e	getc_keyboard   JSL KBD_GETCW       ; Get the character from the keyboard
+.390725		28		plp		done            PLP
+.390726		18		clc		                CLC                 ; Return carry clear for valid data
+.390727		2b		pld		                PLD
+.390728		ab		plb		                PLB
+.390729		7a		ply		                PLY
+.39072a		fa		plx		                PLX
+.39072b		6b		rtl		                RTL
+.39072c						IGETCH
+.39072c		da		phx		                PHX
+.39072d		5a		phy		                PHY
+.39072e		8b		phb		                PHB
+.39072f		0b		phd		                PHD
+.390730		08		php		                PHP
+.390731		e2 20		sep #$20	                SEP #$20        ; set A short
+.390733		af 04 07 00	lda $000704	                LDA @lCHAN_IN       ; Get the current input channel
+.390737		f0 1b		beq $390754	                BEQ getc_keyboard   ; If it's keyboard, read from the key buffer
+.390739		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
+.39073b		f0 0d		beq $39074a	                BEQ getc_uart       ; Yes: handle reading from the UART
+.39073d		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
+.39073f		f0 09		beq $39074a	                BEQ getc_uart       ; Yes: handle reading from the UART
+.390741		a9 00		lda #$00	                LDA #0              ; Return 0 if no valid device
+.390743		28		plp		                PLP
+.390744		38		sec		                SEC                 ; And return carry set
+.390745		2b		pld		                PLD
+.390746		ab		plb		                PLB
+.390747		7a		ply		                PLY
+.390748		fa		plx		                PLX
+.390749		6b		rtl		                RTL
+.39074a		22 f1 59 39	jsl $3959f1	getc_uart       JSL UART_SELECT     ; Select the correct COM port
+.39074e		22 a5 5a 39	jsl $395aa5	                JSL UART_GETC       ; Get the charater from the COM port
+.390752		80 04		bra $390758	                BRA done
+.390754		22 c1 1a 38	jsl $381ac1	getc_keyboard   JSL KBD_GETC        ; Get the character from the keyboard
+.390758		28		plp		done            PLP
+.390759		18		clc		                CLC                 ; Return carry clear for valid data
+.39075a		2b		pld		                PLD
+.39075b		ab		plb		                PLB
+.39075c		7a		ply		                PLY
+.39075d		fa		plx		                PLX
+.39075e		6b		rtl		                RTL
+.39075f		22 68 07 39	jsl $390768	IPRINT          JSL IPUTS
+.390763		22 f8 08 39	jsl $3908f8	                JSL IPRINTCR
+.390767		6b		rtl		                RTL
+.390768		48		pha		IPUTS           PHA
+.390769		08		php		                PHP
+.39076a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39076c		c2 10		rep #$10	                REP #$10        ; set X long
+.39076e		bd 00 00	lda $390000,x	iputs1          LDA $0,b,x      ; read from the string
+.390771		f0 08		beq $39077b	                BEQ iputs_done
+.390773		22 7f 07 39	jsl $39077f	iputs2          JSL IPUTC
+.390777		e8		inx		iputs3          INX
+.390778		4c 6e 07	jmp $39076e	                JMP iputs1
+.39077b		e8		inx		iputs_done      INX
+.39077c		28		plp		                PLP
+.39077d		68		pla		                PLA
+.39077e		6b		rtl		                RTL
+.39077f						IPUTC
+.39077f		da		phx		                PHX
+.390780		5a		phy		                PHY
+.390781		0b		phd		                PHD
+.390782		8b		phb		                PHB
+.390783		08		php		                PHP                 ; stash the flags (we'll be changing M)
+.390784		48		pha		                PHA             ; begin setdp macro
+.390785		08		php		                PHP
+.390786		c2 20		rep #$20	                REP #$20        ; set A long
+.390788		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.39078b		5b		tcd		                TCD
+.39078c		28		plp		                PLP
+.39078d		68		pla		                PLA             ; end setdp macro
+.39078e		48		pha		                PHA             ; begin setdbr macro
+.39078f		08		php		                PHP
+.390790		e2 20		sep #$20	                SEP #$20        ; set A short
+.390792		a9 00		lda #$00	                LDA #0
+.390794		48		pha		                PHA
+.390795		ab		plb		                PLB
+.390796		28		plp		                PLP
+.390797		68		pla		                PLA             ; end setdbr macro
+.390798		e2 20		sep #$20	                SEP #$20        ; set A short
+.39079a		c2 10		rep #$10	                REP #$10        ; set X long
+.39079c		48		pha		                PHA                 ; Save the character to print
+.39079d		af 03 07 00	lda $000703	                LDA @lCHAN_OUT      ; Check the output channel #
+.3907a1		f0 16		beq $3907b9	                BEQ putc_screen     ; If it's 0: print to the screen
+.3907a3		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
+.3907a5		f0 07		beq $3907ae	                BEQ putc_uart       ; Yes: handle printing to the UART
+.3907a7		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
+.3907a9		f0 03		beq $3907ae	                BEQ putc_uart       ; Yes: handle printing to the UART
+.3907ab		68		pla		                PLA                 ; Otherwise, just exit
+.3907ac		80 57		bra $390805	                BRA done
+.3907ae		22 f1 59 39	jsl $3959f1	putc_uart       JSL UART_SELECT     ; Point to the correct UART
+.3907b2		68		pla		                PLA                 ; Recover the character to send
+.3907b3		22 c6 5a 39	jsl $395ac6	                JSL UART_PUTC       ; Send the character
+.3907b7		80 4c		bra $390805	                BRA done
+.3907b9		68		pla		putc_screen     PLA                 ; Get the character to print
+.3907ba		c9 0a		cmp #$0a	                CMP #CHAR_LF        ; Linefeed moves cursor down one line
+.3907bc		f0 69		beq $390827	                BEQ go_down
+.3907be		c9 20		cmp #$20	                CMP #$20
+.3907c0		90 19		bcc $3907db	                BCC check_ctrl0     ; [$00..$1F]: check for arrows
+.3907c2		c9 7f		cmp #$7f	                CMP #$7F
+.3907c4		f0 45		beq $39080b	                BEQ do_del
+.3907c6		b0 02		bcs $3907ca	                BCS check_A0        ; [$20..$7E]: print it
+.3907c8		80 31		bra $3907fb	                BRA printc
+.3907ca		c9 a0		cmp #$a0	check_A0        CMP #$A0
+.3907cc		90 02		bcc $3907d0	                BCC check_ctrl1
+.3907ce		80 2b		bra $3907fb	                BRA printc          ; [$A0..$FF]: print it
+.3907d0		c9 91		cmp #$91	check_ctrl1     CMP #CHAR_DOWN      ; If the down arrow key was pressed
+.3907d2		f0 53		beq $390827	                BEQ go_down         ; ... move the cursor down one row
+.3907d4		c9 9d		cmp #$9d	                CMP #CHAR_LEFT      ; If the left arrow key was pressed
+.3907d6		f0 61		beq $390839	                BEQ go_left         ; ... move the cursor left one column
+.3907d8		4c 05 08	jmp $390805	                JMP done
+.3907db		c9 09		cmp #$09	check_ctrl0     CMP #CHAR_TAB       ; If it's a TAB...
+.3907dd		f0 69		beq $390848	                BEQ do_TAB          ; ... move to the next TAB stop
+.3907df		c9 08		cmp #$08	                CMP #CHAR_BS        ; If it's a backspace...
+.3907e1		f0 34		beq $390817	                BEQ backspace       ; ... move the cursor back and replace with a space
+.3907e3		c9 0d		cmp #$0d	                CMP #CHAR_CR        ; If the carriage return was pressed
+.3907e5		f0 3a		beq $390821	                BEQ do_cr           ; ... move cursor down and to the first column
+.3907e7		c9 11		cmp #$11	                CMP #CHAR_UP        ; If the up arrow key was pressed
+.3907e9		f0 42		beq $39082d	                BEQ go_up           ; ... move the cursor up one row
+.3907eb		c9 1d		cmp #$1d	                CMP #CHAR_RIGHT     ; If the right arrow key was pressed
+.3907ed		f0 44		beq $390833	                BEQ go_right        ; ... move the cursor right one column
+.3907ef		c9 0f		cmp #$0f	                CMP #CHAR_INS       ; If the insert key was pressed
+.3907f1		f0 1e		beq $390811	                BEQ do_ins          ; ... insert a space
+.3907f3		c9 01		cmp #$01	                CMP #CHAR_CTRL_A    ; Check for CTRL-A (start of line)
+.3907f5		f0 48		beq $39083f	                BEQ go_sol          ; ... move the cursor to the start of the line
+.3907f7		c9 05		cmp #$05	                CMP #CHAR_CTRL_E    ; Check for CTRL-E (end of line)
+.3907f9		f0 74		beq $39086f	                BEQ go_eol          ; ... move the cursor to the end of the line
+.3907fb		87 17		sta [$17]	printc          STA [CURSORPOS]     ; Save the character on the screen
+.3907fd		a5 1e		lda $1e		                LDA CURCOLOR        ; Set the color based on CURCOLOR
+.3907ff		87 1f		sta [$1f]	                STA [COLORPOS]
+.390801		22 58 09 39	jsl $390958	                JSL ICSRRIGHT       ; And advance the cursor
+.390805		28		plp		done            PLP
+.390806		ab		plb		                PLB
+.390807		2b		pld		                PLD
+.390808		7a		ply		                PLY
+.390809		fa		plx		                PLX
+.39080a		6b		rtl		                RTL
+.39080b		22 9c 08 39	jsl $39089c	do_del          JSL SCRSHIFTLL      ; Shift the current line left one space into the cursor
+.39080f		80 f4		bra $390805	                BRA done
+.390811		22 c0 08 39	jsl $3908c0	do_ins          JSL SCRSHIFTLR      ; Shift the current line right one space from the cursor
+.390815		80 ee		bra $390805	                BRA done
+.390817		22 8b 09 39	jsl $39098b	backspace       JSL ICSRLEFT
+.39081b		22 9c 08 39	jsl $39089c	                JSL SCRSHIFTLL      ; Shift the current line left one space into the cursor
+.39081f		80 e4		bra $390805	                BRA done
+.390821		22 f8 08 39	jsl $3908f8	do_cr           JSL IPRINTCR        ; Move the cursor to the beginning of the next line
+.390825		80 de		bra $390805	                BRA done
+.390827		22 d7 09 39	jsl $3909d7	go_down         JSL ICSRDOWN        ; Move the cursor down one row (might force a scroll)
+.39082b		80 d8		bra $390805	                BRA done
+.39082d		22 b1 09 39	jsl $3909b1	go_up           JSL ICSRUP          ; Move the cursor up one line
+.390831		80 d2		bra $390805	                BRA done
+.390833		22 58 09 39	jsl $390958	go_right        JSL ICSRRIGHT       ; Move the cursor right one column
+.390837		80 cc		bra $390805	                BRA done
+.390839		22 8b 09 39	jsl $39098b	go_left         JSL ICSRLEFT        ; Move the cursor left one column
+.39083d		80 c6		bra $390805	                BRA done
+.39083f						go_sol
+.39083f		c2 20		rep #$20	                REP #$20        ; set A long
+.390841		a2 00 00	ldx #$0000	                LDX #0
+.390844		a4 1c		ldy $1c		                LDY CURSORY
+.390846		80 21		bra $390869	                BRA do_locate
+.390848						do_TAB
+.390848		c2 20		rep #$20	                REP #$20        ; set A long
+.39084a		a5 1a		lda $1a		                LDA CURSORX         ; Get the current column
+.39084c		29 f8 ff	and #$fff8	                AND #$FFF8          ; See which group of 8 it's in
+.39084f		18		clc		                CLC
+.390850		69 08 00	adc #$0008	                ADC #$0008          ; And move it to the next one
+.390853		aa		tax		                TAX
+.390854		a4 1c		ldy $1c		                LDY CURSORY
+.390856		e2 20		sep #$20	                SEP #$20        ; set A short
+.390858		e4 0f		cpx $0f		set_xy          CPX COLS_VISIBLE    ; Check if we're still on screen horizontally
+.39085a		90 04		bcc $390860	                BCC check_row       ; Yes: check the row
+.39085c		a2 00 00	ldx #$0000	                LDX #0              ; No: move to the first column...
+.39085f		c8		iny		                INY                 ; ... and the next row
+.390860		c4 13		cpy $13		check_row       CPY LINES_VISIBLE   ; Check if we're still on the screen vertically
+.390862		90 05		bcc $390869	                BCC do_locate       ; Yes: reposition the cursor
+.390864		22 48 0a 39	jsl $390a48	                JSL ISCROLLUP       ; No: scroll the screen
+.390868		88		dey		                DEY                 ; And set the row to the last one
+.390869		22 fc 09 39	jsl $3909fc	do_locate       JSL ILOCATE         ; Set the cursor position
+.39086d		80 96		bra $390805	                BRA done
+.39086f		a6 0f		ldx $0f		go_eol          LDX COLS_VISIBLE    ; Move the cursor to the right most column
+.390871		ca		dex		                DEX
+.390872		a4 1c		ldy $1c		                LDY CURSORY
+.390874		22 fc 09 39	jsl $3909fc	                JSL ILOCATE
+.390878		e2 20		sep #$20	                SEP #$20        ; set A short
+.39087a		a7 17		lda [$17]	eol_loop        LDA [CURSORPOS]     ; Get the character under the cursor
+.39087c		c9 20		cmp #$20	                CMP #CHAR_SP        ; Is it blank?
+.39087e		d0 0b		bne $39088b	                BNE eol_done        ; No: exit the loop
+.390880		22 8b 09 39	jsl $39098b	                JSL ICSRLEFT        ; Yes: move to the left
+.390884		a6 1a		ldx $1a		                LDX CURSORX         ; Are we at column 0?
+.390886		d0 f2		bne $39087a	                BNE eol_loop        ; No: try again
+.390888		82 7a ff	brl $390805	                BRL done            ; Yes: we're done
+.39088b		a6 1a		ldx $1a		eol_done        LDX CURSORX         ; Check the column
+.39088d		e8		inx		                INX
+.39088e		e4 0f		cpx $0f		                CPX COLS_VISIBLE    ; Is it the right most?
+.390890		d0 03		bne $390895	                BNE eol_right
+.390892		82 70 ff	brl $390805	                BRL done            ; Yes: we're done
+.390895		22 58 09 39	jsl $390958	eol_right       JSL ICSRRIGHT       ; No: move right one column
+.390899		82 69 ff	brl $390805	                BRL done
+.39089c		da		phx		SCRSHIFTLL      PHX
+.39089d		5a		phy		                PHY
+.39089e		48		pha		                PHA
+.39089f		0b		phd		                PHD
+.3908a0		08		php		                PHP
+.3908a1		48		pha		                PHA             ; begin setdp macro
+.3908a2		08		php		                PHP
+.3908a3		c2 20		rep #$20	                REP #$20        ; set A long
+.3908a5		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.3908a8		5b		tcd		                TCD
+.3908a9		28		plp		                PLP
+.3908aa		68		pla		                PLA             ; end setdp macro
+.3908ab		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3908ad		a5 17		lda $17		                LDA CURSORPOS       ; Get the current cursor position
+.3908af		a8		tay		                TAY                 ; Set it as the destination
+.3908b0		aa		tax		                TAX
+.3908b1		e8		inx		                INX                 ; And set the next cell as the source
+.3908b2		18		clc		                CLC                 ; Calculate the length of the block to move
+.3908b3		a5 0f		lda $0f		                LDA COLS_VISIBLE    ; as columns visible - X
+.3908b5		e5 1a		sbc $1a		                SBC CURSORX
+.3908b7		54 af af	mvn $af,$af	                MVN $AF, $AF        ; And move the block
+.3908ba		28		plp		                PLP
+.3908bb		2b		pld		                PLD
+.3908bc		68		pla		                PLA
+.3908bd		7a		ply		                PLY
+.3908be		fa		plx		                PLX
+.3908bf		6b		rtl		                RTL
+.3908c0		da		phx		SCRSHIFTLR      PHX
+.3908c1		48		pha		                PHA
+.3908c2		0b		phd		                PHD
+.3908c3		08		php		                PHP
+.3908c4		48		pha		                PHA             ; begin setdp macro
+.3908c5		08		php		                PHP
+.3908c6		c2 20		rep #$20	                REP #$20        ; set A long
+.3908c8		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.3908cb		5b		tcd		                TCD
+.3908cc		28		plp		                PLP
+.3908cd		68		pla		                PLA             ; end setdp macro
+.3908ce		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3908d0		a5 1a		lda $1a		                LDA CURSORX         ; What column are we on
+.3908d2		1a		inc a		                INC A
+.3908d3		c5 0f		cmp $0f		                CMP COLS_VISIBLE    ; >= the # visible?
+.3908d5		b0 1b		bcs $3908f2	                BGE done            ; Yes: just skip the whole thing
+.3908d7		38		sec		                SEC                 ; Calculate the length of the block to move
+.3908d8		a5 0f		lda $0f		                LDA COLS_VISIBLE
+.3908da		e5 1a		sbc $1a		                SBC CURSORX
+.3908dc		1a		inc a		                INC A
+.3908dd		18		clc		                CLC
+.3908de		65 17		adc $17		                ADC CURSORPOS       ; Add the current cursor position
+.3908e0		3a		dec a		                DEC A
+.3908e1		a8		tay		                TAY                 ; Make it the destination
+.3908e2		3a		dec a		                DEC A               ; Move to the previous column
+.3908e3		aa		tax		                TAX                 ; Make it the source
+.3908e4		38		sec		                SEC                 ; Calculate the length of the block to move
+.3908e5		a5 0f		lda $0f		                LDA COLS_VISIBLE    ; as columns visible - X
+.3908e7		e5 1a		sbc $1a		                SBC CURSORX
+.3908e9		44 af af	mvp $af,$af	                MVP $AF, $AF        ; And move the block
+.3908ec		e2 20		sep #$20	                SEP #$20        ; set A short
+.3908ee		a9 20		lda #$20	                LDA #CHAR_SP        ; Put a blank space at the cursor position
+.3908f0		87 17		sta [$17]	                STA [CURSORPOS]
+.3908f2		28		plp		done            PLP
+.3908f3		2b		pld		                PLD
+.3908f4		68		pla		                PLA
+.3908f5		fa		plx		                PLX
+.3908f6		6b		rtl		                RTL
+.3908f7						IPUTB
+.3908f7		6b		rtl		                RTL
+.3908f8						IPRINTCR
+.3908f8		da		phx		                PHX
+.3908f9		5a		phy		                PHY
+.3908fa		8b		phb		                PHB
+.3908fb		0b		phd		                PHD
+.3908fc		08		php		                PHP
+.3908fd		48		pha		                PHA             ; begin setdbr macro
+.3908fe		08		php		                PHP
+.3908ff		e2 20		sep #$20	                SEP #$20        ; set A short
+.390901		a9 00		lda #$00	                LDA #0
+.390903		48		pha		                PHA
+.390904		ab		plb		                PLB
+.390905		28		plp		                PLP
+.390906		68		pla		                PLA             ; end setdbr macro
+.390907		48		pha		                PHA             ; begin setdp macro
+.390908		08		php		                PHP
+.390909		c2 20		rep #$20	                REP #$20        ; set A long
+.39090b		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.39090e		5b		tcd		                TCD
+.39090f		28		plp		                PLP
+.390910		68		pla		                PLA             ; end setdp macro
+.390911		e2 20		sep #$20	                SEP #$20        ; set A short
+.390913		c2 10		rep #$10	                REP #$10        ; set X long
+.390915		af 03 07 00	lda $000703	                LDA @lCHAN_OUT
+.390919		f0 1c		beq $390937	                BEQ scr_printcr
+.39091b		c9 01		cmp #$01	                CMP #CHAN_COM1      ; Check to see if it's the COM1 port
+.39091d		f0 06		beq $390925	                BEQ uart_printcr    ; Yes: handle printing to the UART
+.39091f		c9 02		cmp #$02	                CMP #CHAN_COM2      ; Check to see if it's the COM2 port
+.390921		f0 02		beq $390925	                BEQ uart_printcr    ; Yes: handle printing to the UART
+.390923		80 1c		bra $390941	                BRA done
+.390925		22 f1 59 39	jsl $3959f1	uart_printcr    JSL UART_SELECT
+.390929		a9 0d		lda #$0d	                LDA #CHAR_CR
+.39092b		22 7f 07 39	jsl $39077f	                JSL IPUTC
+.39092f		a9 0a		lda #$0a	                LDA #CHAR_LF
+.390931		22 7f 07 39	jsl $39077f	                JSL IPUTC
+.390935		80 0a		bra $390941	                BRA done
+.390937		a2 00 00	ldx #$0000	scr_printcr     LDX #0
+.39093a		a4 1c		ldy $1c		                LDY CURSORY
+.39093c		c8		iny		                INY
+.39093d		22 fc 09 39	jsl $3909fc	                JSL ILOCATE
+.390941		28		plp		done            PLP
+.390942		2b		pld		                PLD
+.390943		ab		plb		                PLB
+.390944		7a		ply		                PLY
+.390945		fa		plx		                PLX
+.390946		6b		rtl		                RTL
+.390947		da		phx		ICSRHOME        PHX
+.390948		5a		phy		                PHY
+.390949		08		php		                PHP
+.39094a		a2 00 00	ldx #$0000	                LDX #0
+.39094d		a0 00 00	ldy #$0000	                LDY #0
+.390950		22 fc 09 39	jsl $3909fc	                JSL ILOCATE
+.390954		28		plp		                PLP
+.390955		7a		ply		                PLY
+.390956		fa		plx		                PLX
+.390957		6b		rtl		                RTL
+.390958		da		phx		ICSRRIGHT       PHX
+.390959		5a		phy		                PHY
+.39095a		48		pha		                PHA
+.39095b		0b		phd		                PHD
+.39095c		08		php		                PHP
+.39095d		c2 20		rep #$20	                REP #$20        ; set A long
+.39095f		c2 10		rep #$10	                REP #$10        ; set X long
+.390961		48		pha		                PHA             ; begin setdp macro
+.390962		08		php		                PHP
+.390963		c2 20		rep #$20	                REP #$20        ; set A long
+.390965		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.390968		5b		tcd		                TCD
+.390969		28		plp		                PLP
+.39096a		68		pla		                PLA             ; end setdp macro
+.39096b		a6 1a		ldx $1a		                LDX CURSORX           ; Get the new column
+.39096d		e8		inx		                INX
+.39096e		a4 1c		ldy $1c		                LDY CURSORY           ; Get the current row
+.390970		e4 0f		cpx $0f		                CPX COLS_VISIBLE      ; Are we off screen?
+.390972		90 0d		bcc $390981	                BCC icsrright_nowrap  ; No: just set the position
+.390974		a2 00 00	ldx #$0000	                LDX #0                ; Yes: move to the first column
+.390977		c8		iny		                INY                   ; And move to the next row
+.390978		c4 13		cpy $13		                CPY LINES_VISIBLE     ; Are we still off screen?
+.39097a		90 05		bcc $390981	                BCC icsrright_nowrap  ; No: just set the position
+.39097c		88		dey		                DEY                   ; Yes: lock to the last row
+.39097d		22 48 0a 39	jsl $390a48	                JSL ISCROLLUP         ; But scroll the screen up
+.390981						icsrright_nowrap
+.390981		22 fc 09 39	jsl $3909fc	                JSL ILOCATE           ; Set the cursor position
+.390985		28		plp		                PLP
+.390986		2b		pld		                PLD
+.390987		68		pla		                PLA
+.390988		7a		ply		                PLY
+.390989		fa		plx		                PLX
+.39098a		6b		rtl		                RTL
+.39098b						ICSRLEFT
+.39098b		da		phx		                PHX
+.39098c		5a		phy		                PHY
+.39098d		48		pha		                PHA
+.39098e		0b		phd		                PHD
+.39098f		08		php		                PHP
+.390990		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390992		48		pha		                PHA             ; begin setdp macro
+.390993		08		php		                PHP
+.390994		c2 20		rep #$20	                REP #$20        ; set A long
+.390996		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.390999		5b		tcd		                TCD
+.39099a		28		plp		                PLP
+.39099b		68		pla		                PLA             ; end setdp macro
+.39099c		a5 1a		lda $1a		                LDA CURSORX
+.39099e		f0 0b		beq $3909ab	                BEQ icsrleft_done_already_zero ; Check that we are not already @ Zero
+.3909a0		a6 1a		ldx $1a		                LDX CURSORX
+.3909a2		ca		dex		                DEX
+.3909a3		86 1a		stx $1a		                STX CURSORX
+.3909a5		a4 1c		ldy $1c		                LDY CURSORY
+.3909a7		22 fc 09 39	jsl $3909fc	                JSL ILOCATE
+.3909ab						icsrleft_done_already_zero
+.3909ab		28		plp		                PLP
+.3909ac		2b		pld		                PLD
+.3909ad		68		pla		                PLA
+.3909ae		7a		ply		                PLY
+.3909af		fa		plx		                PLX
+.3909b0		6b		rtl		                RTL
+.3909b1						ICSRUP
+.3909b1		da		phx		                PHX
+.3909b2		5a		phy		                PHY
+.3909b3		48		pha		                PHA
+.3909b4		0b		phd		                PHD
+.3909b5		08		php		                PHP
+.3909b6		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3909b8		48		pha		                PHA             ; begin setdp macro
+.3909b9		08		php		                PHP
+.3909ba		c2 20		rep #$20	                REP #$20        ; set A long
+.3909bc		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.3909bf		5b		tcd		                TCD
+.3909c0		28		plp		                PLP
+.3909c1		68		pla		                PLA             ; end setdp macro
+.3909c2		a5 1c		lda $1c		                LDA CURSORY
+.3909c4		f0 0b		beq $3909d1	                BEQ isrup_done_already_zero ; Check if we are not already @ Zero
+.3909c6		a4 1c		ldy $1c		                LDY CURSORY
+.3909c8		88		dey		                DEY
+.3909c9		84 1c		sty $1c		                STY CURSORY
+.3909cb		a6 1a		ldx $1a		                LDX CURSORX
+.3909cd		22 fc 09 39	jsl $3909fc	                JSL ILOCATE
+.3909d1						isrup_done_already_zero
+.3909d1		28		plp		                PLP
+.3909d2		2b		pld		                PLD
+.3909d3		68		pla		                PLA
+.3909d4		7a		ply		                PLY
+.3909d5		fa		plx		                PLX
+.3909d6		6b		rtl		                RTL
+.3909d7		da		phx		ICSRDOWN        PHX
+.3909d8		5a		phy		                PHY
+.3909d9		0b		phd		                PHD
+.3909da		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3909dc		48		pha		                PHA             ; begin setdp macro
+.3909dd		08		php		                PHP
+.3909de		c2 20		rep #$20	                REP #$20        ; set A long
+.3909e0		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.3909e3		5b		tcd		                TCD
+.3909e4		28		plp		                PLP
+.3909e5		68		pla		                PLA             ; end setdp macro
+.3909e6		a6 1a		ldx $1a		                LDX CURSORX                 ; Get the current column
+.3909e8		a4 1c		ldy $1c		                LDY CURSORY                 ; Get the new row
+.3909ea		c8		iny		                INY
+.3909eb		c4 13		cpy $13		                CPY LINES_VISIBLE           ; Check to see if we're off screen
+.3909ed		90 05		bcc $3909f4	                BCC icsrdown_noscroll       ; No: go ahead and set the position
+.3909ef		88		dey		                DEY                         ; Yes: go back to the last row
+.3909f0		22 48 0a 39	jsl $390a48	                JSL ISCROLLUP               ; But scroll the screen up
+.3909f4						icsrdown_noscroll
+.3909f4		22 fc 09 39	jsl $3909fc	                JSL ILOCATE                 ; And set the cursor position
+.3909f8		2b		pld		                PLD
+.3909f9		7a		ply		                PLY
+.3909fa		fa		plx		                PLX
+.3909fb		6b		rtl		                RTL
+.3909fc		48		pha		ILOCATE         PHA
+.3909fd		0b		phd		                PHD
+.3909fe		08		php		                PHP
+.3909ff		48		pha		                PHA             ; begin setdp macro
+.390a00		08		php		                PHP
+.390a01		c2 20		rep #$20	                REP #$20        ; set A long
+.390a03		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.390a06		5b		tcd		                TCD
+.390a07		28		plp		                PLP
+.390a08		68		pla		                PLA             ; end setdp macro
+.390a09		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390a0b						ilocate_scroll
+.390a0b		c4 13		cpy $13		                CPY LINES_VISIBLE
+.390a0d		90 07		bcc $390a16	                BCC ilocate_scrolldone
+.390a0f		22 48 0a 39	jsl $390a48	                JSL ISCROLLUP
+.390a13		88		dey		                DEY
+.390a14		80 f5		bra $390a0b	                BRA ilocate_scroll
+.390a16						ilocate_scrolldone
+.390a16		86 1a		stx $1a		                STX CURSORX
+.390a18		84 1c		sty $1c		                STY CURSORY
+.390a1a		a5 0c		lda $0c		                LDA SCREENBEGIN
+.390a1c						ilocate_row
+.390a1c		c0 00 00	cpy #$0000	                CPY #$0
+.390a1f		f0 08		beq $390a29	                BEQ ilocate_right
+.390a21		18		clc		ilocate_down    CLC
+.390a22		65 11		adc $11		                ADC COLS_PER_LINE
+.390a24		88		dey		                DEY
+.390a25		f0 02		beq $390a29	                BEQ ilocate_right
+.390a27		80 f8		bra $390a21	                BRA ilocate_down
+.390a29		18		clc		ilocate_right   CLC
+.390a2a		65 1a		adc $1a		                ADC CURSORX             ; move the cursor right X columns
+.390a2c		85 17		sta $17		                STA CURSORPOS
+.390a2e		a4 1c		ldy $1c		                LDY CURSORY
+.390a30		98		tya		                TYA
+.390a31		8f 16 00 af	sta $af0016	                STA @lVKY_TXT_CURSOR_Y_REG_L  ;Store in Vicky's registers
+.390a35		8a		txa		                TXA
+.390a36		8f 14 00 af	sta $af0014	                STA @lVKY_TXT_CURSOR_X_REG_L  ;Store in Vicky's register
+.390a3a		c2 20		rep #$20	                REP #$20        ; set A long
+.390a3c		18		clc		                CLC
+.390a3d		a5 17		lda $17		                LDA CURSORPOS
+.390a3f		69 00 20	adc #$2000	                ADC #<>(CS_COLOR_MEM_PTR - CS_TEXT_MEM_PTR)
+.390a42		85 1f		sta $1f		                STA COLORPOS
+.390a44		28		plp		ilocate_done    PLP
+.390a45		2b		pld		                PLD
+.390a46		68		pla		                PLA
+.390a47		6b		rtl		                RTL
+.390a48						ISCROLLUP
+.390a48		48		pha		                PHA
+.390a49		da		phx		                PHX
+.390a4a		5a		phy		                PHY
+.390a4b		8b		phb		                PHB
+.390a4c		0b		phd		                PHD
+.390a4d		08		php		                PHP
+.390a4e		48		pha		                PHA             ; begin setdp macro
+.390a4f		08		php		                PHP
+.390a50		c2 20		rep #$20	                REP #$20        ; set A long
+.390a52		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.390a55		5b		tcd		                TCD
+.390a56		28		plp		                PLP
+.390a57		68		pla		                PLA             ; end setdp macro
+.390a58		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390a5a		a5 11		lda $11		                LDA COLS_PER_LINE
+.390a5c		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
+.390a60		a5 13		lda $13		                LDA LINES_VISIBLE
+.390a62		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
+.390a66		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
+.390a6a		85 00		sta $00		                STA TMPPTR1
+.390a6c		18		clc		                CLC
+.390a6d		a9 00 a0	lda #$a000	                LDA #$A000
+.390a70		a8		tay		                TAY
+.390a71		65 11		adc $11		                ADC COLS_PER_LINE
+.390a73		aa		tax		                TAX
+.390a74		a5 00		lda $00		                LDA TMPPTR1
+.390a76		54 af af	mvn $af,$af	                MVN $AF,$AF
+.390a79		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390a7b		18		clc		                CLC
+.390a7c		a9 00 c0	lda #$c000	                LDA #$C000
+.390a7f		a8		tay		                TAY
+.390a80		65 11		adc $11		                ADC COLS_PER_LINE
+.390a82		aa		tax		                TAX
+.390a83		a5 00		lda $00		                LDA TMPPTR1
+.390a85		54 af af	mvn $af,$af	                MVN $AF,$AF
+.390a88		a5 00		lda $00		                LDA TMPPTR1
+.390a8a		48		pha		                PHA
+.390a8b		18		clc		                CLC
+.390a8c		69 00 a0	adc #$a000	                ADC #<>CS_TEXT_MEM_PTR
+.390a8f		85 00		sta $00		                STA TMPPTR1
+.390a91		a0 00 00	ldy #$0000	                LDY #0
+.390a94		a9 20 00	lda #$0020	                LDA #' '
+.390a97		97 00		sta [$00],y	clr_text        STA [TMPPTR1],Y
+.390a99		c8		iny		                INY
+.390a9a		c4 0f		cpy $0f		                CPY COLS_VISIBLE
+.390a9c		d0 f9		bne $390a97	                BNE clr_text
+.390a9e		68		pla		                PLA
+.390a9f		18		clc		                CLC
+.390aa0		69 00 c0	adc #$c000	                ADC #<>CS_COLOR_MEM_PTR
+.390aa3		85 00		sta $00		                STA TMPPTR1
+.390aa5		a0 00 00	ldy #$0000	                LDY #0
+.390aa8		a5 1e		lda $1e		                LDA CURCOLOR
+.390aaa		97 00		sta [$00],y	clr_color       STA [TMPPTR1],Y
+.390aac		c8		iny		                INY
+.390aad		c4 0f		cpy $0f		                CPY COLS_VISIBLE
+.390aaf		d0 f9		bne $390aaa	                BNE clr_color
+.390ab1		28		plp		                PLP
+.390ab2		2b		pld		                PLD
+.390ab3		ab		plb		                PLB
+.390ab4		7a		ply		                PLY
+.390ab5		fa		plx		                PLX
+.390ab6		68		pla		                PLA
+.390ab7		6b		rtl		                RTL
+.390ab8		08		php		IPRINTH         PHP
+.390ab9		48		pha		                PHA
+.390aba						iprinth1
+.390aba		e2 20		sep #$20	                SEP #$20        ; set A short
+.390abc		bd 00 00	lda $0000,x	                LDA #0,b,x      ; Read the value to be printed
+.390abf		4a		lsr a		                LSR
+.390ac0		4a		lsr a		                LSR
+.390ac1		4a		lsr a		                LSR
+.390ac2		4a		lsr a		                LSR
+.390ac3		22 12 0b 39	jsl $390b12	                JSL iprint_digit
+.390ac7		bd 00 00	lda $0000,x	                LDA #0,b,x
+.390aca		22 12 0b 39	jsl $390b12	                JSL iprint_digit
+.390ace		ca		dex		                DEX
+.390acf		88		dey		                DEY
+.390ad0		d0 e8		bne $390aba	                BNE iprinth1
+.390ad2		68		pla		                PLA
+.390ad3		28		plp		                PLP
+.390ad4		6b		rtl		                RTL
+.390ad5						IPRINTAH
+.390ad5		48		pha		                PHA
+.390ad6		08		php		                PHP
+.390ad7		8f 44 02 00	sta $000244	                STA @lCPUA            ; Save A where we can use it multiple times
+.390adb		08		php		                PHP                   ; Get the processor status into A
+.390adc		e2 20		sep #$20	                SEP #$20        ; set A short
+.390ade		c2 10		rep #$10	                REP #$10        ; set X long
+.390ae0		68		pla		                PLA
+.390ae1		29 20		and #$20	                AND #%00100000        ; Is M = 1?
+.390ae3		c9 20		cmp #$20	                CMP #%00100000
+.390ae5		f0 14		beq $390afb	                BEQ eight_bit
+.390ae7		af 46 02 00	lda $000246	                LDA @lCPUA+2          ; Get nibble [15..12]
+.390aeb		4a		lsr a		                LSR A
+.390aec		4a		lsr a		                LSR A
+.390aed		4a		lsr a		                LSR A
+.390aee		4a		lsr a		                LSR A
+.390aef		22 12 0b 39	jsl $390b12	                JSL iprint_digit      ; And print it
+.390af3		af 46 02 00	lda $000246	                LDA @lCPUA+2          ; Get nibble [11..8]
+.390af7		22 12 0b 39	jsl $390b12	                JSL iprint_digit      ; And print it
+.390afb		af 44 02 00	lda $000244	eight_bit       LDA @lCPUA            ; Get nibble [7..4]
+.390aff		4a		lsr a		                LSR A
+.390b00		4a		lsr a		                LSR A
+.390b01		4a		lsr a		                LSR A
+.390b02		4a		lsr a		                LSR A
+.390b03		22 12 0b 39	jsl $390b12	                JSL iprint_digit      ; And print it
+.390b07		af 44 02 00	lda $000244	                LDA @lCPUA            ; Get nibble [3..0]
+.390b0b		22 12 0b 39	jsl $390b12	                JSL iprint_digit      ; And print it
+.390b0f		28		plp		                PLP
+.390b10		68		pla		                PLA
+.390b11		6b		rtl		                RTL
+.390b12		da		phx		iprint_digit    PHX
+.390b13		c2 20		rep #$20	                REP #$20        ; set A long
+.390b15		29 0f 00	and #$000f	                AND #$0F
+.390b18		aa		tax		                TAX
+.390b19		bf 48 76 39	lda $397648,x	                LDA hex_digits,X
+.390b1d		22 7f 07 39	jsl $39077f	                JSL IPUTC       ; Print the digit
+.390b21		fa		plx		                PLX
+.390b22		6b		rtl		                RTL
+.390b23		48		pha		ICLRSCREEN	    PHA
+.390b24		da		phx		                PHX
+.390b25		08		php		                PHP
+.390b26		e2 20		sep #$20	                SEP #$20        ; set A short
+.390b28		c2 10		rep #$10	                REP #$10        ; set X long
+.390b2a		a2 00 00	ldx #$0000	                LDX #$0000		          ; Only Use One Pointer
+.390b2d		a9 20		lda #$20	                LDA #$20		            ; Fill the Entire Screen with Space
+.390b2f		9f 00 a0 af	sta $afa000,x	iclearloop0	STA CS_TEXT_MEM_PTR, x	;
+.390b33		e8		inx		                inx
+.390b34		e0 00 20	cpx #$2000	                cpx #$2000
+.390b37		d0 f6		bne $390b2f	                bne iclearloop0
+.390b39		a2 00 00	ldx #$0000	                LDX	#$0000		          ; Only Use One Pointer
+.390b3c		af 1e 00 00	lda $00001e	                LDA @lCURCOLOR          ; Fill the Color Memory with the current color
+.390b40		9f 00 c0 af	sta $afc000,x	iclearloop1     STA CS_COLOR_MEM_PTR, x	;
+.390b44		e8		inx		                inx
+.390b45		e0 00 20	cpx #$2000	                cpx #$2000
+.390b48		d0 f6		bne $390b40	                bne iclearloop1
+.390b4a		28		plp		                PLP
+.390b4b		fa		plx		                PLX
+.390b4c		68		pla		                PLA
+.390b4d		6b		rtl		                RTL
+.390b4e						COPYBYTES42
+.390b4e		08		php		                PHP
+.390b4f		0b		phd		                PHD
+.390b50		48		pha		                PHA             ; begin setdp macro
+.390b51		08		php		                PHP
+.390b52		c2 20		rep #$20	                REP #$20        ; set A long
+.390b54		a9 00 00	lda #$0000	                LDA #TMPPTR1         ; set DP to page 0
+.390b57		5b		tcd		                TCD
+.390b58		28		plp		                PLP
+.390b59		68		pla		                PLA             ; end setdp macro
+.390b5a		e2 20		sep #$20	                SEP #$20        ; set A short
+.390b5c		c2 10		rep #$10	                REP #$10        ; set X long
+.390b5e		a0 00 00	ldy #$0000	                LDY #0
+.390b61		b7 00		lda [$00],y	copy_loop       LDA [TMPPTR1],Y
+.390b63		97 04		sta [$04],y	                STA [TMPPTR2],Y
+.390b65		c8		iny		                INY
+.390b66		c0 2a 00	cpy #$002a	                CPY #42
+.390b69		d0 f6		bne $390b61	                BNE copy_loop
+.390b6b		2b		pld		                PLD
+.390b6c		28		plp		                PLP
+.390b6d		60		rts		                RTS
+.390b6e						ICOLORFLAG
+.390b6e		48		pha		                PHA
+.390b6f		da		phx		                PHX
+.390b70		5a		phy		                PHY
+.390b71		08		php		                PHP
+.390b72		8b		phb		                PHB
+.390b73		0b		phd		                PHD
+.390b74		48		pha		                PHA             ; begin setdp macro
+.390b75		08		php		                PHP
+.390b76		c2 20		rep #$20	                REP #$20        ; set A long
+.390b78		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.390b7b		5b		tcd		                TCD
+.390b7c		28		plp		                PLP
+.390b7d		68		pla		                PLA             ; end setdp macro
+.390b7e		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390b80		a9 00 c0	lda #$c000	                LDA #<>CS_COLOR_MEM_PTR
+.390b83		85 04		sta $04		                STA TMPPTR2
+.390b85		a9 af 00	lda #$00af	                LDA #`CS_COLOR_MEM_PTR
+.390b88		85 06		sta $06		                STA TMPPTR2+2
+.390b8a		a9 a5 72	lda #$72a5	                LDA #<>greet_clr_line1
+.390b8d		85 00		sta $00		                STA TMPPTR1
+.390b8f		a9 39 00	lda #$0039	                LDA #`greet_clr_line1
+.390b92		85 02		sta $02		                STA TMPPTR1+2
+.390b94		20 4e 0b	jsr $390b4e	                JSR COPYBYTES42
+.390b97		18		clc		                CLC
+.390b98		a5 04		lda $04		                LDA TMPPTR2
+.390b9a		65 11		adc $11		                ADC COLS_PER_LINE
+.390b9c		85 04		sta $04		                STA TMPPTR2
+.390b9e		a9 cf 72	lda #$72cf	                LDA #<>greet_clr_line2
+.390ba1		85 00		sta $00		                STA TMPPTR1
+.390ba3		a9 39 00	lda #$0039	                LDA #`greet_clr_line2
+.390ba6		85 02		sta $02		                STA TMPPTR1+2
+.390ba8		20 4e 0b	jsr $390b4e	                JSR COPYBYTES42
+.390bab		18		clc		                CLC
+.390bac		a5 04		lda $04		                LDA TMPPTR2
+.390bae		65 11		adc $11		                ADC COLS_PER_LINE
+.390bb0		85 04		sta $04		                STA TMPPTR2
+.390bb2		a9 f9 72	lda #$72f9	                LDA #<>greet_clr_line3
+.390bb5		85 00		sta $00		                STA TMPPTR1
+.390bb7		a9 39 00	lda #$0039	                LDA #`greet_clr_line3
+.390bba		85 02		sta $02		                STA TMPPTR1+2
+.390bbc		20 4e 0b	jsr $390b4e	                JSR COPYBYTES42
+.390bbf		18		clc		                CLC
+.390bc0		a5 04		lda $04		                LDA TMPPTR2
+.390bc2		65 11		adc $11		                ADC COLS_PER_LINE
+.390bc4		85 04		sta $04		                STA TMPPTR2
+.390bc6		a9 23 73	lda #$7323	                LDA #<>greet_clr_line4
+.390bc9		85 00		sta $00		                STA TMPPTR1
+.390bcb		a9 39 00	lda #$0039	                LDA #`greet_clr_line4
+.390bce		85 02		sta $02		                STA TMPPTR1+2
+.390bd0		20 4e 0b	jsr $390b4e	                JSR COPYBYTES42
+.390bd3		18		clc		                CLC
+.390bd4		a5 04		lda $04		                LDA TMPPTR2
+.390bd6		65 11		adc $11		                ADC COLS_PER_LINE
+.390bd8		85 04		sta $04		                STA TMPPTR2
+.390bda		a9 4d 73	lda #$734d	                LDA #<>greet_clr_line5
+.390bdd		85 00		sta $00		                STA TMPPTR1
+.390bdf		a9 39 00	lda #$0039	                LDA #`greet_clr_line5
+.390be2		85 02		sta $02		                STA TMPPTR1+2
+.390be4		20 4e 0b	jsr $390b4e	                JSR COPYBYTES42
+.390be7		2b		pld		                PLD
+.390be8		ab		plb		                PLB
+.390be9		28		plp		                PLP
+.390bea		7a		ply		                PLY
+.390beb		fa		plx		                PLX
+.390bec		68		pla		                PLA
+.390bed		6b		rtl		                RTL
+.390bee		0b		phd		IINITCHLUT		  PHD
+.390bef		08		php		                PHP
+.390bf0		48		pha		                PHA
+.390bf1		da		phx		                PHX
+.390bf2		e2 20		sep #$20	                SEP #$20        ; set A short
+.390bf4		e2 10		sep #$10	                SEP #$10        ; set X short
+.390bf6		a2 00		ldx #$00					        LDX	#$00
+.390bf8		bf 77 73 39	lda $397377,x	lutinitloop0	LDA @lfg_color_lut,x		; get Local Data
+.390bfc		9f 40 1f af	sta $af1f40,x	                STA FG_CHAR_LUT_PTR,x	; Write in LUT Memory
+.390c00		e8		inx		                inx
+.390c01		e0 40		cpx #$40	                cpx #$40
+.390c03		d0 f3		bne $390bf8	                bne lutinitloop0
+.390c05		a2 00		ldx #$00	                LDX	#$00
+.390c07		bf b7 73 39	lda $3973b7,x	lutinitloop1	  LDA @lbg_color_lut,x		; get Local Data
+.390c0b		9f 80 1f af	sta $af1f80,x	                STA BG_CHAR_LUT_PTR,x	; Write in LUT Memory
+.390c0f		e8		inx		                INX
+.390c10		e0 40		cpx #$40	                CPX #$40
+.390c12		d0 f3		bne $390c07	                bne lutinitloop1
+.390c14		c2 20		rep #$20	                REP #$20        ; set A long
+.390c16		c2 10		rep #$10	                REP #$10        ; set X long
+.390c18		fa		plx		                PLX
+.390c19		68		pla		                PLA
+.390c1a		28		plp		                PLP
+.390c1b		2b		pld		                PLD
+.390c1c		6b		rtl		                RTL
+.390c1d						IINITGAMMATABLE
+.390c1d		e2 20		sep #$20	                SEP #$20        ; set A short
+.390c1f		c2 10		rep #$10	                REP #$10        ; set X long
+.390c21		a2 00 00	ldx #$0000	                ldx #$0000
+.390c24		bf 00 7b 39	lda $397b00,x	initgammaloop   LDA GAMMA_1_8_Tbl, x
+.390c28		9f 00 40 af	sta $af4000,x	                STA GAMMA_B_LUT_PTR, x
+.390c2c		9f 00 41 af	sta $af4100,x	                STA GAMMA_G_LUT_PTR, x
+.390c30		9f 00 42 af	sta $af4200,x	                STA GAMMA_R_LUT_PTR, x
+.390c34		e8		inx		                inx
+.390c35		e0 00 01	cpx #$0100	                cpx #$0100
+.390c38		d0 ea		bne $390c24	                bne initgammaloop
+.390c3a		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390c3c		6b		rtl		                RTL
+.390c3d		48		pha		IINITALLLUT     PHA
+.390c3e		da		phx		                PHX
+.390c3f		a2 00 00	ldx #$0000	                LDX #$0000
+.390c42		e2 20		sep #$20	                SEP #$20        ; set A short
+.390c44		a9 00		lda #$00	                LDA #$00
+.390c46		85 0a		sta $0a		                STA $0A     ; Temp Location
+.390c48						iinit_lut_loop
+.390c48		86 02		stx $02		                STX $02
+.390c4a		a6 0a		ldx $0a		                LDX $0A
+.390c4c		bf 00 7a 39	lda $397a00,x	                LDA GAMMA_2_2_Tbl, x
+.390c50		49 55		eor #$55	                EOR  #$55
+.390c52		a6 02		ldx $02		                LDX $02
+.390c54		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
+.390c58		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
+.390c5c		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
+.390c60		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
+.390c64		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
+.390c68		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
+.390c6c		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
+.390c70		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
+.390c74		e8		inx		                inx
+.390c75		86 02		stx $02		                STX $02
+.390c77		a6 0a		ldx $0a		                LDX $0A
+.390c79		bf 00 7c 39	lda $397c00,x	                LDA RANDOM_LUT_Tbl, x
+.390c7d		a6 02		ldx $02		                LDX $02
+.390c7f		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
+.390c83		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
+.390c87		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
+.390c8b		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
+.390c8f		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
+.390c93		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
+.390c97		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
+.390c9b		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
+.390c9f		e8		inx		                inx
+.390ca0		86 02		stx $02		                STX $02
+.390ca2		a6 0a		ldx $0a		                LDX $0A
+.390ca4		bf 00 7b 39	lda $397b00,x	                LDA GAMMA_1_8_Tbl, x
+.390ca8		49 aa		eor #$aa	                EOR  #$AA
+.390caa		a6 02		ldx $02		                LDX $02
+.390cac		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
+.390cb0		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
+.390cb4		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
+.390cb8		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
+.390cbc		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
+.390cc0		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
+.390cc4		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
+.390cc8		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
+.390ccc		e8		inx		                inx
+.390ccd		a9 ff		lda #$ff	                LDA #$FF
+.390ccf		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR, x
+.390cd3		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR, x
+.390cd7		9f 00 28 af	sta $af2800,x	                STA @lGRPH_LUT2_PTR, x
+.390cdb		9f 00 2c af	sta $af2c00,x	                STA @lGRPH_LUT3_PTR, x
+.390cdf		9f 00 30 af	sta $af3000,x	                STA @lGRPH_LUT4_PTR, x
+.390ce3		9f 00 34 af	sta $af3400,x	                STA @lGRPH_LUT5_PTR, x
+.390ce7		9f 00 38 af	sta $af3800,x	                STA @lGRPH_LUT6_PTR, x
+.390ceb		9f 00 3c af	sta $af3c00,x	                STA @lGRPH_LUT7_PTR, x
+.390cef		e6 0a		inc $0a		                inc $0A
+.390cf1		e8		inx		                inx
+.390cf2		e0 00 04	cpx #$0400	                cpx #$0400
+.390cf5		f0 03		beq $390cfa	                beq iinit_lut_exit
+.390cf7		82 4e ff	brl $390c48	                brl iinit_lut_loop
+.390cfa						iinit_lut_exit
+.390cfa		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390cfc		fa		plx		                PLX
+.390cfd		68		pla		                PLA
+.390cfe		6b		rtl		                RTL
+.390cff						INITVKYTXTMODE_BYPASS_DPSW
+.390cff		48		pha		                PHA
+.390d00		08		php		                PHP
+.390d01		80 24		bra $390d27	                BRA WeNeed640480Here
+.390d03						IINITVKYTXTMODE
+.390d03		48		pha		                PHA
+.390d04		08		php		                PHP
+.390d05		e2 20		sep #$20	                SEP #$20        ; set A short
+.390d07		af 02 00 af	lda $af0002	                LDA @l GAMMA_CTRL_REG   ; Go Read the Hi-Res DIP Switch Value
+.390d0b		29 10		and #$10	                AND #HIRES_DP_SW_VAL    ; Isolate the Hi-Res Bit ($10) when 1 = 640x480, 0 = 800x600
+.390d0d		c9 10		cmp #$10	                CMP #HIRES_DP_SW_VAL    ; When the Switch is off, the Returned value is 1 (The Pullup is there)
+.390d0f		f0 16		beq $390d27	                BEQ WeNeed640480Here
+.390d11		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H
+.390d15		29 01		and #$01	                AND #Mstr_Ctrl_Video_Mode0
+.390d17		c9 01		cmp #$01	                CMP #Mstr_Ctrl_Video_Mode0
+.390d19		f0 33		beq $390d4e	                BEQ INITVICKYMODEHIRES       ; if we are already in 800x600 Skip to the rest of the Init
+.390d1b		af 01 00 af	lda $af0001	                LDA @L MASTER_CTRL_REG_H
+.390d1f		09 01		ora #$01	                ORA #Mstr_Ctrl_Video_Mode0
+.390d21		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
+.390d25		80 27		bra $390d4e	                BRA INITVICKYMODEHIRES
+.390d27						WeNeed640480Here:
+.390d27		e2 20		sep #$20	                SEP #$20        ; set A short
+.390d29		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H
+.390d2d		29 01		and #$01	                AND #$01
+.390d2f		c9 01		cmp #$01	                CMP #$01
+.390d31		d0 15		bne $390d48	                BNE INITVICKYMODE
+.390d33		a9 00		lda #$00	                LDA #$00
+.390d35		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
+.390d39		ea		nop		                NOP
+.390d3a		ea		nop		                NOP
+.390d3b		ea		nop		                NOP
+.390d3c		ea		nop		                NOP
+.390d3d		ea		nop		                NOP
+.390d3e		a9 01		lda #$01	                LDA #$01
+.390d40		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H
+.390d44		ea		nop		                NOP
+.390d45		ea		nop		                NOP
+.390d46		ea		nop		                NOP
+.390d47		ea		nop		                NOP
+.390d48						INITVICKYMODE
+.390d48		a9 00		lda #$00	                LDA #$00
+.390d4a		8f 01 00 af	sta $af0001	                STA @L MASTER_CTRL_REG_H ; Set it to 640x480 for real
+.390d4e						INITVICKYMODEHIRES
+.390d4e		a9 01		lda #$01	                LDA #Mstr_Ctrl_Text_Mode_En
+.390d50		8f 00 00 af	sta $af0000	                STA @L MASTER_CTRL_REG_L
+.390d54		e2 20		sep #$20	                SEP #$20        ; set A short
+.390d56		a9 00		lda #$00	                LDA #$00
+.390d58		8f 07 00 af	sta $af0007	                STA BORDER_COLOR_R
+.390d5c		a9 54		lda #$54	                LDA #$54
+.390d5e		8f 06 00 af	sta $af0006	                STA BORDER_COLOR_G
+.390d62		a9 54		lda #$54	                LDA #$54
+.390d64		8f 05 00 af	sta $af0005	                STA BORDER_COLOR_B
+.390d68		a9 01		lda #$01	                LDA #Border_Ctrl_Enable           ; Enable the Border
+.390d6a		8f 04 00 af	sta $af0004	                STA BORDER_CTRL_REG
+.390d6e		a9 20		lda #$20	                LDA #32                           ; Set the border to the standard 32 pixels
+.390d70		8f 08 00 af	sta $af0008	                STA BORDER_X_SIZE
+.390d74		8f 09 00 af	sta $af0009	                STA BORDER_Y_SIZE
+.390d78		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390d7a		22 81 0d 39	jsl $390d81	                JSL ISETSIZES                     ; Calculate the size of the text screen
+.390d7e		28		plp		                PLP
+.390d7f		68		pla		                PLA
+.390d80		6b		rtl		                RTL
+.390d81						ISETSIZES
+.390d81		48		pha		                PHA
+.390d82		da		phx		                PHX
+.390d83		5a		phy		                PHY
+.390d84		8b		phb		                PHB
+.390d85		0b		phd		                PHD
+.390d86		08		php		                PHP
+.390d87		48		pha		                PHA             ; begin setdp macro
+.390d88		08		php		                PHP
+.390d89		c2 20		rep #$20	                REP #$20        ; set A long
+.390d8b		a9 00 00	lda #$0000	                LDA #<>BANK0_BEGIN         ; set DP to page 0
+.390d8e		5b		tcd		                TCD
+.390d8f		28		plp		                PLP
+.390d90		68		pla		                PLA             ; end setdp macro
+.390d91		48		pha		                PHA             ; begin setdbr macro
+.390d92		08		php		                PHP
+.390d93		e2 20		sep #$20	                SEP #$20        ; set A short
+.390d95		a9 00		lda #$00	                LDA #0
+.390d97		48		pha		                PHA
+.390d98		ab		plb		                PLB
+.390d99		28		plp		                PLP
+.390d9a		68		pla		                PLA             ; end setdbr macro
+.390d9b		e2 30		sep #$30	                SEP #$30        ; set A&X short
+.390d9d		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H
+.390da1		29 03		and #$03	                AND #$03                    ; Mask off the resolution bits
+.390da3		0a		asl a		                ASL A
+.390da4		aa		tax		                TAX                         ; Index to the col/line count in X
+.390da5		c2 20		rep #$20	                REP #$20        ; set A long
+.390da7		bf 24 0e 39	lda $390e24,x	                LDA cols_by_res,X           ; Get the number of columns
+.390dab		85 11		sta $11		                STA COLS_PER_LINE           ; This is how many columns there are per line in the memory
+.390dad		85 0f		sta $0f		                STA COLS_VISIBLE            ; This is how many would be visible with no border
+.390daf		bf 2c 0e 39	lda $390e2c,x	                LDA lines_by_res,X          ; Get the number of lines
+.390db3		85 15		sta $15		                STA LINES_MAX               ; This is the total number of lines in memory
+.390db5		85 13		sta $13		                STA LINES_VISIBLE           ; This is how many lines would be visible with no border
+.390db7		e2 20		sep #$20	                SEP #$20        ; set A short
+.390db9		af 04 00 af	lda $af0004	                LDA @l BORDER_CTRL_REG      ; Check to see if we have a border
+.390dbd		89 01		bit #$01	                BIT #Border_Ctrl_Enable
+.390dbf		f0 5c		beq $390e1d	                BEQ done                    ; No border... the sizes are correct now
+.390dc1		af 08 00 af	lda $af0008	                LDA @l BORDER_X_SIZE        ; Get the horizontal border width
+.390dc5		29 3f		and #$3f	                AND #$3F
+.390dc7		89 03		bit #$03	                BIT #$03                    ; Check the lower two bits... indicates a partial column is eaten
+.390dc9		d0 04		bne $390dcf	                BNE frac_width
+.390dcb		4a		lsr a		                LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4
+.390dcc		4a		lsr a		                LSR A
+.390dcd		80 03		bra $390dd2	                BRA store_width
+.390dcf		4a		lsr a		frac_width      LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4 + 1
+.390dd0		4a		lsr a		                LSR A                       ; because a column is partially hidden
+.390dd1		1a		inc a		                INC A
+.390dd2		85 00		sta $00		store_width     STA TMPPTR1
+.390dd4		64 01		stz $01		                STZ TMPPTR1+1
+.390dd6		e2 20		sep #$20	                SEP #$20        ; set A short
+.390dd8		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H    ; Check if we're pixel doubling
+.390ddc		89 02		bit #$02	                BIT #Mstr_Ctrl_Video_Mode1
+.390dde		f0 04		beq $390de4	                BEQ adjust_width            ; No... just adjust the width of the screen
+.390de0		c2 20		rep #$20	                REP #$20        ; set A long
+.390de2		46 00		lsr $00		                LSR TMPPTR1                 ; Yes... cut the adjustment in half
+.390de4						adjust_width
+.390de4		c2 20		rep #$20	                REP #$20        ; set A long
+.390de6		38		sec		                SEC
+.390de7		a5 11		lda $11		                LDA COLS_PER_LINE
+.390de9		e5 00		sbc $00		                SBC TMPPTR1
+.390deb		85 0f		sta $0f		                STA COLS_VISIBLE
+.390ded		af 09 00 af	lda $af0009	                LDA @l BORDER_Y_SIZE        ; Get the horizontal border width
+.390df1		29 3f 00	and #$003f	                AND #$3F
+.390df4		89 03 00	bit #$0003	                BIT #$03                    ; Check the lower two bits... indicates a partial column is eaten
+.390df7		d0 04		bne $390dfd	                BNE frac_height
+.390df9		4a		lsr a		                LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4
+.390dfa		4a		lsr a		                LSR A
+.390dfb		80 03		bra $390e00	                BRA store_height
+.390dfd		4a		lsr a		frac_height     LSR A                       ; COLUMNS_HIDDEN := BORDER_X_SIZE / 4 + 1
+.390dfe		4a		lsr a		                LSR A                       ; because a column is partially hidden
+.390dff		1a		inc a		                INC A
+.390e00		85 00		sta $00		store_height    STA TMPPTR1
+.390e02		64 01		stz $01		                STZ TMPPTR1+1
+.390e04		e2 20		sep #$20	                SEP #$20        ; set A short
+.390e06		af 01 00 af	lda $af0001	                LDA @l MASTER_CTRL_REG_H    ; Check if we're pixel doubling
+.390e0a		89 02		bit #$02	                BIT #Mstr_Ctrl_Video_Mode1
+.390e0c		f0 04		beq $390e12	                BEQ adjust_height           ; No... just adjust the height of the screen
+.390e0e		c2 20		rep #$20	                REP #$20        ; set A long
+.390e10		46 00		lsr $00		                LSR TMPPTR1                 ; Yes... cut the adjustment in half
+.390e12						adjust_height
+.390e12		c2 20		rep #$20	                REP #$20        ; set A long
+.390e14		38		sec		                SEC
+.390e15		a5 15		lda $15		                LDA LINES_MAX
+.390e17		e5 00		sbc $00		                SBC TMPPTR1
+.390e19		85 13		sta $13		                STA LINES_VISIBLE
+.390e1b		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390e1d		28		plp		done            PLP
+.390e1e		2b		pld		                PLD
+.390e1f		ab		plb		                PLB
+.390e20		7a		ply		                PLY
+.390e21		fa		plx		                PLX
+.390e22		68		pla		                PLA
+.390e23		6b		rtl		                RTL
+>390e24		50 00 64 00 28 00 32 00		cols_by_res     .word 80,100,40,50
+>390e2c		3c 00 4b 00 1e 00 25 00		lines_by_res    .word 60,75,30,37
+.390e34						IINITVKYGRPMODE
+.390e34		48		pha		                PHA
+.390e35		e2 20		sep #$20	                SEP #$20        ; set A short
+.390e37		a9 00		lda #$00	                LDA #$00          ; Enable Bit-Map and uses LUT0
+.390e39		8f 00 01 af	sta $af0100	                STA @lBM0_CONTROL_REG
+.390e3d		a9 00		lda #$00	                LDA #$00          ;; (L)Load Base Address of where Bitmap begins
+.390e3f		8f 01 01 af	sta $af0101	                STA @lBM0_START_ADDY_L
+.390e43		a9 c0		lda #$c0	                LDA #$C0
+.390e45		8f 02 01 af	sta $af0102	                STA @lBM0_START_ADDY_M
+.390e49		a9 00		lda #$00	                LDA #$00
+.390e4b		8f 03 01 af	sta $af0103	                STA @lBM0_START_ADDY_H ; This address is always base from
+.390e4f		a9 00		lda #$00	                LDA #$00          ; Enable Bit-Map and uses LUT0
+.390e51		8f 08 01 af	sta $af0108	                STA @lBM1_CONTROL_REG
+.390e55		a9 00		lda #$00	                LDA #$00          ;; (L)Load Base Address of where Bitmap begins
+.390e57		8f 09 01 af	sta $af0109	                STA @lBM1_START_ADDY_L
+.390e5b		a9 c0		lda #$c0	                LDA #$C0
+.390e5d		8f 0a 01 af	sta $af010a	                STA @lBM1_START_ADDY_M
+.390e61		a9 00		lda #$00	                LDA #$00
+.390e63		8f 0b 01 af	sta $af010b	                STA @lBM1_START_ADDY_H ; This address is always base from
+.390e67		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390e69		68		pla		                PLA
+.390e6a		6b		rtl		                RTL
+.390e6b						IINITTILEMODE
+.390e6b		6b		rtl		                RTL
+.390e6c		6b		rtl		INOP            RTL
+.390e6d						IINITFONTSET
+.390e6d		48		pha		                PHA
+.390e6e		da		phx		                PHX
+.390e6f		5a		phy		                PHY
+.390e70		8b		phb		                PHB
+.390e71		08		php		                PHP
+.390e72		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390e74		a2 00 00	ldx #$0000	                LDX #<>FONT_4_BANK0         ; Font data to load
+.390e77		a0 00 80	ldy #$8000	                LDY #<>FONT_MEMORY_BANK0    ; Location to load the font data
+.390e7a		a9 00 08	lda #$0800	                LDA #8 * 256                ; Size of a FONT in bytes
+.390e7d		54 af 3f	mvn $3f,$af	                MVN #`FONT_4_BANK0, #`FONT_MEMORY_BANK0
+.390e80		28		plp		                PLP
+.390e81		ab		plb		                PLB
+.390e82		7a		ply		                PLY
+.390e83		fa		plx		                PLX
+.390e84		68		pla		                PLA
+.390e85		6b		rtl		                RTL
+.390e86						INITMOUSEPOINTER
+.390e86		e2 20		sep #$20	                SEP #$20        ; set A short
+.390e88		c2 10		rep #$10	                REP #$10        ; set X long
+.390e8a		a2 00 00	ldx #$0000	                LDX #$0000
+.390e8d						FILL_MOUSE_MARKER
+.390e8d		bf 00 7d 39	lda $397d00,x	                LDA @lMOUSE_POINTER_PTR,X
+.390e91		9f 00 05 af	sta $af0500,x	                STA @lMOUSE_PTR_GRAP0_START, X
+.390e95		e8		inx		                INX
+.390e96		e0 00 01	cpx #$0100	                CPX #$0100
+.390e99		d0 f2		bne $390e8d	                BNE FILL_MOUSE_MARKER
+.390e9b		ea		nop		                nop
+.390e9c		a9 01		lda #$01	                LDA #$01
+.390e9e		8f 00 07 af	sta $af0700	                STA @lMOUSE_PTR_CTRL_REG_L  ; Enable Mouse, Mouse Pointer Graphic Bank 0
+.390ea2		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390ea4		6b		rtl		                RTL
+.390ea5						IINITCURSOR
+.390ea5		e2 20		sep #$20	                SEP #$20        ; set A short
+.390ea7		a9 b1		lda #$b1	                LDA #$B1      ;The Cursor Character will be a Fully Filled Block
+.390ea9		8f 12 00 af	sta $af0012	                STA VKY_TXT_CURSOR_CHAR_REG
+.390ead		a9 03		lda #$03	                LDA #$03      ;Set Cursor Enable And Flash Rate @1Hz
+.390eaf		8f 10 00 af	sta $af0010	                STA VKY_TXT_CURSOR_CTRL_REG ;
+.390eb3		c2 30		rep #$30	                REP #$30        ; set A&X long
+.390eb5		a9 00 00	lda #$0000	                LDA #$0000;
+.390eb8		8f 14 00 af	sta $af0014	                STA VKY_TXT_CURSOR_X_REG_L; // Set the X to Position 1
+.390ebc		a9 06 00	lda #$0006	                LDA #$0006;
+.390ebf		8f 16 00 af	sta $af0016	                STA VKY_TXT_CURSOR_Y_REG_L; // Set the Y to Position 6 (Below)
+.390ec3		6b		rtl		                RTL
+.390ec4		0b		phd		IINITSUPERIO	  PHD
+.390ec5		08		php		                PHP
+.390ec6		48		pha		                PHA
+.390ec7		e2 20		sep #$20	                SEP #$20        ; set A short
+.390ec9		a9 01		lda #$01	                LDA #$01		;Default Value - C256 Doesn't use this IO Pin
+.390ecb		8f 23 11 af	sta $af1123	                STA GP10_REG
+.390ecf		af 23 11 af	lda $af1123	                LDA GP10_REG
+.390ed3		a9 01		lda #$01	                LDA #$01		;Default Value - C256 Doesn't use this IO Pin
+.390ed5		8f 24 11 af	sta $af1124	                STA GP11_REG
+.390ed9		a9 01		lda #$01	                LDA #$01		;Default Value - C256 Doesn't use this IO Pin
+.390edb		8f 25 11 af	sta $af1125	                STA GP12_REG
+.390edf		a9 01		lda #$01	        	LDA #$01		;Default Value - C256 Doesn't use this IO Pin
+.390ee1		8f 26 11 af	sta $af1126	        	STA GP13_REG
+.390ee5		a9 05		lda #$05	        	LDA #$05		;(C256 - POT A Analog BX) Bit[0] = 1, Bit[2] = 1
+.390ee7		8f 27 11 af	sta $af1127	        	STA GP14_REG
+.390eeb		a9 05		lda #$05	        	LDA #$05		;(C256 - POT A Analog BY) Bit[0] = 1, Bit[2] = 1
+.390eed		8f 28 11 af	sta $af1128	        	STA GP15_REG
+.390ef1		a9 05		lda #$05	        	LDA #$05		;(C256 - POT B Analog BX) Bit[0] = 1, Bit[2] = 1
+.390ef3		8f 29 11 af	sta $af1129	        	STA GP16_REG
+.390ef7		a9 05		lda #$05	        	LDA #$05		;(C256 - POT B Analog BY) Bit[0] = 1, Bit[2] = 1
+.390ef9		8f 2a 11 af	sta $af112a	        	STA GP17_REG
+.390efd		a9 00		lda #$00	        	LDA #$00		;(C256 - HEADPHONE MUTE) - Output GPIO - Push-Pull (1 - Headphone On, 0 - HeadPhone Off)
+.390eff		8f 2b 11 af	sta $af112b	        	STA GP20_REG
+.390f03		a9 01		lda #$01			LDA #$01		;Default Value - C256 Doesn't use this IO Pin
+.390f05		8f 2f 11 af	sta $af112f			STA GP24_REG
+.390f09		a9 05		lda #$05			LDA #$05		;(C256 - MIDI IN) Bit[0] = 1, Bit[2] = 1 (Page 132 Manual)
+.390f0b		8f 30 11 af	sta $af1130			STA GP25_REG
+.390f0f		a9 84		lda #$84			LDA #$84		;(C256 - MIDI OUT) Bit[2] = 1, Bit[7] = 1 (Open Drain - To be Checked)
+.390f11		8f 31 11 af	sta $af1131			STA GP26_REG
+.390f15		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 1) Setup as GPIO Input for now
+.390f17		8f 33 11 af	sta $af1133			STA GP30_REG
+.390f1b		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 4) Setup as GPIO Input for now
+.390f1d		8f 34 11 af	sta $af1134			STA GP31_REG
+.390f21		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 3) Setup as GPIO Input for now
+.390f23		8f 35 11 af	sta $af1135			STA GP32_REG
+.390f27		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 6) Setup as GPIO Input for now
+.390f29		8f 36 11 af	sta $af1136			STA GP33_REG
+.390f2d		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 5) Setup as GPIO Input for now
+.390f2f		8f 37 11 af	sta $af1137			STA GP34_REG
+.390f33		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 8) Setup as GPIO Input for now
+.390f35		8f 38 11 af	sta $af1138			STA GP35_REG
+.390f39		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 7) Setup as GPIO Input for now
+.390f3b		8f 39 11 af	sta $af1139			STA GP36_REG
+.390f3f		a9 01		lda #$01			LDA #$01		;Default Value - (C256 - JP1 Fanout Pin 10) Setup as GPIO Input for now
+.390f41		8f 3a 11 af	sta $af113a			STA GP37_REG
+.390f45		a9 01		lda #$01			LDA #$01		;Default Value - C256 Doesn't use this IO Pin
+.390f47		8f 3d 11 af	sta $af113d			STA GP42_REG
+.390f4b		a9 01		lda #$01			LDA #$01		;(C256 - INPUT PLL CLK INTERRUPT) Default Value - Will keep it as an input for now, no real usage for now
+.390f4d		8f 3e 11 af	sta $af113e			STA GP43_REG
+.390f51		a9 05		lda #$05			LDA #$05		;(C256 - UART2 - RI2) - Input - Set Secondary Function
+.390f53		8f 3f 11 af	sta $af113f			STA GP50_REG
+.390f57		a9 05		lda #$05	                LDA #$05		;(C256 - UART2 - DCD2) - Input - Set Secondary Function
+.390f59		8f 40 11 af	sta $af1140	                STA GP51_REG
+.390f5d		a9 05		lda #$05	                LDA #$05		;(C256 - UART2 - RXD2) - Input - Set Secondary Function
+.390f5f		8f 41 11 af	sta $af1141	                STA GP52_REG
+.390f63		a9 04		lda #$04	                LDA #$04		;(C256 - UART2 - TXD2) - Output - Set Secondary Function
+.390f65		8f 42 11 af	sta $af1142	                STA GP53_REG
+.390f69		a9 05		lda #$05	                LDA #$05		;(C256 - UART2 - DSR2) - Input - Set Secondary Function
+.390f6b		8f 43 11 af	sta $af1143	                STA GP54_REG
+.390f6f		a9 04		lda #$04	                LDA #$04		;(C256 - UART2 - RTS2) - Output - Set Secondary Function
+.390f71		8f 44 11 af	sta $af1144	                STA GP55_REG
+.390f75		a9 05		lda #$05	                LDA #$05		;(C256 - UART2 - CTS2) - Input - Set Secondary Function
+.390f77		8f 45 11 af	sta $af1145	                STA GP56_REG
+.390f7b		a9 04		lda #$04	                LDA #$04		;(C256 - UART2 - DTR2) - Output - Set Secondary Function
+.390f7d		8f 46 11 af	sta $af1146	                STA GP57_REG
+.390f81		a9 84		lda #$84	                LDA #$84		;(C256 - LED1) - Open Drain - Output
+.390f83		8f 47 11 af	sta $af1147	                STA GP60_REG
+.390f87		a9 84		lda #$84	                LDA #$84		;(C256 - LED2) - Open Drain - Output
+.390f89		8f 48 11 af	sta $af1148	                STA GP61_REG
+.390f8d		a9 00		lda #$00	                LDA #$00		;GPIO Data Register (GP10..GP17) - Not Used
+.390f8f		8f 4b 11 af	sta $af114b	                STA GP1_REG
+.390f93		a9 01		lda #$01	                LDA #$01		;GPIO Data Register (GP20..GP27) - Bit[0] - Headphone Mute (Enabling it)
+.390f95		8f 4c 11 af	sta $af114c	                STA GP2_REG
+.390f99		a9 00		lda #$00	                LDA #$00		;GPIO Data Register (GP30..GP37) - Since it is in Output mode, nothing to write here.
+.390f9b		8f 4d 11 af	sta $af114d	                STA GP3_REG
+.390f9f		a9 00		lda #$00	                LDA #$00		;GPIO Data Register (GP40..GP47)  - Not Used
+.390fa1		8f 4e 11 af	sta $af114e	                STA GP4_REG
+.390fa5		a9 00		lda #$00	                LDA #$00		;GPIO Data Register (GP50..GP57)  - Not Used
+.390fa7		8f 4f 11 af	sta $af114f	                STA GP5_REG
+.390fab		a9 00		lda #$00	                LDA #$00		;GPIO Data Register (GP60..GP61)  - Not Used
+.390fad		8f 50 11 af	sta $af1150	                STA GP6_REG
+.390fb1		a9 01		lda #$01	                LDA #$01		;LED1 Output - Already setup by Vicky Init Phase, for now, I will leave it alone
+.390fb3		8f 5d 11 af	sta $af115d	                STA LED1_REG
+.390fb7		a9 02		lda #$02	                LDA #$02		;LED2 Output - However, I will setup this one, to make sure the Code works (Full On, when Code was ran)
+.390fb9		8f 5e 11 af	sta $af115e	                STA LED2_REG
+.390fbd		c2 20		rep #$20	                REP #$20        ; set A long
+.390fbf		68		pla		                PLA
+.390fc0		28		plp			        PLP
+.390fc1		2b		pld				PLD
+.390fc2		6b		rtl		                RTL
+.390fc3		0b		phd		IINITKEYBOARD	PHD
+.390fc4		08		php				PHP
+.390fc5		48		pha				PHA
+.390fc6		da		phx				PHX
+.390fc7		e2 20		sep #$20	                SEP #$20        ; set A short
+.390fc9		c2 10		rep #$10	                REP #$10        ; set X long
+.390fcb		18		clc		                CLC
+.390fcc		20 62 10	jsr $391062	                JSR Poll_Inbuf ;
+.390fcf		a9 aa		lda #$aa			LDA #$AA			;Send self test command
+.390fd1		8f 07 18 af	sta $af1807			STA KBD_CMD_BUF
+.390fd5		20 6d 10	jsr $39106d	                JSR Poll_Outbuf ;
+.390fd8		af 03 18 af	lda $af1803	                LDA KBD_OUT_BUF		;Check self test result
+.390fdc		c9 55		cmp #$55	                CMP #$55
+.390fde		f0 03		beq $390fe3	                BEQ	passAAtest
+.390fe0		82 72 00	brl $391055	                BRL initkb_loop_out
+.390fe3						passAAtest
+.390fe3		a9 ab		lda #$ab			LDA #$AB			;Send test Interface command
+.390fe5		8f 07 18 af	sta $af1807	                STA KBD_CMD_BUF
+.390fe9		20 6d 10	jsr $39106d	                JSR Poll_Outbuf ;
+.390fec		af 03 18 af	lda $af1803			LDA KBD_OUT_BUF		;Display Interface test results
+.390ff0		c9 00		cmp #$00			CMP #$00			;Should be 00
+.390ff2		f0 03		beq $390ff7			BEQ	passABtest
+.390ff4		82 5e 00	brl $391055	                BRL initkb_loop_out
+.390ff7						passABtest
+.390ff7		a9 60		lda #$60	                LDA #$60            ; Send Command 0x60 so to Enable Interrupt
+.390ff9		8f 07 18 af	sta $af1807	                STA KBD_CMD_BUF
+.390ffd		20 62 10	jsr $391062	                JSR Poll_Inbuf ;
+.391000		a9 43		lda #$43	                LDA #%01000011      ; Enable Interrupt - Translation from CODE 2 to CODE 1 Scan code is enable
+.391002		8f 03 18 af	sta $af1803	                STA KBD_DATA_BUF
+.391006		20 62 10	jsr $391062	                JSR Poll_Inbuf ;
+.391009		a9 ff		lda #$ff	                LDA #$FF      ; Send Keyboard Reset command
+.39100b		8f 03 18 af	sta $af1803	                STA KBD_DATA_BUF
+.39100f		a2 ff ff	ldx #$ffff	                LDX #$FFFF
+.391012		ca		dex		DLY_LOOP1       DEX
+.391013		ea		nop		                NOP
+.391014		ea		nop		                NOP
+.391015		ea		nop		                NOP
+.391016		ea		nop		                NOP
+.391017		ea		nop		                NOP
+.391018		ea		nop		                NOP
+.391019		ea		nop		                NOP
+.39101a		ea		nop		                NOP
+.39101b		e0 00 00	cpx #$0000	                CPX #$0000
+.39101e		d0 f2		bne $391012	                BNE DLY_LOOP1
+.391020		20 6d 10	jsr $39106d	                JSR Poll_Outbuf ;
+.391023		af 03 18 af	lda $af1803	                LDA KBD_OUT_BUF   ; Read Output Buffer
+.391027						DO_CMD_F4_AGAIN
+.391027		20 62 10	jsr $391062	                JSR Poll_Inbuf ;
+.39102a		a9 f4		lda #$f4					        LDA #$F4			; Enable the Keyboard
+.39102c		8f 03 18 af	sta $af1803					        STA KBD_DATA_BUF
+.391030		20 6d 10	jsr $39106d	                JSR Poll_Outbuf ;
+.391033		af 03 18 af	lda $af1803					        LDA KBD_OUT_BUF		; Clear the Output buffer
+.391037		c9 fa		cmp #$fa	                CMP #$FA
+.391039		d0 ec		bne $391027	                BNE DO_CMD_F4_AGAIN
+.39103b		af 41 01 00	lda $000141	                LDA @lINT_PENDING_REG1  ; Read the Pending Register &
+.39103f		29 01		and #$01	                AND #FNX1_INT00_KBD
+.391041		8f 41 01 00	sta $000141	                STA @lINT_PENDING_REG1  ; Writing it back will clear the Active Bit
+.391045		af 4d 01 00	lda $00014d	                LDA @lINT_MASK_REG1
+.391049		29 fe		and #$fe	                AND #~FNX1_INT00_KBD
+.39104b		8f 4d 01 00	sta $00014d	                STA @lINT_MASK_REG1
+.39104f		a2 73 74	ldx #$7473	                LDX #<>Success_kb_init
+.391052		38		sec		                SEC
+.391053		b0 00		bcs $391055	                BCS InitKbSuccess
+.391055						initkb_loop_out
+.391055		22 5f 07 39	jsl $39075f	InitKbSuccess   JSL IPRINT       ; print Message
+.391059		c2 20		rep #$20	                REP #$20        ; set A long
+.39105b		c2 10		rep #$10	                REP #$10        ; set X long
+.39105d		fa		plx		                PLX
+.39105e		68		pla		                PLA
+.39105f		28		plp						        PLP
+.391060		2b		pld						        PLD
+.391061		6b		rtl		                RTL
+.391062						Poll_Inbuf
+.391062		af 07 18 af	lda $af1807	                LDA STATUS_PORT		; Load Status Byte
+.391066		29 02		and #$02					        AND	#<INPT_BUF_FULL	; Test bit $02 (if 0, Empty)
+.391068		c9 02		cmp #$02					        CMP #<INPT_BUF_FULL
+.39106a		f0 f6		beq $391062					        BEQ Poll_Inbuf
+.39106c		60		rts		                RTS
+.39106d						Poll_Outbuf
+.39106d		af 07 18 af	lda $af1807	                LDA STATUS_PORT
+.391071		29 01		and #$01	                AND #OUT_BUF_FULL ; Test bit $01 (if 1, Full)
+.391073		c9 01		cmp #$01	                CMP #OUT_BUF_FULL
+.391075		d0 f6		bne $39106d	                BNE Poll_Outbuf
+.391077		60		rts		                RTS
+.391078		0b		phd		IINITMOUSE      PHD
+.391079		08		php						        PHP
+.39107a		48		pha						        PHA
+.39107b		da		phx						        PHX
+.39107c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39107e		c2 10		rep #$10	                REP #$10        ; set X long
+.391080		18		clc		                CLC
+.391081		a2 ff ff	ldx #$ffff	                LDX #$FFFF
+.391084						DO_CMD_A9_AGAIN
+.391084		20 62 10	jsr $391062	                JSR Poll_Inbuf
+.391087		a9 a9		lda #$a9	                LDA #$A9          ; Tests second PS2 Channel
+.391089		8f 07 18 af	sta $af1807	                STA KBD_CMD_BUF
+.39108d		20 07 11	jsr $391107	                JSR Poll_Outbuf_Mouse_TimeOut ;
+.391090		af 03 18 af	lda $af1803					        LDA KBD_OUT_BUF		; Clear the Output buffer
+.391094		c9 00		cmp #$00	                CMP #$00
+.391096		d0 ec		bne $391084	                BNE DO_CMD_A9_AGAIN
+.391098		a9 f6		lda #$f6	                LDA #$F6        ;Tell the mouse to use default settings
+.39109a		20 e1 10	jsr $3910e1	                JSR MOUSE_WRITE
+.39109d		20 f4 10	jsr $3910f4	                JSR MOUSE_READ ;***
+.3910a0		a9 e8		lda #$e8	                LDA #$E8
+.3910a2		20 e1 10	jsr $3910e1	                JSR MOUSE_WRITE
+.3910a5		20 f4 10	jsr $3910f4	                JSR MOUSE_READ ;***
+.3910a8		a9 00		lda #$00	                LDA #$00
+.3910aa		20 e1 10	jsr $3910e1	                JSR MOUSE_WRITE
+.3910ad		20 f4 10	jsr $3910f4	                JSR MOUSE_READ ;***
+.3910b0		a9 f4		lda #$f4	                LDA #$F4        ; Enable the Mouse
+.3910b2		20 e1 10	jsr $3910e1	                JSR MOUSE_WRITE
+.3910b5		20 f4 10	jsr $3910f4	                JSR MOUSE_READ ;***
+.3910b8		a9 00		lda #$00	                LDA #$00
+.3910ba		85 e0		sta $e0		                STA MOUSE_PTR
+.3910bc		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0  ; Read the Pending Register &
+.3910c0		29 80		and #$80	                AND #FNX0_INT07_MOUSE
+.3910c2		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0  ; Writing it back will clear the Active Bit
+.3910c6		af 4c 01 00	lda $00014c	                LDA @lINT_MASK_REG0
+.3910ca		29 7f		and #$7f	                AND #~FNX0_INT07_MOUSE
+.3910cc		8f 4c 01 00	sta $00014c	                STA @lINT_MASK_REG0
+.3910d0		c2 10		rep #$10	                REP #$10        ; set X long
+.3910d2		a2 85 74	ldx #$7485	                LDX #<>Success_ms_init
+.3910d5		80 03		bra $3910da	                BRA InitMsSuccess
+.3910d7		a2 bc 74	ldx #$74bc	initms_loop_out LDX #<>Failed_ms_init
+.3910da						InitMsSuccess
+.3910da		c2 20		rep #$20	                REP #$20        ; set A long
+.3910dc		fa		plx		                PLX
+.3910dd		68		pla		                PLA
+.3910de		28		plp				PLP
+.3910df		2b		pld				PLD
+.3910e0		6b		rtl		                RTL
+.3910e1						MOUSE_WRITE
+.3910e1		48		pha		                PHA
+.3910e2		20 62 10	jsr $391062	                JSR Poll_Inbuf    ; Test bit $01 (if 2, Full)
+.3910e5		a9 d4		lda #$d4	                LDA #$D4
+.3910e7		8f 07 18 af	sta $af1807	                STA KBD_CMD_BUF   ; KBD_CMD_BUF		= $AF1064
+.3910eb		20 62 10	jsr $391062	                JSR Poll_Inbuf
+.3910ee		68		pla		                PLA
+.3910ef		8f 03 18 af	sta $af1803	                STA KBD_DATA_BUF  ; KBD_DATA_BUF	= $AF1060
+.3910f3		60		rts		                RTS
+.3910f4						MOUSE_READ
+.3910f4		20 fc 10	jsr $3910fc	                JSR Poll_Outbuf_Mouse   ; Test bit $01 (if 1, Full)
+.3910f7		af 03 18 af	lda $af1803	                LDA KBD_INPT_BUF  ; KBD_INPT_BUF	= $AF1060
+.3910fb		60		rts		                RTS
+.3910fc						Poll_Outbuf_Mouse
+.3910fc		af 07 18 af	lda $af1807	                LDA STATUS_PORT
+.391100		29 01		and #$01	                AND #OUT_BUF_FULL ; Test bit $01 (if 1, Full)
+.391102		c9 01		cmp #$01	                CMP #OUT_BUF_FULL
+.391104		d0 f6		bne $3910fc	                BNE Poll_Outbuf_Mouse
+.391106		60		rts		                RTS
+.391107						Poll_Outbuf_Mouse_TimeOut
+.391107		af 07 18 af	lda $af1807	                LDA STATUS_PORT
+.39110b		29 01		and #$01	                AND #OUT_BUF_FULL ; Test bit $01 (if 1, Full)
+.39110d		c9 01		cmp #$01	                CMP #OUT_BUF_FULL
+.39110f		f0 08		beq $391119	                BEQ Poll_OutbufWeAreDone
+.391111		ca		dex		                DEX
+.391112		e0 00 00	cpx #$0000	                CPX #$0000
+.391115		d0 f0		bne $391107	                BNE Poll_Outbuf_Mouse_TimeOut
+.391117		80 be		bra $3910d7	                BRA initms_loop_out
+.391119						Poll_OutbufWeAreDone:
+.391119		60		rts		                RTS
+.39111a		48		pha		INITRTC         PHA
+.39111b		08		php		                PHP
+.39111c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39111e		a9 00		lda #$00	                LDA #0
+.391120		8f 0b 08 af	sta $af080b	                STA @l RTC_RATES    ; Set watch dog timer and periodic interrupt rates to 0
+.391124		8f 0c 08 af	sta $af080c	                STA @l RTC_ENABLE   ; Disable all the alarms and interrupts
+.391128		af 0e 08 af	lda $af080e	                LDA @lRTC_CTRL      ; Make sure the RTC will continue to tick in battery mode
+.39112c		09 04		ora #$04	                ORA #%00000100
+.39112e		8f 0e 08 af	sta $af080e	                STA @lRTC_CTRL
+.391132		28		plp		                PLP
+.391133		68		pla		                PLA
+.391134		6b		rtl		                RTL
+.391135		48		pha		IINITCODEC      PHA
+.391136		08		php		                PHP
+.391137		c2 20		rep #$20	                REP #$20        ; set A long
+.391139		a9 00 1a	lda #$1a00	                LDA #%0001101000000000     ;R10 - Programming the DAC
+.39113c		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.391140		a9 01 00	lda #$0001	                LDA #$0001
+.391143		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.391147		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.39114a		a9 00 1a	lda #$1a00	                LDA #%0001101000000000     ;R13 - Turn On Headphones
+.39114d		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.391151		a9 01 00	lda #$0001	                LDA #$0001
+.391154		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.391158		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.39115b		a9 1e 2a	lda #$2a1e	                LDA #%0010101000011110       ;R21 - Enable All the Analog In
+.39115e		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.391162		a9 01 00	lda #$0001	                LDA #$0001
+.391165		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.391169		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.39116c		a9 01 23	lda #$2301	                LDA #%0010001100000001      ;R17 - Enable All the Analog In
+.39116f		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.391173		a9 01 00	lda #$0001	                LDA #$0001
+.391176		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.39117a		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.39117d		a9 07 2c	lda #$2c07	                LDA #%0010110000000111      ;R22 - Enable all Analog Out
+.391180		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.391184		a9 01 00	lda #$0001	                LDA #$0001
+.391187		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.39118b		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.39118e		a9 02 14	lda #$1402	                LDA #%0001010000000010      ;R10 - DAC Interface Control
+.391191		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.391195		a9 01 00	lda #$0001	                LDA #$0001
+.391198		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.39119c		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.39119f		a9 02 16	lda #$1602	                LDA #%0001011000000010      ;R11 - ADC Interface Control
+.3911a2		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.3911a6		a9 01 00	lda #$0001	                LDA #$0001
+.3911a9		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.3911ad		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.3911b0		a9 45 18	lda #$1845	                LDA #%0001100_001000101      ;R12 - Master Mode Control
+.3911b3		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.3911b7		a9 01 00	lda #$0001	                LDA #$0001
+.3911ba		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.3911be		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.3911c1		28		plp		                PLP
+.3911c2		68		pla		                PLA
+.3911c3		6b		rtl		                RTL
+.3911c4						IRESETCODEC
+.3911c4		c2 20		rep #$20	                REP #$20        ; set A long
+.3911c6		a9 00 2e	lda #$2e00	                LDA #$2E00      ;R22 - Enable all Analog Out
+.3911c9		8f 00 e9 af	sta $afe900	                STA CODEC_DATA_LO
+.3911cd		a9 01 00	lda #$0001	                LDA #$0001
+.3911d0		8f 02 e9 af	sta $afe902	                STA CODEC_WR_CTRL             ; Execute the Write
+.3911d4		20 d8 11	jsr $3911d8	                JSR CODEC_TRF_FINISHED
+.3911d7		6b		rtl		                RTL
+.3911d8						CODEC_TRF_FINISHED
+.3911d8		e2 20		sep #$20	                SEP #$20        ; set A short
+.3911da		af 02 e9 af	lda $afe902	CODEC_LOOP      LDA CODEC_WR_CTRL
+.3911de		29 01		and #$01	                AND #$01
+.3911e0		c9 01		cmp #$01	                CMP #$01
+.3911e2		f0 f6		beq $3911da	                BEQ CODEC_LOOP
+.3911e4		c2 20		rep #$20	                REP #$20        ; set A long
+.3911e6		60		rts		                RTS
+.3911e7						IBM_FILL_SCREEN
+.3911e7		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3911e9		a9 00 00	lda #$0000	                LDA #$0000
+.3911ec		a2 00 00	ldx #$0000	                LDX #$0000
+.3911ef						BM_FILL_SCREEN_LOOPY
+.3911ef		a0 00 00	ldy #$0000	                LDY #$0000
+.3911f2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3911f4						BM_FILL_SCREEN_LOOPX
+.3911f4		97 48		sta [$48],y	                STA [BMP_PRSE_DST_PTR],Y    ; This is where the Pixel Go, Video Memory
+.3911f6		c8		iny		                INY
+.3911f7		c4 40		cpy $40		                CPY BM_CLEAR_SCRN_X              ; Transfer the First line
+.3911f9		d0 f9		bne $3911f4	                BNE BM_FILL_SCREEN_LOOPX
+.3911fb		20 06 12	jsr $391206	                JSR BM_FILL_COMPUTE_Y_DST
+.3911fe		e8		inx		                INX
+.3911ff		e4 42		cpx $42		                CPX BM_CLEAR_SCRN_Y
+.391201		d0 ec		bne $3911ef	                BNE BM_FILL_SCREEN_LOOPY
+.391203		c2 30		rep #$30	                REP #$30        ; set A&X long
+.391205		6b		rtl		                RTL
+.391206						BM_FILL_COMPUTE_Y_DST
+.391206		c2 20		rep #$20	                REP #$20        ; set A long
+.391208		a5 48		lda $48		                LDA BMP_PRSE_DST_PTR        ; Right now it is set @ $020000 (128K) + File Size
+.39120a		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
+.39120e		a5 4a		lda $4a		                LDA BMP_PRSE_DST_PTR+2      ; Right now it is set @ $020000 (128K)
+.391210		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
+.391214		a9 80 02	lda #$0280	                LDA #$280        ; Right now it is set @ $020000 (128K) + File Size
+.391217		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL
+.39121b		a9 00 00	lda #$0000	                LDA #$0000
+.39121e		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
+.391222		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
+.391226		85 48		sta $48		                STA BMP_PRSE_DST_PTR
+.391228		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
+.39122c		85 4a		sta $4a		                STA BMP_PRSE_DST_PTR+2
+.39122e		a9 00 00	lda #$0000	                LDA #$0000
+.391231		60		rts		                RTS
+.391232						IBMP_PARSER
+.391232		c2 30		rep #$30	                REP #$30        ; set A&X long
+.391234		a0 00 00	ldy #$0000	                LDY #$0000
+.391237		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y
+.391239		c9 42 4d	cmp #$4d42	                CMP #$4D42
+.39123c		f0 03		beq $391241	                BEQ IBMP_PARSER_CONT
+.39123e		82 04 01	brl $391345	                BRL BMP_PARSER_END_WITH_ERROR
+.391241						IBMP_PARSER_CONT
+.391241		a0 02 00	ldy #$0002	                LDY #$0002
+.391244		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; File Size Low Short
+.391246		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL          ; Store in 32Bit Adder (A)
+.39124a		a0 04 00	ldy #$0004	                LDY #$0004
+.39124d		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; File Size High Short
+.39124f		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL          ; Store in 32Bit Adder (A)
+.391253		a9 ff ff	lda #$ffff	                LDA #$FFFF                  ; Store -1 in Adder (B)
+.391256		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL
+.39125a		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
+.39125e		18		clc		                CLC
+.39125f		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
+.391263		85 50		sta $50		                STA BMP_FILE_SIZE
+.391265		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
+.391269		85 52		sta $52		                STA BMP_FILE_SIZE+2
+.39126b		a0 12 00	ldy #$0012	                LDY #$0012
+.39126e		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; The X SIze is 32bits in BMP, but 16bits will suffice
+.391270		85 40		sta $40		                STA BMP_X_SIZE
+.391272		a0 16 00	ldy #$0016	                LDY #$0016
+.391275		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; The X SIze is 32bits in BMP, but 16bits will suffice
+.391277		85 42		sta $42		                STA BMP_Y_SIZE
+.391279		a0 2e 00	ldy #$002e	                LDY #$002E
+.39127c		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; The X SIze is 32bits in BMP, but 16bits will suffice
+.39127e		0a		asl a		                ASL A; Multiply by 2
+.39127f		0a		asl a		                ASL A; Multiply by 2
+.391280		85 4c		sta $4c		                STA BMP_COLOR_PALET         ;
+.391282		e0 00 00	cpx #$0000	                CPX #$0000
+.391285		d0 05		bne $39128c	                BNE BMP_LUT1_PICK
+.391287		20 4d 13	jsr $39134d	                JSR BMP_PARSER_UPDATE_LUT0   ; Go Upload the LUT0
+.39128a		80 08		bra $391294	                BRA DONE_TRANSFER_LUT;
+.39128c						  BMP_LUT1_PICK
+.39128c		e0 01 00	cpx #$0001	                CPX #$0001
+.39128f		d0 03		bne $391294	                BNE BMP_LUT2_PICK
+.391291		20 7d 13	jsr $39137d	                JSR BMP_PARSER_UPDATE_LUT1   ; Go Upload the LUT1
+.391294						  BMP_LUT2_PICK
+.391294						  DONE_TRANSFER_LUT
+.391294		a5 56		lda $56		                LDA BMP_POSITION_Y
+.391296		8f 00 01 00	sta $000100	                STA @lUNSIGNED_MULT_A_LO
+.39129a		a5 4e		lda $4e		                LDA SCRN_X_STRIDE
+.39129c		8f 02 01 00	sta $000102	                STA @lUNSIGNED_MULT_B_LO
+.3912a0		af 04 01 00	lda $000104	                LDA @lUNSIGNED_MULT_AL_LO
+.3912a4		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL          ; Store in 32Bit Adder (A)
+.3912a8		af 06 01 00	lda $000106	                LDA @lUNSIGNED_MULT_AL_LO+2
+.3912ac		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL          ; Store in 32Bit Adder (A)
+.3912b0		a5 54		lda $54		                LDA BMP_POSITION_X
+.3912b2		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL          ; Put the X Position Adder (B)
+.3912b6		a9 00 00	lda #$0000	                LDA #$0000
+.3912b9		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
+.3912bd		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL          ; Put the Results in TEMP
+.3912c1		85 f0		sta $f0		                STA USER_TEMP
+.3912c3		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL          ; Put the Results in TEMP
+.3912c7		85 f2		sta $f2		                STA USER_TEMP+2
+.3912c9		a5 48		lda $48		                LDA BMP_PRSE_DST_PTR
+.3912cb		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL          ; Store in 32Bit Adder (A)
+.3912cf		a5 4a		lda $4a		                LDA BMP_PRSE_DST_PTR+2
+.3912d1		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL          ; Store in 32Bit Adder (A)
+.3912d5		a5 f0		lda $f0		                LDA USER_TEMP
+.3912d7		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL          ; Store in 32Bit Adder (B)
+.3912db		a5 f2		lda $f2		                LDA USER_TEMP+2
+.3912dd		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL          ; Store in 32Bit Adder (B)
+.3912e1		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL          ; Put the Results in BMP_PRSE_DST_PTR
+.3912e5		85 48		sta $48		                STA BMP_PRSE_DST_PTR
+.3912e7		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL          ; Put the Results in BMP_PRSE_DST_PTR
+.3912eb		85 4a		sta $4a		                STA BMP_PRSE_DST_PTR+2
+.3912ed		a5 44		lda $44		                LDA BMP_PRSE_SRC_PTR        ; Right now it is set @ $020000 (128K)
+.3912ef		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
+.3912f3		a5 46		lda $46		                LDA BMP_PRSE_SRC_PTR+2        ; Right now it is set @ $020000 (128K)
+.3912f5		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
+.3912f9		a5 50		lda $50		                LDA BMP_FILE_SIZE
+.3912fb		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL
+.3912ff		a5 52		lda $52		                LDA BMP_FILE_SIZE+2
+.391301		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL
+.391305		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
+.391309		85 44		sta $44		                STA BMP_PRSE_SRC_PTR
+.39130b		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
+.39130f		85 46		sta $46		                STA BMP_PRSE_SRC_PTR+2
+.391311		a5 44		lda $44		                LDA BMP_PRSE_SRC_PTR        ; Right now it is set @ $020000 (128K) + File Size
+.391313		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
+.391317		a5 46		lda $46		                LDA BMP_PRSE_SRC_PTR+2      ; Right now it is set @ $020000 (128K)
+.391319		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
+.39131d		18		clc		                CLC
+.39131e		a5 40		lda $40		                LDA BMP_X_SIZE              ; Load The Size in X of the image and Make it negative
+.391320		49 ff ff	eor #$ffff	                EOR #$FFFF                  ; Inverse all bit
+.391323		69 01 00	adc #$0001	                ADC #$0001                  ; Add 0 ()
+.391326		8f 24 01 00	sta $000124	                STA @lADDER32_B_LL          ; Store the Results in reg B of ADDER32
+.39132a		a9 ff ff	lda #$ffff	                LDA #$FFFF
+.39132d		8f 26 01 00	sta $000126	                STA @lADDER32_B_HL          ; Store in the Reminder of the 32Bits B Register
+.391331		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
+.391335		85 44		sta $44		                STA BMP_PRSE_SRC_PTR
+.391337		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
+.39133b		85 46		sta $46		                STA BMP_PRSE_SRC_PTR+2
+.39133d		20 ad 13	jsr $3913ad	                JSR BMP_PARSER_DMA_SHIT_OUT  ; We are going to start with the slow method
+.391340		a2 09 75	ldx #$7509	                LDX #<>bmp_parser_msg0
+.391343		80 03		bra $391348	                BRA BMP_PARSER_END_NO_ERROR
+.391345						BMP_PARSER_END_WITH_ERROR
+.391345		a2 f5 74	ldx #$74f5	                LDX #<>bmp_parser_err0
+.391348						BMP_PARSER_END_NO_ERROR
+.391348		22 5f 07 39	jsl $39075f	                JSL IPRINT       ; print the first line
+.39134c		6b		rtl		                RTL
+.39134d						BMP_PARSER_UPDATE_LUT0
+.39134d		38		sec		                SEC
+.39134e		a0 7a 00	ldy #$007a	                LDY #$007A
+.391351		a2 00 00	ldx #$0000	                LDX #$0000
+.391354		e2 20		sep #$20	                SEP #$20        ; set A short
+.391356						BMP_PARSER_UPDATE_LOOP
+.391356		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; First Pixel is Red
+.391358		9f 00 20 af	sta $af2000,x	                STA @lGRPH_LUT0_PTR+0, X      ; The look-up Table point to a pixel Blue
+.39135c		c8		iny		                INY
+.39135d		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Second Pixel is Green
+.39135f		9f 01 20 af	sta $af2001,x	                STA @lGRPH_LUT0_PTR+1, X      ; The look-up Table point to a pixel Blue
+.391363		c8		iny		                INY
+.391364		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Third Pixel is Blue
+.391366		9f 02 20 af	sta $af2002,x	                STA @lGRPH_LUT0_PTR+2, X      ; The look-up Table point to a pixel Blue
+.39136a		c8		iny		                INY
+.39136b		a9 80		lda #$80	                LDA #$80
+.39136d		9f 03 20 af	sta $af2003,x	                STA @lGRPH_LUT0_PTR+3, X      ; The look-up Table point to a pixel Blue
+.391371		c8		iny		                INY ; For the Alpha Value, nobody cares
+.391372		e8		inx		                INX
+.391373		e8		inx		                INX
+.391374		e8		inx		                INX
+.391375		e8		inx		                INX
+.391376		e4 4c		cpx $4c		                CPX BMP_COLOR_PALET         ; Apparently sometime there is less than 256 Values in the lookup
+.391378		d0 dc		bne $391356	                BNE BMP_PARSER_UPDATE_LOOP
+.39137a		c2 20		rep #$20	                REP #$20        ; set A long
+.39137c		60		rts		                RTS
+.39137d						BMP_PARSER_UPDATE_LUT1
+.39137d		38		sec		                SEC
+.39137e		a0 36 00	ldy #$0036	                LDY #$0036
+.391381		a2 00 00	ldx #$0000	                LDX #$0000
+.391384		e2 20		sep #$20	                SEP #$20        ; set A short
+.391386						PALETTE_LUT1_LOOP
+.391386		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; First Pixel is Red
+.391388		9f 00 24 af	sta $af2400,x	                STA @lGRPH_LUT1_PTR+0, X      ; The look-up Table point to a pixel Blue
+.39138c		c8		iny		                INY
+.39138d		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Second Pixel is Green
+.39138f		9f 01 24 af	sta $af2401,x	                STA @lGRPH_LUT1_PTR+1, X      ; The look-up Table point to a pixel Blue
+.391393		c8		iny		                INY
+.391394		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Third Pixel is Blue
+.391396		9f 02 24 af	sta $af2402,x	                STA @lGRPH_LUT1_PTR+2, X      ; The look-up Table point to a pixel Blue
+.39139a		c8		iny		                INY
+.39139b		a9 80		lda #$80	                LDA #$80
+.39139d		9f 03 24 af	sta $af2403,x	                STA @lGRPH_LUT1_PTR+3, X      ; The look-up Table point to a pixel Blue
+.3913a1		c8		iny		                INY ; For the Alpha Value, nobody cares
+.3913a2		e8		inx		                INX
+.3913a3		e8		inx		                INX
+.3913a4		e8		inx		                INX
+.3913a5		e8		inx		                INX
+.3913a6		e4 4c		cpx $4c		                CPX BMP_COLOR_PALET         ; Apparently sometime there is less than 256 Values in the lookup
+.3913a8		d0 dc		bne $391386	                BNE PALETTE_LUT1_LOOP
+.3913aa		c2 20		rep #$20	                REP #$20        ; set A long
+.3913ac		60		rts		                RTS
+.3913ad						BMP_PARSER_DMA_SHIT_OUT
+.3913ad		a2 00 00	ldx #$0000	                LDX #$0000
+.3913b0						BMP_PARSER_LOOPY
+.3913b0		a0 00 00	ldy #$0000	                LDY #$0000
+.3913b3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3913b5						BMP_PARSER_LOOPX
+.3913b5		b7 44		lda [$44],y	                LDA [BMP_PRSE_SRC_PTR],Y    ; Load First Pixel Y (will be linear)
+.3913b7		97 48		sta [$48],y	                STA [BMP_PRSE_DST_PTR],Y    ; This is where the Pixel Go, Video Memory
+.3913b9		c8		iny		                INY
+.3913ba		c4 40		cpy $40		                CPY BMP_X_SIZE              ; Transfer the First line
+.3913bc		d0 f7		bne $3913b5	                BNE BMP_PARSER_LOOPX
+.3913be		20 ca 13	jsr $3913ca	                JSR BMP_PARSER_COMPUTE_Y_SRC
+.3913c1		20 e5 13	jsr $3913e5	                JSR BMP_PARSER_COMPUTE_Y_DST
+.3913c4		e8		inx		                INX
+.3913c5		e4 42		cpx $42		                CPX BMP_Y_SIZE
+.3913c7		d0 e7		bne $3913b0	                BNE BMP_PARSER_LOOPY
+.3913c9		60		rts		                RTS
+.3913ca						BMP_PARSER_COMPUTE_Y_SRC
+.3913ca		c2 20		rep #$20	                REP #$20        ; set A long
+.3913cc		a5 44		lda $44		                LDA BMP_PRSE_SRC_PTR        ; Right now it is set @ $020000 (128K) + File Size
+.3913ce		8f 20 01 00	sta $000120	                STA @lADDER32_A_LL
+.3913d2		a5 46		lda $46		                LDA BMP_PRSE_SRC_PTR+2      ; Right now it is set @ $020000 (128K)
+.3913d4		8f 22 01 00	sta $000122	                STA @lADDER32_A_HL
+.3913d8		af 28 01 00	lda $000128	                LDA @lADDER32_R_LL
+.3913dc		85 44		sta $44		                STA BMP_PRSE_SRC_PTR
+.3913de		af 2a 01 00	lda $00012a	                LDA @lADDER32_R_HL
+.3913e2		85 46		sta $46		                STA BMP_PRSE_SRC_PTR+2
+.3913e4		60		rts		                RTS
+.3913e5						BMP_PARSER_COMPUTE_Y_DST
+.3913e5		c2 20		rep #$20	                REP #$20        ; set A long
+.3913e7		18		clc		                CLC
+.3913e8		a5 48		lda $48		                LDA BMP_PRSE_DST_PTR
+.3913ea		65 4e		adc $4e		                ADC SCRN_X_STRIDE        ; In Normal Circumstances, it is 640
+.3913ec		85 48		sta $48		                STA BMP_PRSE_DST_PTR
+.3913ee		a5 4a		lda $4a		                LDA BMP_PRSE_DST_PTR+2
+.3913f0		69 00 00	adc #$0000	                ADC #$0000
+.3913f3		85 4a		sta $4a		                STA BMP_PRSE_DST_PTR+2
+.3913f5		60		rts		                RTS
+.3913f6		ea		nop		ILOOP           NOP
+.3913f7		ea		nop		                NOP
+.3913f8		ea		nop		                NOP
+.3913f9		ea		nop		                NOP
+.3913fa		ea		nop		                NOP
+.3913fb		ea		nop		                NOP
+.3913fc		ea		nop		                NOP
+.3913fd		ea		nop		                NOP
+.3913fe		ea		nop		                NOP
+.3913ff		ea		nop		                NOP
+.391400		6b		rtl		                RTL
+.391401		22 f6 13 39	jsl $3913f6	ILOOP_1         JSL ILOOP
+.391405		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391409		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.39140d		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391411		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391415		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391419		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.39141d		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391421		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391425		22 f6 13 39	jsl $3913f6	                JSL ILOOP
+.391429		6b		rtl		                RTL
+.39142a		22 01 14 39	jsl $391401	ILOOP_1MS       JSL ILOOP_1
+.39142e		6b		rtl		                RTL
+.39142f		e0 00 00	cpx #$0000	ILOOP_MS        CPX #0
+.391432		f0 07		beq $39143b	                BEQ LOOP_MS_END
+.391434		22 2a 14 39	jsl $39142a	                JSL ILOOP_1MS
+.391438		ca		dex		                DEX
+.391439		80 f4		bra $39142f	                BRA ILOOP_MS
+.39143b		6b		rtl		LOOP_MS_END     RTL
+.39143c						IDELAY
+.39143c		8b		phb		                PHB
+.39143d		08		php		                PHP
+.39143e		48		pha		                PHA             ; begin setdbr macro
+.39143f		08		php		                PHP
+.391440		e2 20		sep #$20	                SEP #$20        ; set A short
+.391442		a9 00		lda #$00	                LDA #0
+.391444		48		pha		                PHA
+.391445		ab		plb		                PLB
+.391446		28		plp		                PLP
+.391447		68		pla		                PLA             ; end setdbr macro
+.391448		e2 20		sep #$20	                SEP #$20        ; set A short
+.39144a		a9 00		lda #$00	                LDA #0                      ; Stop the timer if it's running
+.39144c		8f 60 01 00	sta $000160	                STA @l TIMER0_CTRL_REG
+.391450		af 4c 01 00	lda $00014c	                LDA @l INT_MASK_REG0        ; Enable Timer 0 Interrupts
+.391454		29 fb		and #$fb	                AND #~FNX0_INT02_TMR0
+.391456		8f 4c 01 00	sta $00014c	                STA @l INT_MASK_REG0
+.39145a		a9 7f		lda #$7f	                LDA #~TIMER0TRIGGER         ; Clear the timer 0 trigger flag
+.39145c		8d 05 07	sta $0705	                STA @w TIMERFLAGS
+.39145f		a9 00		lda #$00	                LDA #0
+.391461		8f 61 01 00	sta $000161	                STA @l TIMER0_CHARGE_L      ; Clear the comparator for count-down
+.391465		8f 62 01 00	sta $000162	                STA @l TIMER0_CHARGE_M
+.391469		8f 63 01 00	sta $000163	                STA @l TIMER0_CHARGE_H
+.39146d		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39146f		8a		txa		                TXA
+.391470		8f 65 01 00	sta $000165	                STA @l TIMER0_CMP_L         ; Set the number of ticks
+.391474		98		tya		                TYA
+.391475		e2 20		sep #$20	                SEP #$20        ; set A short
+.391477		8f 67 01 00	sta $000167	                STA @l TIMER0_CMP_H
+.39147b		a9 09		lda #$09	                LDA #TMR0_EN | TMR0_UPDWN   ; Enable the timer to count up
+.39147d		8f 60 01 00	sta $000160	                STA @l TIMER0_CTRL_REG
+.391481		a9 80		lda #$80	                LDA #TIMER0TRIGGER          ; Timer zero's trigger flag
+.391483		cb		wai		loop            WAI                         ; Wait for an interrupt
+.391484		1c 05 07	trb $0705	                TRB @w TIMERFLAGS           ; Check for the flag
+.391487		f0 fa		beq $391483	                BEQ loop                    ; Keep checking until it's set
+.391489		a9 00		lda #$00	                LDA #0                      ; Stop the timer
+.39148b		8f 60 01 00	sta $000160	                STA @l TIMER0_CTRL_REG
+.39148f		a9 7f		lda #$7f	                LDA #~TIMER0TRIGGER         ; Clear the timer 0 trigger flag
+.391491		8d 05 07	sta $0705	                STA @w TIMERFLAGS
+.391494		af 4c 01 00	lda $00014c	                LDA @l INT_MASK_REG0        ; Disable Timer 0 Interrupts
+.391498		09 04		ora #$04	                ORA #FNX0_INT02_TMR0
+.39149a		8f 4c 01 00	sta $00014c	                STA @l INT_MASK_REG0
+.39149e		28		plp		                PLP
+.39149f		ab		plb		                PLB
+.3914a0		6b		rtl		                RTL
+.3914a1						SHOW_CREDITS
+.3914a1		48		pha		                PHA
+.3914a2		da		phx		                PHX
+.3914a3		5a		phy		                PHY
+.3914a4		08		php		                PHP
+.3914a5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3914a7		c2 10		rep #$10	                REP #$10        ; set X long
+.3914a9		af 10 00 af	lda $af0010	                LDA @lVKY_TXT_CURSOR_CTRL_REG   ; Disable the cursor
+.3914ad		29 fe		and #$fe	                AND #~Vky_Cursor_Enable
+.3914af		8f 10 00 af	sta $af0010	                STA @lVKY_TXT_CURSOR_CTRL_REG
+.3914b3		a2 00 00	ldx #$0000	                LDX #0
+.3914b6		bf 00 00 3b	lda $3b0000,x	credit_loop     LDA @lCREDITS_TEXT,X            ; Copy a byte of text
+.3914ba		9f 00 a0 af	sta $afa000,x	                STA @lCS_TEXT_MEM_PTR,X
+.3914be		bf 00 18 3b	lda $3b1800,x	                LDA @lCREDITS_COLOR,X           ; Copy a byte of color
+.3914c2		9f 00 c0 af	sta $afc000,x	                STA @lCS_COLOR_MEM_PTR,X
+.3914c6		e8		inx		                INX
+.3914c7		e0 00 20	cpx #$2000	                CPX #128 * 64
+.3914ca		d0 ea		bne $3914b6	                BNE credit_loop
+.3914cc		22 f9 06 39	jsl $3906f9	                JSL IGETCHW                     ; Wait for a keypress
+.3914d0		22 23 0b 39	jsl $390b23	                JSL ICLRSCREEN                  ; Then clear the screen and return
+.3914d4		22 47 09 39	jsl $390947	                JSL ICSRHOME                    ; Move cursor to the home position
+.3914d8		af 10 00 af	lda $af0010	                LDA @lVKY_TXT_CURSOR_CTRL_REG   ; Enable the cursor
+.3914dc		09 01		ora #$01	                ORA #Vky_Cursor_Enable
+.3914de		8f 10 00 af	sta $af0010	                STA @lVKY_TXT_CURSOR_CTRL_REG
+.3914e2		28		plp		                PLP
+.3914e3		7a		ply		                PLY
+.3914e4		fa		plx		                PLX
+.3914e5		68		pla		                PLA
+.3914e6		6b		rtl		                RTL
+.3914e7		00		brk #		ISCINIT         BRK ;
+.3914e8		00		brk #		IIOINIT         BRK ;
+.3914e9		00		brk #		ISETLFS         BRK ; Obsolete (done in OPEN)
+.3914ea		00		brk #		ISETNAM         BRK ; Obsolete (done in OPEN)
+.3914eb		00		brk #		IOPEN           BRK ; Open a channel for reading and/or writing. Use SETLFS and SETNAM to set the channels and filename first.
+.3914ec		00		brk #		ICLOSE          BRK ; Close a channel
+.3914ed		00		brk #		IGETB           BRK ; Get a byte from input channel. Return 0 if no input. Carry is set if no input.
+.3914ee		00		brk #		IGETS           BRK ; Get a string from the input channel. NULL terminates
+.3914ef		00		brk #		IGETLINE        BRK ; Get a line of text from input channel. CR or NULL terminates.
+.3914f0		00		brk #		IGETFIELD       BRK ; Get a field from the input channel. Value in A, CR, or NULL terminates
+.3914f1		00		brk #		ITRIM           BRK ; Removes spaces at beginning and end of string.
+.3914f2		00		brk #		IPRINTC         BRK ; Print character to screen. Handles terminal commands
+.3914f3		00		brk #		IPRINTS         BRK ; Print string to screen. Handles terminal commands
+.3914f4		00		brk #		IPRINTF         BRK ; Print a float value
+.3914f5		00		brk #		IPRINTI         BRK ; Prints integer value in TEMP
+.3914f6		00		brk #		IPRINTAI        BRK ; Prints integer value in A
+.3914f7		00		brk #		IPUSHKEY        BRK ;
+.3914f8		00		brk #		IPUSHKEYS       BRK ;
+.3914f9		00		brk #		ISCRREADLINE    BRK ; Loads the MCMDADDR/BCMDADDR variable with the address of the current line on the screen. This is called when the RETURN key is pressed and is the first step in processing an immediate mode command.
+.3914fa		00		brk #		ISCRGETWORD     BRK ; Read a current word on the screen. A word ends with a space, punctuation (except _), or any control character (value < 32). Loads the address into CMPTEXT_VAL and length into CMPTEXT_LEN variables.
+.3914fb		6b		rtl		IRQHANDLESTUB   RTL
+
+;******  Processing file: src\Libraries/OPL2_Library.asm
+
+
+;******  Processing file: src\Libraries/../Defines/OPL3_def.asm
+
+=$afe600					OPL3_R_BASE               = $AFE600
+=$e600						OPL3_R_BASE_LL            = $E600
+=$00af						OPL3_R_BASE_HL            = $00AF
+=$afe601					OPL3_R_TEST               = $AFE601 ; TEST
+=$afe602					OPL3_R_TIMER1             = $AFE602 ; TIMER-1
+=$afe603					OPL3_R_TIMER2             = $AFE603 ; TIMER-2
+=$afe604					OPL3_R_IRQ                = $AFE604 ;
+=$afe605					OPL3_R_OPL3_MODE          = $AFE605 ; Set bit 0 to 1 if you want to use in OPL3 Mode
+=$afe608					OPL3_R_CSM                = $AFE608 ;
+=$afe620					OPL3_R_AM_VID_EG_KSR_MULT = $AFE620 ; $40..$35 (21 Registers)
+=$afe640					OPL3_R_KSL_TL             = $AFE640;  $40..$55 (21 Registers)
+=$afe660					OPL3_R_AR_DR              = $AFE660;  $60..$75 (21 Registers)
+=$afe680					OPL3_R_SL_RR              = $AFE680;  $80..$95 (21 Registers)
+=$afe6a0					OPL3_R_FNumber            = $AFE6A0;  $A0..$A8
+=$afe6b0					OPL3_R_KON_BLOCK_FNumber  = $AFE6B0;  $B0..$B9
+=$afe6bd					OPL3_R_DPTH_RHYTM         = $AFE6BD;  $BD
+=$afe6c0					OPL3_R_FEEDBACK           = $AFE6C0;  $C0..$C9
+=$afe6e0					OPL3_R_WAVE_SELECT        = $AFE6E0;  $E0..$F5
+=$afe700					OPL3_L_BASE               = $AFE700
+=$e700						OPL3_L_BASE_LL            = $E700
+=$00af						OPL3_L_BASE_HL            = $00AF
+=$afe701					OPL3_L_TEST               = $AFE701 ; TEST
+=$afe702					OPL3_L_TIMER1             = $AFE702 ; TIMER-1
+=$afe703					OPL3_L_TIMER2             = $AFE703 ; TIMER-2
+=$afe704					OPL3_L_IRQ                = $AFE704 ;
+=$afe708					OPL3_L_CSM                = $AFE708 ;
+=$afe720					OPL3_L_AM_VID_EG_KSR_MULT = $AFE720 ; $40..$35 (21 Registers)
+=$afe740					OPL3_L_KSL_TL             = $AFE740;  $40..$55 (21 Registers)
+=$afe760					OPL3_L_AR_DR              = $AFE760;  $60..$75 (21 Registers)
+=$afe780					OPL3_L_SL_RR              = $AFE780;  $80..$95 (21 Registers)
+=$afe7a0					OPL3_L_FNumber            = $AFE7A0;  $A0..$A8
+=$afe7b0					OPL3_L_KON_BLOCK_FNumber  = $AFE7B0;  $B0..$B9
+=$afe7bd					OPL3_L_DPTH_RHYTM         = $AFE7BD;  $BD
+=$afe7c0					OPL3_L_FEEDBACK           = $AFE7C0;  $C0..$C9
+=$afe7e0					OPL3_L_WAVE_SELECT        = $AFE7E0;  $E0..$F5
+=$80						TREMOLO    = $80
+=$40						VIBRATO    = $40
+=$20						SUSTAINING = $20
+=$10						KSR        = $10
+=$0f						MULTIPLIER = $0F
+=$c0						KEY_SCALE  = $C0
+=$3f						OP_LEVEL   = $3F
+=$f0						ATTACK_RT  = $F0
+=$0f						DECAY_RT   = $0F
+=$f0						SUSTAIN_RT = $F0
+=$0f						RELEASE_RT = $0F
+=$0e						FEEDBACK   = $0E
+=$01						ALGORITHM  = $01
+=9						OPL2_NUM_CHANNELS = 9
+=0						OPERATOR1 = 0
+=1						OPERATOR2 = 1
+=0						MODULATOR = 0
+=1						CARRIER = 1
+=0						FREQ_MODULATION = 0
+=1						ADDITIVE_SYNTH  = 1
+=$10						DRUM_BASS   = $10
+=$08						DRUM_SNARE  = $08
+=$04						DRUM_TOM    = $04
+=$02						DRUM_CYMBAL = $02
+=$01						DRUM_HI_HAT = $01
+=1						NOTE_CS =   1
+=2						NOTE_D =    2
+=3						NOTE_DS =   3
+=4						NOTE_E =    4
+=5						NOTE_F =    5
+=6						NOTE_FS =   6
+=7						NOTE_G =    7
+=8						NOTE_GS =   8
+=9						NOTE_A =    9
+=10						NOTE_AS =  10
+=11						NOTE_B =   11
+=12						NOTE_C =   12
+>3914fc		6b 01 81 01 98 01 b0 01		noteFNumbers    .word  $016B, $0181, $0198, $01B0, $01CA, $01E5, $0202, $0220, $0241, $0263, $0287, $02AE
+>391504		ca 01 e5 01 02 02 20 02 41 02 63 02 87 02 ae 02
+>391514		00 01 02 08 09 0a 10 11		registerOffsets_operator0 .byte $00, $01, $02, $08, $09, $0A, $10, $11, $12 ;initializers for operator 1 */
+>39151c		12
+>39151d		03 04 05 0b 0c 0d 13 14		registerOffsets_operator1 .byte $03, $04, $05, $0B, $0C, $0D, $13, $14, $15 ;initializers for operator 2 */
+>391525		15
+>391526		10 13 14 12 15 11		drumOffsets               .byte $10, $13, $14, $12, $15, $11
+>39152c		10 08 04 02 01			drumBits                  .byte $10, $08, $04, $02, $01
+>391531		20 40 60 80 e0 c0		instrumentBaseRegs        .byte $20, $40, $60, $80, $E0, $C0
+
+;******  Return to file: src\Libraries/OPL2_Library.asm
+
+
+;******  Processing file: src\Libraries/OPL2_Instruments.asm
+
+>391537		00 24 4f f2 0b 00 0e 31		INSTRUMENT_ACCORDN    .text $00, $24, $4F, $F2, $0B, $00, $0E, $31, $00, $52, $0B, $00, 'ACCORDN   '
+>39153f		00 52 0b 00 41 43 43 4f 52 44 4e 20 20 20
+>39154d		00 31 43 6e 17 01 02 22		INSTRUMENT_BAGPIPE1   .text $00, $31, $43, $6E, $17, $01, $02, $22, $05, $8B, $0C, $02, 'BAGPIPE1  '
+>391555		05 8b 0c 02 42 41 47 50 49 50 45 31 20 20
+>391563		00 30 00 ff a0 03 00 a3		INSTRUMENT_BAGPIPE2   .text $00, $30, $00, $FF, $A0, $03, $00, $A3, $00, $65, $0B, $02, 'BAGPIPE2  '
+>39156b		00 65 0b 02 42 41 47 50 49 50 45 32 20 20
+>391579		00 31 87 a1 11 00 08 16		INSTRUMENT_BANJO1     .text $00, $31, $87, $A1, $11, $00, $08, $16, $80, $7D, $43, $00, 'BANJO1    '
+>391581		80 7d 43 00 42 41 4e 4a 4f 31 20 20 20 20
+>39158f		00 01 15 25 2f 00 0a 21		INSTRUMENT_BASS1      .text $00, $01, $15, $25, $2F, $00, $0A, $21, $80, $65, $6C, $00, 'BASS1     '
+>391597		80 65 6c 00 42 41 53 53 31 20 20 20 20 20
+>3915a5		00 01 1d f2 ef 00 0a 01		INSTRUMENT_BASS2      .text $00, $01, $1D, $F2, $EF, $00, $0A, $01, $00, $F5, $78, $00, 'BASS2     '
+>3915ad		00 f5 78 00 42 41 53 53 32 20 20 20 20 20
+>3915bb		00 c0 6d f9 01 01 0e 41		INSTRUMENT_BASSHARP   .text $00, $C0, $6D, $F9, $01, $01, $0E, $41, $00, $F2, $73, $00, 'BASSHARP  '
+>3915c3		00 f2 73 00 42 41 53 53 48 41 52 50 20 20
+>3915d1		00 30 c8 d5 19 00 0c 71		INSTRUMENT_BASSOON1   .text $00, $30, $C8, $D5, $19, $00, $0C, $71, $80, $61, $1B, $00, 'BASSOON1  '
+>3915d9		80 61 1b 00 42 41 53 53 4f 4f 4e 31 20 20
+>3915e7		00 c1 4f b1 53 03 06 e0		INSTRUMENT_BASSTRLG   .text $00, $C1, $4F, $B1, $53, $03, $06, $E0, $00, $12, $74, $03, 'BASSTRLG  '
+>3915ef		00 12 74 03 42 41 53 53 54 52 4c 47 20 20
+>3915fd		06 00 0b a8 4c 00 00 00		INSTRUMENT_BDRUM1     .text $06, $00, $0B, $A8, $4C, $00, $00, $00, $00, $00, $00, $00, 'BDRUM1    '
+>391605		00 00 00 00 42 44 52 55 4d 31 20 20 20 20
+>391613		00 64 db ff 01 00 04 3e		INSTRUMENT_BELLONG    .text $00, $64, $DB, $FF, $01, $00, $04, $3E, $C0, $F3, $62, $00, 'BELLONG   '
+>39161b		c0 f3 62 00 42 45 4c 4c 4f 4e 47 20 20 20
+>391629		00 07 4f f2 60 00 08 12		INSTRUMENT_BELLS      .text $00, $07, $4F, $F2, $60, $00, $08, $12, $00, $F2, $72, $00, 'BELLS     '
+>391631		00 f2 72 00 42 45 4c 4c 53 20 20 20 20 20
+>39163f		00 64 db ff 01 00 04 3e		INSTRUMENT_BELSHORT   .text $00, $64, $DB, $FF, $01, $00, $04, $3E, $C0, $F5, $F3, $00, 'BELSHORT  '
+>391647		c0 f5 f3 00 42 45 4c 53 48 4f 52 54 20 20
+>391655		00 20 4b 7b 04 01 0e 21		INSTRUMENT_BNCEBASS   .text $00, $20, $4B, $7B, $04, $01, $0E, $21, $00, $F5, $72, $00, 'BNCEBASS  '
+>39165d		00 f5 72 00 42 4e 43 45 42 41 53 53 20 20
+>39166b		00 21 16 71 ae 00 0e 21		INSTRUMENT_BRASS1     .text $00, $21, $16, $71, $AE, $00, $0E, $21, $00, $81, $9E, $00, 'BRASS1    '
+>391673		00 81 9e 00 42 52 41 53 53 31 20 20 20 20
+>391681		00 30 c5 52 11 00 00 31		INSTRUMENT_CBASSOON   .text $00, $30, $C5, $52, $11, $00, $00, $31, $80, $31, $2E, $00, 'CBASSOON  '
+>391689		80 31 2e 00 43 42 41 53 53 4f 4f 4e 20 20
+>391697		00 33 87 01 10 00 08 14		INSTRUMENT_CELESTA    .text $00, $33, $87, $01, $10, $00, $08, $14, $80, $7D, $33, $00, 'CELESTA   '
+>39169f		80 7d 33 00 43 45 4c 45 53 54 41 20 20 20
+>3916ad		00 32 16 73 24 00 0e 21		INSTRUMENT_CLAR1      .text $00, $32, $16, $73, $24, $00, $0E, $21, $80, $75, $57, $00, 'CLAR1     '
+>3916b5		80 75 57 00 43 4c 41 52 31 20 20 20 20 20
+>3916c3		00 31 1c 41 1b 00 0c 60		INSTRUMENT_CLAR2      .text $00, $31, $1C, $41, $1B, $00, $0C, $60, $80, $42, $3B, $00, 'CLAR2     '
+>3916cb		80 42 3b 00 43 4c 41 52 32 20 20 20 20 20
+>3916d9		00 32 9a 51 1b 00 0c 61		INSTRUMENT_CLARINET   .text $00, $32, $9A, $51, $1B, $00, $0C, $61, $82, $A2, $3B, $00, 'CLARINET  '
+>3916e1		82 a2 3b 00 43 4c 41 52 49 4e 45 54 20 20
+>3916ef		00 11 0d f2 01 00 0a 15		INSTRUMENT_CLAVECIN   .text $00, $11, $0D, $F2, $01, $00, $0A, $15, $0D, $F2, $B1, $00, 'CLAVECIN  '
+>3916f7		0d f2 b1 00 43 4c 41 56 45 43 49 4e 20 20
+>391705		00 00 02 f0 ff 00 06 11		INSTRUMENT_CROMORNE   .text $00, $00, $02, $F0, $FF, $00, $06, $11, $80, $F0, $FF, $00, 'CROMORNE  '
+>39170d		80 f0 ff 00 43 52 4f 4d 4f 52 4e 45 20 20
+>39171b		09 01 00 f5 b5 00 00 00		INSTRUMENT_CYMBAL1    .text $09, $01, $00, $F5, $B5, $00, $00, $00, $00, $00, $00, $00, 'CYMBAL1   '
+>391723		00 00 00 00 43 59 4d 42 41 4c 31 20 20 20
+>391731		00 05 8a f0 7b 00 08 01		INSTRUMENT_ELCLAV1    .text $00, $05, $8A, $F0, $7B, $00, $08, $01, $80, $F4, $7B, $00, 'ELCLAV1   '
+>391739		80 f4 7b 00 45 4c 43 4c 41 56 31 20 20 20
+>391747		00 01 49 f1 53 01 06 11		INSTRUMENT_ELCLAV2    .text $00, $01, $49, $F1, $53, $01, $06, $11, $00, $F1, $74, $02, 'ELCLAV2   '
+>39174f		00 f1 74 02 45 4c 43 4c 41 56 32 20 20 20
+>39175d		00 e0 6d 57 04 01 0e 61		INSTRUMENT_ELECFL     .text $00, $E0, $6D, $57, $04, $01, $0E, $61, $00, $67, $7D, $00, 'ELECFL    '
+>391765		00 67 7d 00 45 4c 45 43 46 4c 20 20 20 20
+>391773		00 13 97 9a 12 02 0e 91		INSTRUMENT_ELECVIBE   .text $00, $13, $97, $9A, $12, $02, $0E, $91, $80, $9B, $11, $00, 'ELECVIBE  '
+>39177b		80 9b 11 00 45 4c 45 43 56 49 42 45 20 20
+>391789		00 f1 01 97 17 00 08 21		INSTRUMENT_ELGUIT1    .text $00, $F1, $01, $97, $17, $00, $08, $21, $0D, $F1, $18, $00, 'ELGUIT1   '
+>391791		0d f1 18 00 45 4c 47 55 49 54 31 20 20 20
+>39179f		00 13 96 ff 21 00 0a 11		INSTRUMENT_ELGUIT2    .text $00, $13, $96, $FF, $21, $00, $0A, $11, $80, $FF, $03, $00, 'ELGUIT2   '
+>3917a7		80 ff 03 00 45 4c 47 55 49 54 32 20 20 20
+>3917b5		00 07 8f 82 7d 00 0c 14		INSTRUMENT_ELGUIT3    .text $00, $07, $8F, $82, $7D, $00, $0C, $14, $80, $82, $7D, $00, 'ELGUIT3   '
+>3917bd		80 82 7d 00 45 4c 47 55 49 54 33 20 20 20
+>3917cb		00 05 8f da 15 00 0a 01		INSTRUMENT_ELGUIT4    .text $00, $05, $8F, $DA, $15, $00, $0A, $01, $80, $F9, $14, $02, 'ELGUIT4   '
+>3917d3		80 f9 14 02 45 4c 47 55 49 54 34 20 20 20
+>3917e1		00 b2 cd 91 2a 02 09 b1		INSTRUMENT_ELORGAN1   .text $00, $B2, $CD, $91, $2A, $02, $09, $B1, $80, $91, $2A, $01, 'ELORGAN1  '
+>3917e9		80 91 2a 01 45 4c 4f 52 47 41 4e 31 20 20
+>3917f7		00 01 4f f1 50 00 06 01		INSTRUMENT_ELPIANO1   .text $00, $01, $4F, $F1, $50, $00, $06, $01, $04, $D2, $7C, $00, 'ELPIANO1  '
+>3917ff		04 d2 7c 00 45 4c 50 49 41 4e 4f 31 20 20
+>39180d		00 02 22 f2 13 00 0e 02		INSTRUMENT_ELPIANO2   .text $00, $02, $22, $F2, $13, $00, $0E, $02, $00, $F5, $43, $00, 'ELPIANO2  '
+>391815		00 f5 43 00 45 4c 50 49 41 4e 4f 32 20 20
+>391823		00 81 63 f3 58 00 00 01		INSTRUMENT_EPIANO1A   .text $00, $81, $63, $F3, $58, $00, $00, $01, $80, $F2, $58, $00, 'EPIANO1A  '
+>39182b		80 f2 58 00 45 50 49 41 4e 4f 31 41 20 20
+>391839		00 07 1f f5 fa 00 0e 01		INSTRUMENT_EPIANO1B   .text $00, $07, $1F, $F5, $FA, $00, $0E, $01, $57, $F5, $FA, $00, 'EPIANO1B  '
+>391841		57 f5 fa 00 45 50 49 41 4e 4f 31 42 20 20
+>39184f		00 21 83 74 17 00 07 a2		INSTRUMENT_FLUTE      .text $00, $21, $83, $74, $17, $00, $07, $A2, $8D, $65, $17, $00, 'FLUTE     '
+>391857		8d 65 17 00 46 4c 55 54 45 20 20 20 20 20
+>391865		00 a1 27 74 8f 00 02 a1		INSTRUMENT_FLUTE1     .text $00, $A1, $27, $74, $8F, $00, $02, $A1, $80, $65, $2A, $00, 'FLUTE1    '
+>39186d		80 65 2a 00 46 4c 55 54 45 31 20 20 20 20
+>39187b		00 e0 ec 6e 8f 00 0e 61		INSTRUMENT_FLUTE2     .text $00, $E0, $EC, $6E, $8F, $00, $0E, $61, $00, $65, $2A, $00, 'FLUTE2    '
+>391883		00 65 2a 00 46 4c 55 54 45 32 20 20 20 20
+>391891		00 21 9f 53 5a 00 0c 21		INSTRUMENT_FRHORN1    .text $00, $21, $9F, $53, $5A, $00, $0C, $21, $80, $AA, $1A, $00, 'FRHORN1   '
+>391899		80 aa 1a 00 46 52 48 4f 52 4e 31 20 20 20
+>3918a7		00 20 8e a5 8f 02 06 21		INSTRUMENT_FRHORN2    .text $00, $20, $8E, $A5, $8F, $02, $06, $21, $00, $36, $3D, $00, 'FRHORN2   '
+>3918af		00 36 3d 00 46 52 48 4f 52 4e 32 20 20 20
+>3918bd		00 f0 18 55 ef 02 00 e0		INSTRUMENT_FSTRP1     .text $00, $F0, $18, $55, $EF, $02, $00, $E0, $80, $87, $1E, $03, 'FSTRP1    '
+>3918c5		80 87 1e 03 46 53 54 52 50 31 20 20 20 20
+>3918d3		00 70 16 55 2f 02 0c e0		INSTRUMENT_FSTRP2     .text $00, $70, $16, $55, $2F, $02, $0C, $E0, $80, $87, $1E, $03, 'FSTRP2    '
+>3918db		80 87 1e 03 46 53 54 52 50 32 20 20 20 20
+>3918e9		00 f1 00 97 13 00 0a 25		INSTRUMENT_FUZGUIT1   .text $00, $F1, $00, $97, $13, $00, $0A, $25, $0D, $F1, $18, $01, 'FUZGUIT1  '
+>3918f1		0d f1 18 01 46 55 5a 47 55 49 54 31 20 20
+>3918ff		00 31 48 f1 53 00 06 32		INSTRUMENT_FUZGUIT2   .text $00, $31, $48, $F1, $53, $00, $06, $32, $00, $F2, $27, $02, 'FUZGUIT2  '
+>391907		00 f2 27 02 46 55 5a 47 55 49 54 32 20 20
+>391915		00 01 11 f2 1f 00 0a 01		INSTRUMENT_GUITAR1    .text $00, $01, $11, $F2, $1F, $00, $0A, $01, $00, $F5, $88, $00, 'GUITAR1   '
+>39191d		00 f5 88 00 47 55 49 54 41 52 31 20 20 20
+>39192b		00 02 29 f5 75 00 00 01		INSTRUMENT_HARP1      .text $00, $02, $29, $F5, $75, $00, $00, $01, $83, $F2, $F3, $00, 'HARP1     '
+>391933		83 f2 f3 00 48 41 52 50 31 20 20 20 20 20
+>391941		00 02 99 f5 55 00 00 01		INSTRUMENT_HARP2      .text $00, $02, $99, $F5, $55, $00, $00, $01, $80, $F6, $53, $00, 'HARP2     '
+>391949		80 f6 53 00 48 41 52 50 32 20 20 20 20 20
+>391957		00 02 57 f5 56 00 00 01		INSTRUMENT_HARP3      .text $00, $02, $57, $F5, $56, $00, $00, $01, $80, $F6, $54, $00, 'HARP3     '
+>39195f		80 f6 54 00 48 41 52 50 33 20 20 20 20 20
+>39196d		00 02 29 f5 75 00 00 01		INSTRUMENT_HARPE1     .text $00, $02, $29, $F5, $75, $00, $00, $01, $03, $F2, $F3, $00, 'HARPE1    '
+>391975		03 f2 f3 00 48 41 52 50 45 31 20 20 20 20
+>391983		00 32 87 a1 10 00 08 16		INSTRUMENT_HARPSI1    .text $00, $32, $87, $A1, $10, $00, $08, $16, $80, $7D, $33, $00, 'HARPSI1   '
+>39198b		80 7d 33 00 48 41 52 50 53 49 31 20 20 20
+>391999		00 33 87 a1 10 00 06 15		INSTRUMENT_HARPSI2    .text $00, $33, $87, $A1, $10, $00, $06, $15, $80, $7D, $43, $00, 'HARPSI2   '
+>3919a1		80 7d 43 00 48 41 52 50 53 49 32 20 20 20
+>3919af		00 35 84 a8 10 00 08 18		INSTRUMENT_HARPSI3    .text $00, $35, $84, $A8, $10, $00, $08, $18, $80, $7D, $33, $00, 'HARPSI3   '
+>3919b7		80 7d 33 00 48 41 52 50 53 49 33 20 20 20
+>3919c5		00 11 0d f2 01 00 0a 15		INSTRUMENT_HARPSI4    .text $00, $11, $0D, $F2, $01, $00, $0A, $15, $0D, $F2, $B1, $00, 'HARPSI4   '
+>3919cd		0d f2 b1 00 48 41 52 50 53 49 34 20 20 20
+>3919db		00 36 87 8a 00 00 08 1a		INSTRUMENT_HARPSI5    .text $00, $36, $87, $8A, $00, $00, $08, $1A, $80, $7F, $33, $00, 'HARPSI5   '
+>3919e3		80 7f 33 00 48 41 52 50 53 49 35 20 20 20
+>3919f1		00 f0 00 1e 11 01 08 e2		INSTRUMENT_HELICPTR   .text $00, $F0, $00, $1E, $11, $01, $08, $E2, $C0, $11, $11, $01, 'HELICPTR  '
+>3919f9		c0 11 11 01 48 45 4c 49 43 50 54 52 20 20
+>391a07		0a 01 00 f7 b5 00 00 00		INSTRUMENT_HIHAT1     .text $0A, $01, $00, $F7, $B5, $00, $00, $00, $00, $00, $00, $00, 'HIHAT1    '
+>391a0f		00 00 00 00 48 49 48 41 54 31 20 20 20 20
+>391a1d		0a 01 03 da 18 00 00 00		INSTRUMENT_HIHAT2     .text $0A, $01, $03, $DA, $18, $00, $00, $00, $00, $00, $00, $00, 'HIHAT2    '
+>391a25		00 00 00 00 48 49 48 41 54 32 20 20 20 20
+>391a33		00 87 4d 78 42 00 0a 94		INSTRUMENT_JAVAICAN   .text $00, $87, $4D, $78, $42, $00, $0A, $94, $00, $85, $54, $00, 'JAVAICAN  '
+>391a3b		00 85 54 00 4a 41 56 41 49 43 41 4e 20 20
+>391a49		00 03 5e 85 51 01 0e 11		INSTRUMENT_JAZZGUIT   .text $00, $03, $5E, $85, $51, $01, $0E, $11, $00, $D2, $71, $00, 'JAZZGUIT  '
+>391a51		00 d2 71 00 4a 41 5a 5a 47 55 49 54 20 20
+>391a5f		00 00 50 f2 70 00 0e 13		INSTRUMENT_JEWSHARP   .text $00, $00, $50, $F2, $70, $00, $0E, $13, $00, $F2, $72, $00, 'JEWSHARP  '
+>391a67		00 f2 72 00 4a 45 57 53 48 41 52 50 20 20
+>391a75		00 00 02 f0 fa 01 06 11		INSTRUMENT_KEYBRD1    .text $00, $00, $02, $F0, $FA, $01, $06, $11, $80, $F2, $FA, $01, 'KEYBRD1   '
+>391a7d		80 f2 fa 01 4b 45 59 42 52 44 31 20 20 20
+>391a8b		00 01 8f f2 bd 00 08 14		INSTRUMENT_KEYBRD2    .text $00, $01, $8F, $F2, $BD, $00, $08, $14, $80, $82, $BD, $00, 'KEYBRD2   '
+>391a93		80 82 bd 00 4b 45 59 42 52 44 32 20 20 20
+>391aa1		00 01 00 f0 f0 00 00 e4		INSTRUMENT_KEYBRD3    .text $00, $01, $00, $F0, $F0, $00, $00, $E4, $03, $F3, $36, $00, 'KEYBRD3   '
+>391aa9		03 f3 36 00 4b 45 59 42 52 44 33 20 20 20
+>391ab7		09 e6 00 25 b5 00 00 00		INSTRUMENT_LASER      .text $09, $E6, $00, $25, $B5, $00, $00, $00, $00, $00, $00, $00, 'LASER     '
+>391abf		00 00 00 00 4c 41 53 45 52 20 20 20 20 20
+>391acd		00 32 44 f8 ff 00 0e 11		INSTRUMENT_LOGDRUM1   .text $00, $32, $44, $F8, $FF, $00, $0E, $11, $00, $F5, $7F, $00, 'LOGDRUM1  '
+>391ad5		00 f5 7f 00 4c 4f 47 44 52 55 4d 31 20 20
+>391ae3		00 05 4e da 25 00 0a 01		INSTRUMENT_MARIMBA1   .text $00, $05, $4E, $DA, $25, $00, $0A, $01, $00, $F9, $15, $00, 'MARIMBA1  '
+>391aeb		00 f9 15 00 4d 41 52 49 4d 42 41 31 20 20
+>391af9		00 85 4e da 15 00 0a 81		INSTRUMENT_MARIMBA2   .text $00, $85, $4E, $DA, $15, $00, $0A, $81, $80, $F9, $13, $00, 'MARIMBA2  '
+>391b01		80 f9 13 00 4d 41 52 49 4d 42 41 32 20 20
+>391b0f		00 30 00 fe 11 01 08 ae		INSTRUMENT_MDRNPHON   .text $00, $30, $00, $FE, $11, $01, $08, $AE, $C0, $F1, $19, $01, 'MDRNPHON  '
+>391b17		c0 f1 19 01 4d 44 52 4e 50 48 4f 4e 20 20
+>391b25		07 0c 00 c8 b6 01 00 00		INSTRUMENT_MLTRDRUM   .text $07, $0C, $00, $C8, $B6, $01, $00, $00, $00, $00, $00, $00, 'MLTRDRUM  '
+>391b2d		00 00 00 00 4d 4c 54 52 44 52 55 4d 20 20
+>391b3b		00 20 90 f5 9e 02 0c 11		INSTRUMENT_MOOGSYNT   .text $00, $20, $90, $F5, $9E, $02, $0C, $11, $00, $F4, $5B, $03, 'MOOGSYNT  '
+>391b43		00 f4 5b 03 4d 4f 4f 47 53 59 4e 54 20 20
+>391b51		00 0e 40 d1 53 00 0e 0e		INSTRUMENT_NOISE1     .text $00, $0E, $40, $D1, $53, $00, $0E, $0E, $00, $F2, $7F, $03, 'NOISE1    '
+>391b59		00 f2 7f 03 4e 4f 49 53 45 31 20 20 20 20
+>391b67		00 b1 c5 6e 17 00 02 22		INSTRUMENT_OBOE1      .text $00, $B1, $C5, $6E, $17, $00, $02, $22, $05, $8B, $0E, $00, 'OBOE1     '
+>391b6f		05 8b 0e 00 4f 42 4f 45 31 20 20 20 20 20
+>391b7d		00 65 d2 81 03 00 02 71		INSTRUMENT_ORGAN1     .text $00, $65, $D2, $81, $03, $00, $02, $71, $80, $F1, $05, $00, 'ORGAN1    '
+>391b85		80 f1 05 00 4f 52 47 41 4e 31 20 20 20 20
+>391b93		00 24 80 ff 0f 00 01 21		INSTRUMENT_ORGAN2     .text $00, $24, $80, $FF, $0F, $00, $01, $21, $80, $FF, $0F, $00, 'ORGAN2    '
+>391b9b		80 ff 0f 00 4f 52 47 41 4e 32 20 20 20 20
+>391ba9		00 03 5b f0 1f 00 0a 01		INSTRUMENT_ORGAN3     .text $00, $03, $5B, $F0, $1F, $00, $0A, $01, $80, $F0, $1F, $00, 'ORGAN3    '
+>391bb1		80 f0 1f 00 4f 52 47 41 4e 33 20 20 20 20
+>391bbf		00 03 5b f0 1f 00 0a 01		INSTRUMENT_ORGAN3A    .text $00, $03, $5B, $F0, $1F, $00, $0A, $01, $8D, $F0, $13, $00, 'ORGAN3A   '
+>391bc7		8d f0 13 00 4f 52 47 41 4e 33 41 20 20 20
+>391bd5		00 03 5b f0 1f 00 0a 01		INSTRUMENT_ORGAN3B    .text $00, $03, $5B, $F0, $1F, $00, $0A, $01, $92, $F0, $12, $00, 'ORGAN3B   '
+>391bdd		92 f0 12 00 4f 52 47 41 4e 33 42 20 20 20
+>391beb		00 0c 00 f8 b5 00 01 00		INSTRUMENT_ORGNPERC   .text $00, $0C, $00, $F8, $B5, $00, $01, $00, $00, $D6, $4F, $00, 'ORGNPERC  '
+>391bf3		00 d6 4f 00 4f 52 47 4e 50 45 52 43 20 20
+>391c01		00 17 4f f2 61 00 08 12		INSTRUMENT_PHONE1     .text $00, $17, $4F, $F2, $61, $00, $08, $12, $08, $F1, $B2, $00, 'PHONE1    '
+>391c09		08 f1 b2 00 50 48 4f 4e 45 31 20 20 20 20
+>391c17		00 17 4f f2 61 00 08 12		INSTRUMENT_PHONE2     .text $00, $17, $4F, $F2, $61, $00, $08, $12, $0A, $F1, $B4, $00, 'PHONE2    '
+>391c1f		0a f1 b4 00 50 48 4f 4e 45 32 20 20 20 20
+>391c2d		00 81 63 f3 58 00 00 01		INSTRUMENT_PIAN1A     .text $00, $81, $63, $F3, $58, $00, $00, $01, $80, $F2, $58, $00, 'PIAN1A    '
+>391c35		80 f2 58 00 50 49 41 4e 31 41 20 20 20 20
+>391c43		00 07 1f f5 fa 00 0e 01		INSTRUMENT_PIAN1B     .text $00, $07, $1F, $F5, $FA, $00, $0E, $01, $26, $F5, $FA, $00, 'PIAN1B    '
+>391c4b		26 f5 fa 00 50 49 41 4e 31 42 20 20 20 20
+>391c59		00 07 1f f5 fa 00 0e 01		INSTRUMENT_PIAN1C     .text $00, $07, $1F, $F5, $FA, $00, $0E, $01, $57, $F5, $FA, $00, 'PIAN1C    '
+>391c61		57 f5 fa 00 50 49 41 4e 31 43 20 20 20 20
+>391c6f		00 03 4f f1 53 00 06 17		INSTRUMENT_PIANO      .text $00, $03, $4F, $F1, $53, $00, $06, $17, $00, $F2, $74, $00, 'PIANO     '
+>391c77		00 f2 74 00 50 49 41 4e 4f 20 20 20 20 20
+>391c85		00 01 4f f1 53 00 06 11		INSTRUMENT_PIANO1     .text $00, $01, $4F, $F1, $53, $00, $06, $11, $00, $D2, $74, $00, 'PIANO1    '
+>391c8d		00 d2 74 00 50 49 41 4e 4f 31 20 20 20 20
+>391c9b		00 41 9d f2 51 00 06 13		INSTRUMENT_PIANO2     .text $00, $41, $9D, $F2, $51, $00, $06, $13, $00, $F2, $F1, $00, 'PIANO2    '
+>391ca3		00 f2 f1 00 50 49 41 4e 4f 32 20 20 20 20
+>391cb1		00 01 4f f1 50 00 06 01		INSTRUMENT_PIANO3     .text $00, $01, $4F, $F1, $50, $00, $06, $01, $04, $D2, $7C, $00, 'PIANO3    '
+>391cb9		04 d2 7c 00 50 49 41 4e 4f 33 20 20 20 20
+>391cc7		00 01 4d f1 60 00 08 11		INSTRUMENT_PIANO4     .text $00, $01, $4D, $F1, $60, $00, $08, $11, $00, $D2, $7B, $00, 'PIANO4    '
+>391ccf		00 d2 7b 00 50 49 41 4e 4f 34 20 20 20 20
+>391cdd		00 03 4f f1 53 00 06 17		INSTRUMENT_PIANOBEL   .text $00, $03, $4F, $F1, $53, $00, $06, $17, $03, $F2, $74, $00, 'PIANOBEL  '
+>391ce5		03 f2 74 00 50 49 41 4e 4f 42 45 4c 20 20
+>391cf3		00 01 cf f1 53 00 02 12		INSTRUMENT_PIANOF     .text $00, $01, $CF, $F1, $53, $00, $02, $12, $00, $F2, $83, $00, 'PIANOF    '
+>391cfb		00 f2 83 00 50 49 41 4e 4f 46 20 20 20 20
+>391d09		00 10 00 75 93 01 00 01		INSTRUMENT_POPBASS1   .text $00, $10, $00, $75, $93, $01, $00, $01, $00, $F5, $82, $01, 'POPBASS1  '
+>391d11		00 f5 82 01 50 4f 50 42 41 53 53 31 20 20
+>391d1f		07 0c 00 c7 b4 00 00 00		INSTRUMENT_RKSNARE1   .text $07, $0C, $00, $C7, $B4, $00, $00, $00, $00, $00, $00, $00, 'RKSNARE1  '
+>391d27		00 00 00 00 52 4b 53 4e 41 52 45 31 20 20
+>391d35		00 01 4f 71 53 00 0a 12		INSTRUMENT_SAX1       .text $00, $01, $4F, $71, $53, $00, $0A, $12, $00, $52, $7C, $00, 'SAX1      '
+>391d3d		00 52 7c 00 53 41 58 31 20 20 20 20 20 20
+>391d4b		00 07 00 f0 f0 00 0e 00		INSTRUMENT_SCRATCH    .text $00, $07, $00, $F0, $F0, $00, $0E, $00, $00, $5C, $DC, $00, 'SCRATCH   '
+>391d53		00 5c dc 00 53 43 52 41 54 43 48 20 20 20
+>391d61		00 07 00 f0 f0 00 0e 00		INSTRUMENT_SCRATCH4   .text $00, $07, $00, $F0, $F0, $00, $0E, $00, $00, $5C, $DC, $00, 'SCRATCH4  '
+>391d69		00 5c dc 00 53 43 52 41 54 43 48 34 20 20
+>391d77		00 06 00 f0 f0 00 0e 00		INSTRUMENT_SDRUM2     .text $00, $06, $00, $F0, $F0, $00, $0E, $00, $00, $F6, $B4, $00, 'SDRUM2    '
+>391d7f		00 f6 b4 00 53 44 52 55 4d 32 20 20 20 20
+>391d8d		00 e4 0e ff 3f 01 00 c0		INSTRUMENT_SHRTVIBE   .text $00, $E4, $0E, $FF, $3F, $01, $00, $C0, $00, $F3, $07, $00, 'SHRTVIBE  '
+>391d95		00 f3 07 00 53 48 52 54 56 49 42 45 20 20
+>391da3		00 01 40 f1 53 00 00 08		INSTRUMENT_SITAR1     .text $00, $01, $40, $F1, $53, $00, $00, $08, $40, $F1, $53, $00, 'SITAR1    '
+>391dab		40 f1 53 00 53 49 54 41 52 31 20 20 20 20
+>391db9		00 01 40 f1 53 00 00 08		INSTRUMENT_SITAR2     .text $00, $01, $40, $F1, $53, $00, $00, $08, $40, $F1, $53, $01, 'SITAR2    '
+>391dc1		40 f1 53 01 53 49 54 41 52 32 20 20 20 20
+>391dcf		00 61 0c 81 03 00 08 71		INSTRUMENT_SNAKEFL    .text $00, $61, $0C, $81, $03, $00, $08, $71, $80, $61, $0C, $00, 'SNAKEFL   '
+>391dd7		80 61 0c 00 53 4e 41 4b 45 46 4c 20 20 20
+>391de5		07 0c 00 f8 b5 00 00 00		INSTRUMENT_SNARE1     .text $07, $0C, $00, $F8, $B5, $00, $00, $00, $00, $00, $00, $00, 'SNARE1    '
+>391ded		00 00 00 00 53 4e 41 52 45 31 20 20 20 20
+>391dfb		00 06 00 f0 f0 00 0e c4		INSTRUMENT_SNRSUST    .text $00, $06, $00, $F0, $F0, $00, $0E, $C4, $03, $C4, $34, $00, 'SNRSUST   '
+>391e03		03 c4 34 00 53 4e 52 53 55 53 54 20 20 20
+>391e11		00 70 1c 51 03 02 0e 20		INSTRUMENT_SOLOVLN    .text $00, $70, $1C, $51, $03, $02, $0E, $20, $00, $54, $67, $02, 'SOLOVLN   '
+>391e19		00 54 67 02 53 4f 4c 4f 56 4c 4e 20 20 20
+>391e27		00 01 46 f1 83 00 06 61		INSTRUMENT_STEELGT1   .text $00, $01, $46, $F1, $83, $00, $06, $61, $03, $31, $86, $00, 'STEELGT1  '
+>391e2f		03 31 86 00 53 54 45 45 4c 47 54 31 20 20
+>391e3d		00 01 47 f1 83 00 06 61		INSTRUMENT_STEELGT2   .text $00, $01, $47, $F1, $83, $00, $06, $61, $03, $91, $86, $00, 'STEELGT2  '
+>391e45		03 91 86 00 53 54 45 45 4c 47 54 32 20 20
+>391e53		00 b1 8b 71 11 00 06 61		INSTRUMENT_STRINGS1   .text $00, $B1, $8B, $71, $11, $00, $06, $61, $40, $42, $15, $01, 'STRINGS1  '
+>391e5b		40 42 15 01 53 54 52 49 4e 47 53 31 20 20
+>391e69		00 e1 4f b1 d3 03 06 21		INSTRUMENT_STRNLONG   .text $00, $E1, $4F, $B1, $D3, $03, $06, $21, $00, $12, $74, $01, 'STRNLONG  '
+>391e71		00 12 74 01 53 54 52 4e 4c 4f 4e 47 20 20
+>391e7f		00 55 97 2a 02 00 00 12		INSTRUMENT_SYN1       .text $00, $55, $97, $2A, $02, $00, $00, $12, $80, $42, $F3, $00, 'SYN1      '
+>391e87		80 42 f3 00 53 59 4e 31 20 20 20 20 20 20
+>391e95		00 13 97 9a 12 00 0e 11		INSTRUMENT_SYN2       .text $00, $13, $97, $9A, $12, $00, $0E, $11, $80, $9B, $14, $00, 'SYN2      '
+>391e9d		80 9b 14 00 53 59 4e 32 20 20 20 20 20 20
+>391eab		00 11 8a f1 11 00 06 01		INSTRUMENT_SYN3       .text $00, $11, $8A, $F1, $11, $00, $06, $01, $40, $F1, $B3, $00, 'SYN3      '
+>391eb3		40 f1 b3 00 53 59 4e 33 20 20 20 20 20 20
+>391ec1		00 21 0d e9 3a 00 0a 22		INSTRUMENT_SYN4       .text $00, $21, $0D, $E9, $3A, $00, $0A, $22, $80, $65, $6C, $00, 'SYN4      '
+>391ec9		80 65 6c 00 53 59 4e 34 20 20 20 20 20 20
+>391ed7		00 01 4f 71 53 00 06 19		INSTRUMENT_SYN5       .text $00, $01, $4F, $71, $53, $00, $06, $19, $00, $52, $7C, $00, 'SYN5      '
+>391edf		00 52 7c 00 53 59 4e 35 20 20 20 20 20 20
+>391eed		00 24 0f 41 7e 00 0a 21		INSTRUMENT_SYN6       .text $00, $24, $0F, $41, $7E, $00, $0A, $21, $00, $F1, $5E, $00, 'SYN6      '
+>391ef5		00 f1 5e 00 53 59 4e 36 20 20 20 20 20 20
+>391f03		00 07 87 f0 05 00 04 01		INSTRUMENT_SYN9       .text $00, $07, $87, $F0, $05, $00, $04, $01, $80, $F0, $05, $00, 'SYN9      '
+>391f0b		80 f0 05 00 53 59 4e 39 20 20 20 20 20 20
+>391f19		00 26 03 e0 f0 00 08 1e		INSTRUMENT_SYNBAL1    .text $00, $26, $03, $E0, $F0, $00, $08, $1E, $00, $FF, $31, $00, 'SYNBAL1   '
+>391f21		00 ff 31 00 53 59 4e 42 41 4c 31 20 20 20
+>391f2f		00 28 03 e0 f0 00 04 13		INSTRUMENT_SYNBAL2    .text $00, $28, $03, $E0, $F0, $00, $04, $13, $00, $E8, $11, $00, 'SYNBAL2   '
+>391f37		00 e8 11 00 53 59 4e 42 41 4c 32 20 20 20
+>391f45		00 30 88 d5 19 00 0c 71		INSTRUMENT_SYNBASS1   .text $00, $30, $88, $D5, $19, $00, $0C, $71, $80, $61, $1B, $00, 'SYNBASS1  '
+>391f4d		80 61 1b 00 53 59 4e 42 41 53 53 31 20 20
+>391f5b		00 81 86 65 01 00 0c 11		INSTRUMENT_SYNBASS2   .text $00, $81, $86, $65, $01, $00, $0C, $11, $00, $32, $74, $00, 'SYNBASS2  '
+>391f63		00 32 74 00 53 59 4e 42 41 53 53 32 20 20
+>391f71		00 81 83 65 05 00 0a 51		INSTRUMENT_SYNBASS4   .text $00, $81, $83, $65, $05, $00, $0A, $51, $00, $32, $74, $00, 'SYNBASS4  '
+>391f79		00 32 74 00 53 59 4e 42 41 53 53 34 20 20
+>391f87		00 06 00 f0 f0 00 0e 00		INSTRUMENT_SYNSNR1    .text $00, $06, $00, $F0, $F0, $00, $0E, $00, $00, $F8, $B6, $00, 'SYNSNR1   '
+>391f8f		00 f8 b6 00 53 59 4e 53 4e 52 31 20 20 20
+>391f9d		00 06 00 f0 f0 00 0e 00		INSTRUMENT_SYNSNR2    .text $00, $06, $00, $F0, $F0, $00, $0E, $00, $00, $F6, $B4, $00, 'SYNSNR2   '
+>391fa5		00 f6 b4 00 53 59 4e 53 4e 52 32 20 20 20
+>391fb3		00 8f 81 ef 01 00 04 01		INSTRUMENT_TINCAN1    .text $00, $8F, $81, $EF, $01, $00, $04, $01, $00, $98, $F1, $00, 'TINCAN1   '
+>391fbb		00 98 f1 00 54 49 4e 43 41 4e 31 20 20 20
+>391fc9		08 04 00 f7 b5 00 00 00		INSTRUMENT_TOM1       .text $08, $04, $00, $F7, $B5, $00, $00, $00, $00, $00, $00, $00, 'TOM1      '
+>391fd1		00 00 00 00 54 4f 4d 31 20 20 20 20 20 20
+>391fdf		08 02 00 c8 97 00 00 00		INSTRUMENT_TOM2       .text $08, $02, $00, $C8, $97, $00, $00, $00, $00, $00, $00, $00, 'TOM2      '
+>391fe7		00 00 00 00 54 4f 4d 32 20 20 20 20 20 20
+>391ff5		00 17 4f f2 61 00 08 12		INSTRUMENT_TRAINBEL   .text $00, $17, $4F, $F2, $61, $00, $08, $12, $08, $F2, $74, $00, 'TRAINBEL  '
+>391ffd		08 f2 74 00 54 52 41 49 4e 42 45 4c 20 20
+>39200b		00 26 03 e0 f0 00 08 1e		INSTRUMENT_TRIANGLE   .text $00, $26, $03, $E0, $F0, $00, $08, $1E, $00, $FF, $31, $00, 'TRIANGLE  '
+>392013		00 ff 31 00 54 52 49 41 4e 47 4c 45 20 20
+>392021		00 b1 1c 41 1f 00 0e 61		INSTRUMENT_TROMB1     .text $00, $B1, $1C, $41, $1F, $00, $0E, $61, $80, $92, $3B, $00, 'TROMB1    '
+>392029		80 92 3b 00 54 52 4f 4d 42 31 20 20 20 20
+>392037		00 21 1c 53 1d 00 0c 61		INSTRUMENT_TROMB2     .text $00, $21, $1C, $53, $1D, $00, $0C, $61, $80, $52, $3B, $00, 'TROMB2    '
+>39203f		80 52 3b 00 54 52 4f 4d 42 32 20 20 20 20
+>39204d		00 31 1c 41 0b 00 0e 61		INSTRUMENT_TRUMPET1   .text $00, $31, $1C, $41, $0B, $00, $0E, $61, $80, $92, $3B, $00, 'TRUMPET1  '
+>392055		80 92 3b 00 54 52 55 4d 50 45 54 31 20 20
+>392063		00 31 1c 23 1d 00 0c 61		INSTRUMENT_TRUMPET2   .text $00, $31, $1C, $23, $1D, $00, $0C, $61, $80, $52, $3B, $00, 'TRUMPET2  '
+>39206b		80 52 3b 00 54 52 55 4d 50 45 54 32 20 20
+>392079		00 31 1c 41 01 00 0e 61		INSTRUMENT_TRUMPET3   .text $00, $31, $1C, $41, $01, $00, $0E, $61, $80, $92, $3B, $00, 'TRUMPET3  '
+>392081		80 92 3b 00 54 52 55 4d 50 45 54 33 20 20
+>39208f		00 31 1c 41 0b 00 0c 61		INSTRUMENT_TRUMPET4   .text $00, $31, $1C, $41, $0B, $00, $0C, $61, $80, $92, $3B, $00, 'TRUMPET4  '
+>392097		80 92 3b 00 54 52 55 4d 50 45 54 34 20 20
+>3920a5		00 21 19 43 8c 00 0c 21		INSTRUMENT_TUBA1      .text $00, $21, $19, $43, $8C, $00, $0C, $21, $80, $85, $2F, $00, 'TUBA1     '
+>3920ad		80 85 2f 00 54 55 42 41 31 20 20 20 20 20
+>3920bb		00 84 53 f5 33 00 06 a0		INSTRUMENT_VIBRA1     .text $00, $84, $53, $F5, $33, $00, $06, $A0, $80, $FD, $25, $00, 'VIBRA1    '
+>3920c3		80 fd 25 00 56 49 42 52 41 31 20 20 20 20
+>3920d1		00 06 73 f6 54 00 00 81		INSTRUMENT_VIBRA2     .text $00, $06, $73, $F6, $54, $00, $00, $81, $03, $F2, $B3, $00, 'VIBRA2    '
+>3920d9		03 f2 b3 00 56 49 42 52 41 32 20 20 20 20
+>3920e7		00 93 97 aa 12 02 0e 91		INSTRUMENT_VIBRA3     .text $00, $93, $97, $AA, $12, $02, $0E, $91, $80, $AC, $21, $00, 'VIBRA3    '
+>3920ef		80 ac 21 00 56 49 42 52 41 33 20 20 20 20
+>3920fd		00 31 1c 51 03 00 0e 61		INSTRUMENT_VIOLIN1    .text $00, $31, $1C, $51, $03, $00, $0E, $61, $80, $54, $67, $00, 'VIOLIN1   '
+>392105		80 54 67 00 56 49 4f 4c 49 4e 31 20 20 20
+>392113		00 e1 88 62 29 00 0c 22		INSTRUMENT_VIOLIN2    .text $00, $E1, $88, $62, $29, $00, $0C, $22, $80, $53, $2C, $00, 'VIOLIN2   '
+>39211b		80 53 2c 00 56 49 4f 4c 49 4e 32 20 20 20
+>392129		00 e1 88 64 29 00 06 22		INSTRUMENT_VIOLIN3    .text $00, $E1, $88, $64, $29, $00, $06, $22, $83, $53, $2C, $00, 'VIOLIN3   '
+>392131		83 53 2c 00 56 49 4f 4c 49 4e 33 20 20 20
+>39213f		00 31 9c f1 f9 00 0e 31		INSTRUMENT_VLNPIZZ1   .text $00, $31, $9C, $F1, $F9, $00, $0E, $31, $80, $F7, $E6, $00, 'VLNPIZZ1  '
+>392147		80 f7 e6 00 56 4c 4e 50 49 5a 5a 31 20 20
+>392155		00 00 02 00 f0 00 0e 14		INSTRUMENT_WAVE       .text $00, $00, $02, $00, $F0, $00, $0E, $14, $80, $1B, $A2, $00, 'WAVE      '
+>39215d		80 1b a2 00 57 41 56 45 20 20 20 20 20 20
+>39216b		00 11 2d c8 2f 00 0c 31		INSTRUMENT_XYLO1      .text $00, $11, $2D, $C8, $2F, $00, $0C, $31, $00, $F5, $F5, $00, 'XYLO1     '
+>392173		00 f5 f5 00 58 59 4c 4f 31 20 20 20 20 20
+>392181		06 2e 00 ff 0f 00 00 00		INSTRUMENT_XYLO2      .text $06, $2E, $00, $FF, $0F, $00, $00, $00, $00, $00, $00, $00, 'XYLO2     '
+>392189		00 00 00 00 58 59 4c 4f 32 20 20 20 20 20
+>392197		00 06 00 ff f0 00 0e c4		INSTRUMENT_XYLO3      .text $00, $06, $00, $FF, $F0, $00, $0E, $C4, $00, $F8, $B5, $00, 'XYLO3     '
+>39219f		00 f8 b5 00 58 59 4c 4f 33 20 20 20 20 20
+
+;******  Return to file: src\Libraries/OPL2_Library.asm
+
+
+;******  Processing file: src\Libraries/OPL2_Midi_Drums.asm
+
+>3921ad		00 3e 00 9f 0f 0f 00 30		DRUMINS_CLAP2         .text $00, $3E, $00, $9F, $0F, $0F, $00, $30, $00, $87, $FA, $00
+>3921b5		00 87 fa 00
+>3921b9		00 01 00 78 97 09 00 02		DRUMINS_SCRATCH1      .text $00, $01, $00, $78, $97, $09, $00, $02, $00, $88, $98, $03
+>3921c1		00 88 98 03
+>3921c5		00 01 00 78 97 09 00 02		DRUMINS_SCRATCH2      .text $00, $01, $00, $78, $97, $09, $00, $02, $00, $88, $98, $03
+>3921cd		00 88 98 03
+>3921d1		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT2      .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
+>3921d9		00 f9 69 00
+>3921dd		00 00 00 f8 6c 01 00 0e		DRUMINS_HIQ           .text $00, $00, $00, $F8, $6C, $01, $00, $0E, $80, $E8, $4A, $00
+>3921e5		80 e8 4a 00
+>3921e9		00 25 1b fa f2 01 00 12		DRUMINS_WOODBLOK      .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
+>3921f1		00 f6 9a 00
+>3921f5		00 06 03 f4 44 00 01 01		DRUMINS_GLOCK         .text $00, $06, $03, $F4, $44, $00, $01, $01, $1B, $F2, $34, $00
+>3921fd		1b f2 34 00
+>392201		00 00 00 f9 f3 05 00 01		DRUMINS_BASS_DR2      .text $00, $00, $00, $F9, $F3, $05, $00, $01, $00, $F7, $8A, $00
+>392209		00 f7 8a 00
+>39220d		00 01 07 fa fd 05 00 01		DRUMINS_BASS_DR1      .text $00, $01, $07, $FA, $FD, $05, $00, $01, $00, $F6, $47, $00
+>392215		00 f6 47 00
+>392219		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT       .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
+>392221		00 f9 69 00
+>392225		00 24 00 ff 00 0f 00 02		DRUMINS_SNARE_AC      .text $00, $24, $00, $FF, $00, $0F, $00, $02, $00, $F7, $A9, $00
+>39222d		00 f7 a9 00
+>392231		00 3e 00 9f 0f 0f 00 30		DRUMINS_CLAP          .text $00, $3E, $00, $9F, $0F, $0F, $00, $30, $00, $87, $FA, $00
+>392239		00 87 fa 00
+>39223d		00 24 00 ff 00 0f 00 02		DRUMINS_SNARE_EL      .text $00, $24, $00, $FF, $00, $0F, $00, $02, $00, $F7, $A9, $00
+>392245		00 f7 a9 00
+>392249		00 06 0a fa 1f 0c 00 11		DRUMINS_LO_TOMS       .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
+>392251		00 f5 f5 00
+>392255		00 2c 00 f2 fe 07 00 02		DRUMINS_HIHAT_CL      .text $00, $2C, $00, $F2, $FE, $07, $00, $02, $06, $B8, $D8, $03
+>39225d		06 b8 d8 03
+>392261		00 06 0a fa 1f 0c 00 11		DRUMINS_HI_TOMS       .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
+>392269		00 f5 f5 00
+>39226d		00 2c 00 f2 fe 07 00 02		DRUMINS_HIHAT_PL      .text $00, $2C, $00, $F2, $FE, $07, $00, $02, $06, $B8, $D8, $03
+>392275		06 b8 d8 03
+>392279		00 06 0a fa 1f 0c 00 11		DRUMINS_LOW_TOM       .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
+>392281		00 f5 f5 00
+>392285		00 2e 00 82 f6 05 00 04		DRUMINS_HIHAT_OP      .text $00, $2E, $00, $82, $F6, $05, $00, $04, $10, $74, $F8, $03
+>39228d		10 74 f8 03
+>392291		00 06 0a fa 1f 0c 00 11		DRUMINS_LTOM_MID      .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
+>392299		00 f5 f5 00
+>39229d		00 06 0a fa 1f 0c 00 11		DRUMINS_HTOM_MID      .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
+>3922a5		00 f5 f5 00
+>3922a9		00 2c 00 9f 00 0f 02 0e		DRUMINS_CRASH         .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
+>3922b1		05 c5 d4 03
+>3922b5		00 06 0a fa 1f 0c 00 11		DRUMINS_TOM_HIGH      .text $00, $06, $0A, $FA, $1F, $0C, $00, $11, $00, $F5, $F5, $00
+>3922bd		00 f5 f5 00
+>3922c1		00 29 10 94 00 0f 00 04		DRUMINS_RIDE_CY       .text $00, $29, $10, $94, $00, $0F, $00, $04, $04, $F9, $44, $03
+>3922c9		04 f9 44 03
+>3922cd		00 2c 00 9f 00 0f 02 0e		DRUMINS_TAMBOUR       .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
+>3922d5		05 c5 d4 03
+>3922d9		00 29 10 94 00 0f 00 04		DRUMINS_CYMBAL        .text $00, $29, $10, $94, $00, $0F, $00, $04, $04, $F9, $44, $03
+>3922e1		04 f9 44 03
+>3922e5		00 2e 09 f5 f1 01 00 06		DRUMINS_TAMBOU2       .text $00, $2E, $09, $F5, $F1, $01, $00, $06, $03, $87, $F7, $03
+>3922ed		03 87 f7 03
+>3922f1		00 2c 00 9f 00 0f 02 0e		DRUMINS_SPLASH        .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
+>3922f9		05 c5 d4 03
+>3922fd		00 37 14 f7 a1 09 01 03		DRUMINS_COWBELL       .text $00, $37, $14, $F7, $A1, $09, $01, $03, $00, $F6, $28, $00
+>392305		00 f6 28 00
+>392309		00 2c 00 9f 00 0f 02 0e		DRUMINS_CRASH2        .text $00, $2C, $00, $9F, $00, $0F, $02, $0E, $05, $C5, $D4, $03
+>392311		05 c5 d4 03
+>392315		00 80 00 ff 00 0d 01 00		DRUMINS_VIBRASLA      .text $00, $80, $00, $FF, $00, $0D, $01, $00, $00, $F5, $F7, $01
+>39231d		00 f5 f7 01
+>392321		00 29 10 94 00 0f 00 04		DRUMINS_RIDE2         .text $00, $29, $10, $94, $00, $0F, $00, $04, $04, $F9, $44, $03
+>392329		04 f9 44 03
+>39232d		00 25 c4 fa fa 01 00 03		DRUMINS_HI_BONGO      .text $00, $25, $C4, $FA, $FA, $01, $00, $03, $00, $99, $F9, $00
+>392335		00 99 f9 00
+>392339		00 21 03 fb fa 01 01 02		DRUMINS_LO_BONGO      .text $00, $21, $03, $FB, $FA, $01, $01, $02, $00, $A8, $F7, $00
+>392341		00 a8 f7 00
+>392345		00 25 c4 fa fa 01 00 03		DRUMINS_MUTECONG      .text $00, $25, $C4, $FA, $FA, $01, $00, $03, $00, $99, $F9, $00
+>39234d		00 99 f9 00
+>392351		00 24 18 f9 fa 0f 02 03		DRUMINS_OPENCONG      .text $00, $24, $18, $F9, $FA, $0F, $02, $03, $00, $A6, $F6, $00
+>392359		00 a6 f6 00
+>39235d		00 24 18 f9 fa 0f 02 03		DRUMINS_LOWCONGA      .text $00, $24, $18, $F9, $FA, $0F, $02, $03, $00, $A6, $F6, $00
+>392365		00 a6 f6 00
+>392369		00 05 14 f5 f5 07 02 03		DRUMINS_HI_TIMBA      .text $00, $05, $14, $F5, $F5, $07, $02, $03, $00, $F6, $36, $02
+>392371		00 f6 36 02
+>392375		00 05 14 f5 f5 07 02 03		DRUMINS_LO_TIMBA      .text $00, $05, $14, $F5, $F5, $07, $02, $03, $00, $F6, $36, $02
+>39237d		00 f6 36 02
+>392381		00 1c 0c f9 31 0f 01 15		DRUMINS_HI_AGOGO      .text $00, $1C, $0C, $F9, $31, $0F, $01, $15, $00, $96, $E8, $01
+>392389		00 96 e8 01
+>39238d		00 1c 0c f9 31 0f 01 15		DRUMINS_LO_AGOGO      .text $00, $1C, $0C, $F9, $31, $0F, $01, $15, $00, $96, $E8, $01
+>392395		00 96 e8 01
+>392399		00 0e 00 ff 01 0f 00 0e		DRUMINS_CABASA        .text $00, $0E, $00, $FF, $01, $0F, $00, $0E, $02, $79, $77, $03
+>3923a1		02 79 77 03
+>3923a5		00 0e 00 ff 01 0f 00 0e		DRUMINS_MARACAS       .text $00, $0E, $00, $FF, $01, $0F, $00, $0E, $02, $79, $77, $03
+>3923ad		02 79 77 03
+>3923b1		00 20 15 af 07 05 01 0e		DRUMINS_S_WHISTL      .text $00, $20, $15, $AF, $07, $05, $01, $0E, $00, $A5, $2B, $02
+>3923b9		00 a5 2b 02
+>3923bd		00 20 18 bf 07 01 01 0e		DRUMINS_L_WHISTL      .text $00, $20, $18, $BF, $07, $01, $01, $0E, $00, $93, $3B, $02
+>3923c5		00 93 3b 02
+>3923c9		00 20 00 f0 f7 0b 00 08		DRUMINS_S_GUIRO       .text $00, $20, $00, $F0, $F7, $0B, $00, $08, $01, $89, $3B, $03
+>3923d1		01 89 3b 03
+>3923d5		00 20 00 f3 fa 09 00 08		DRUMINS_L_GUIRO       .text $00, $20, $00, $F3, $FA, $09, $00, $08, $0A, $53, $2B, $02
+>3923dd		0a 53 2b 02
+>3923e1		00 15 21 f8 9a 09 01 13		DRUMINS_CLAVES        .text $00, $15, $21, $F8, $9A, $09, $01, $13, $00, $F6, $89, $00
+>3923e9		00 f6 89 00
+>3923ed		00 25 1b fa f2 01 00 12		DRUMINS_HI_WDBLK      .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
+>3923f5		00 f6 9a 00
+>3923f9		00 25 1b fa f2 01 00 12		DRUMINS_LO_WDBLK      .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
+>392401		00 f6 9a 00
+>392405		00 20 01 5f 07 01 00 08		DRUMINS_MU_CUICA      .text $00, $20, $01, $5F, $07, $01, $00, $08, $00, $87, $4B, $01
+>39240d		00 87 4b 01
+>392411		00 25 12 57 f7 01 01 03		DRUMINS_OP_CUICA      .text $00, $25, $12, $57, $F7, $01, $01, $03, $00, $78, $67, $01
+>392419		00 78 67 01
+>39241d		00 22 2f f1 f0 07 00 27		DRUMINS_MU_TRNGL      .text $00, $22, $2F, $F1, $F0, $07, $00, $27, $02, $F8, $FC, $00
+>392425		02 f8 fc 00
+>392429		00 26 44 f1 f0 07 00 27		DRUMINS_OP_TRNGL      .text $00, $26, $44, $F1, $F0, $07, $00, $27, $40, $F5, $F5, $00
+>392431		40 f5 f5 00
+>392435		00 0e 00 ff 01 0f 00 0e		DRUMINS_SHAKER        .text $00, $0E, $00, $FF, $01, $0F, $00, $0E, $02, $79, $77, $03
+>39243d		02 79 77 03
+>392441		00 26 44 f1 f0 07 00 27		DRUMINS_TRIANGL1      .text $00, $26, $44, $F1, $F0, $07, $00, $27, $40, $F5, $F5, $00
+>392449		40 f5 f5 00
+>39244d		00 26 44 f1 f0 07 00 27		DRUMINS_TRIANGL2      .text $00, $26, $44, $F1, $F0, $07, $00, $27, $40, $F5, $F5, $00
+>392455		40 f5 f5 00
+>392459		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT3      .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
+>392461		00 f9 69 00
+>392465		00 16 08 f1 fb 01 00 11		DRUMINS_RIMSHOT4      .text $00, $16, $08, $F1, $FB, $01, $00, $11, $00, $F9, $69, $00
+>39246d		00 f9 69 00
+>392471		00 02 1d f5 93 01 00 00		DRUMINS_TAIKO         .text $00, $02, $1D, $F5, $93, $01, $00, $00, $00, $C6, $45, $00
+>392479		00 c6 45 00
+=27						DRUM_NOTE_BASE = 27;
+=60						NUM_MIDI_DRUMS = 60;
+>39247d		ad 21 39 00 b9 21 39 00		midiDrums     .dword DRUMINS_CLAP2, DRUMINS_SCRATCH1, DRUMINS_SCRATCH2, DRUMINS_RIMSHOT2
+>392485		c5 21 39 00 d1 21 39 00
+>39248d		dd 21 39 00 e9 21 39 00		              .dword DRUMINS_HIQ, DRUMINS_WOODBLOK, DRUMINS_GLOCK, DRUMINS_BASS_DR2
+>392495		f5 21 39 00 01 22 39 00
+>39249d		0d 22 39 00 19 22 39 00		              .dword DRUMINS_BASS_DR1, DRUMINS_RIMSHOT,  DRUMINS_SNARE_AC, DRUMINS_CLAP
+>3924a5		25 22 39 00 31 22 39 00
+>3924ad		3d 22 39 00 49 22 39 00		              .dword DRUMINS_SNARE_EL, DRUMINS_LO_TOMS,  DRUMINS_HIHAT_CL, DRUMINS_HI_TOMS
+>3924b5		55 22 39 00 61 22 39 00
+>3924bd		6d 22 39 00 79 22 39 00		              .dword DRUMINS_HIHAT_PL, DRUMINS_LOW_TOM,	DRUMINS_HIHAT_OP, DRUMINS_LTOM_MID
+>3924c5		85 22 39 00 91 22 39 00
+>3924cd		9d 22 39 00 a9 22 39 00		              .dword DRUMINS_HTOM_MID, DRUMINS_CRASH,    DRUMINS_TOM_HIGH, DRUMINS_RIDE_CY
+>3924d5		b5 22 39 00 c1 22 39 00
+>3924dd		cd 22 39 00 d9 22 39 00		              .dword DRUMINS_TAMBOUR,  DRUMINS_CYMBAL,   DRUMINS_TAMBOU2,  DRUMINS_SPLASH
+>3924e5		e5 22 39 00 f1 22 39 00
+>3924ed		fd 22 39 00 09 23 39 00		              .dword DRUMINS_COWBELL,  DRUMINS_CRASH2, 	DRUMINS_VIBRASLA, DRUMINS_RIDE2
+>3924f5		15 23 39 00 21 23 39 00
+>3924fd		2d 23 39 00 39 23 39 00		              .dword DRUMINS_HI_BONGO, DRUMINS_LO_BONGO, DRUMINS_MUTECONG, DRUMINS_OPENCONG
+>392505		45 23 39 00 51 23 39 00
+>39250d		5d 23 39 00 69 23 39 00		              .dword DRUMINS_LOWCONGA, DRUMINS_HI_TIMBA, DRUMINS_LO_TIMBA, DRUMINS_HI_AGOGO
+>392515		75 23 39 00 81 23 39 00
+>39251d		8d 23 39 00 99 23 39 00		              .dword DRUMINS_LO_AGOGO, DRUMINS_CABASA, DRUMINS_MARACAS,  DRUMINS_S_WHISTL
+>392525		a5 23 39 00 b1 23 39 00
+>39252d		bd 23 39 00 c9 23 39 00		              .dword DRUMINS_L_WHISTL, DRUMINS_S_GUIRO,  DRUMINS_L_GUIRO,  DRUMINS_CLAVES
+>392535		d5 23 39 00 e1 23 39 00
+>39253d		ed 23 39 00 f9 23 39 00		              .dword DRUMINS_HI_WDBLK, DRUMINS_LO_WDBLK, DRUMINS_MU_CUICA, DRUMINS_OP_CUICA
+>392545		05 24 39 00 11 24 39 00
+>39254d		1d 24 39 00 29 24 39 00		              .dword DRUMINS_MU_TRNGL, DRUMINS_OP_TRNGL, DRUMINS_SHAKER, DRUMINS_TRIANGL1
+>392555		35 24 39 00 41 24 39 00
+>39255d		4d 24 39 00 59 24 39 00		              .dword DRUMINS_TRIANGL2, DRUMINS_RIMSHOT3, DRUMINS_RIMSHOT4, DRUMINS_TAIKO
+>392565		65 24 39 00 71 24 39 00
+
+;******  Return to file: src\Libraries/OPL2_Library.asm
+
+
+;******  Processing file: src\Libraries/OPL2_Midi_Instruments.asm
+
+>39256d		00 33 5a b2 50 01 00 31		MIDI_INSTRUMENT_PIANO1     .text $00, $33, $5A, $B2, $50, $01, $00, $31, $00, $B1, $F5, $01
+>392575		00 b1 f5 01
+>392579		00 31 49 f2 53 07 01 11		MIDI_INSTRUMENT_PIANO2     .text $00, $31, $49, $F2, $53, $07, $01, $11, $03, $F1, $F5, $00
+>392581		03 f1 f5 00
+>392585		00 31 95 d1 83 0d 01 32		MIDI_INSTRUMENT_PIANO3     .text $00, $31, $95, $D1, $83, $0D, $01, $32, $03, $C1, $F5, $00
+>39258d		03 c1 f5 00
+>392591		00 34 9b f3 63 01 01 11		MIDI_INSTRUMENT_HONKTONK   .text $00, $34, $9B, $F3, $63, $01, $01, $11, $00, $92, $F5, $01
+>392599		00 92 f5 01
+>39259d		00 27 28 f8 b7 01 02 91		MIDI_INSTRUMENT_EP1        .text $00, $27, $28, $F8, $B7, $01, $02, $91, $00, $F1, $F9, $00
+>3925a5		00 f1 f9 00
+>3925a9		00 1a 2d f3 ee 01 01 11		MIDI_INSTRUMENT_EP2        .text $00, $1A, $2D, $F3, $EE, $01, $01, $11, $00, $F1, $F5, $00
+>3925b1		00 f1 f5 00
+>3925b5		00 35 95 f2 58 0f 01 32		MIDI_INSTRUMENT_HARPSIC    .text $00, $35, $95, $F2, $58, $0F, $01, $32, $02, $81, $F6, $01
+>3925bd		02 81 f6 01
+>3925c1		00 31 85 c9 40 01 00 35		MIDI_INSTRUMENT_CLAVIC     .text $00, $31, $85, $C9, $40, $01, $00, $35, $00, $C2, $B9, $01
+>3925c9		00 c2 b9 01
+>3925cd		00 09 15 c7 64 08 00 01		MIDI_INSTRUMENT_CELESTA    .text $00, $09, $15, $C7, $64, $08, $00, $01, $05, $B2, $35, $00
+>3925d5		05 b2 35 00
+>3925d9		00 06 03 f4 44 00 01 01		MIDI_INSTRUMENT_GLOCK      .text $00, $06, $03, $F4, $44, $00, $01, $01, $1B, $F2, $34, $00
+>3925e1		1b f2 34 00
+>3925e5		00 04 06 a9 24 0a 01 01		MIDI_INSTRUMENT_MUSICBOX   .text $00, $04, $06, $A9, $24, $0A, $01, $01, $01, $F5, $74, $00
+>3925ed		01 f5 74 00
+>3925f1		00 d4 00 f6 33 00 00 f1		MIDI_INSTRUMENT_VIBES      .text $00, $D4, $00, $F6, $33, $00, $00, $F1, $00, $61, $E3, $00
+>3925f9		00 61 e3 00
+>3925fd		00 d4 00 f7 e8 04 00 d1		MIDI_INSTRUMENT_MARIMBA    .text $00, $D4, $00, $F7, $E8, $04, $00, $D1, $00, $A4, $64, $00
+>392605		00 a4 64 00
+>392609		00 36 16 f7 f7 01 00 31		MIDI_INSTRUMENT_XYLO       .text $00, $36, $16, $F7, $F7, $01, $00, $31, $07, $B5, $F5, $00
+>392611		07 b5 f5 00
+>392615		00 03 1b a2 43 0b 00 00		MIDI_INSTRUMENT_TUBEBELL   .text $00, $03, $1B, $A2, $43, $0B, $00, $00, $00, $F3, $74, $00
+>39261d		00 f3 74 00
+>392621		00 c3 8e f8 35 01 01 11		MIDI_INSTRUMENT_SANTUR     .text $00, $C3, $8E, $F8, $35, $01, $01, $11, $00, $C3, $94, $01
+>392629		00 c3 94 01
+>39262d		00 e2 07 f4 1b 06 01 e0		MIDI_INSTRUMENT_ORGAN1     .text $00, $E2, $07, $F4, $1B, $06, $01, $E0, $00, $F4, $0D, $01
+>392635		00 f4 0d 01
+>392639		00 f2 00 f6 2c 04 00 f0		MIDI_INSTRUMENT_ORGAN2     .text $00, $F2, $00, $F6, $2C, $04, $00, $F0, $00, $F5, $0B, $01
+>392641		00 f5 0b 01
+>392645		00 f1 06 b6 15 0a 00 f0		MIDI_INSTRUMENT_ORGAN3     .text $00, $F1, $06, $B6, $15, $0A, $00, $F0, $00, $BF, $07, $00
+>39264d		00 bf 07 00
+>392651		00 22 03 79 16 08 01 e0		MIDI_INSTRUMENT_PIPEORG    .text $00, $22, $03, $79, $16, $08, $01, $E0, $00, $6D, $08, $01
+>392659		00 6d 08 01
+>39265d		00 31 27 63 06 01 00 72		MIDI_INSTRUMENT_REEDORG    .text $00, $31, $27, $63, $06, $01, $00, $72, $00, $51, $17, $01
+>392665		00 51 17 01
+>392669		00 b4 1d 53 16 0f 01 71		MIDI_INSTRUMENT_ACORDIAN   .text $00, $B4, $1D, $53, $16, $0F, $01, $71, $00, $51, $17, $01
+>392671		00 51 17 01
+>392675		00 25 29 97 15 01 00 32		MIDI_INSTRUMENT_HARMONIC   .text $00, $25, $29, $97, $15, $01, $00, $32, $00, $53, $08, $01
+>39267d		00 53 08 01
+>392681		00 24 9e 67 15 0f 00 31		MIDI_INSTRUMENT_BANDNEON   .text $00, $24, $9E, $67, $15, $0F, $00, $31, $00, $53, $06, $01
+>392689		00 53 06 01
+>39268d		00 13 27 a3 b4 05 01 31		MIDI_INSTRUMENT_NYLONGT    .text $00, $13, $27, $A3, $B4, $05, $01, $31, $00, $D2, $F8, $00
+>392695		00 d2 f8 00
+>392699		00 17 a3 f3 32 01 00 11		MIDI_INSTRUMENT_STEELGT    .text $00, $17, $A3, $F3, $32, $01, $00, $11, $00, $E2, $C7, $01
+>3926a1		00 e2 c7 01
+>3926a5		00 33 24 d2 c1 0f 01 31		MIDI_INSTRUMENT_JAZZGT     .text $00, $33, $24, $D2, $C1, $0F, $01, $31, $00, $F1, $9C, $00
+>3926ad		00 f1 9c 00
+>3926b1		00 31 05 f8 44 01 00 32		MIDI_INSTRUMENT_CLEANGT    .text $00, $31, $05, $F8, $44, $01, $00, $32, $02, $F2, $C9, $01
+>3926b9		02 f2 c9 01
+>3926bd		00 21 09 9c 7b 07 00 02		MIDI_INSTRUMENT_MUTEGT     .text $00, $21, $09, $9C, $7B, $07, $00, $02, $03, $95, $FB, $00
+>3926c5		03 95 fb 00
+>3926c9		00 21 84 81 98 07 01 21		MIDI_INSTRUMENT_OVERDGT    .text $00, $21, $84, $81, $98, $07, $01, $21, $04, $A1, $59, $00
+>3926d1		04 a1 59 00
+>3926d5		00 b1 0c 78 43 01 00 22		MIDI_INSTRUMENT_DISTGT     .text $00, $B1, $0C, $78, $43, $01, $00, $22, $03, $91, $FC, $03
+>3926dd		03 91 fc 03
+>3926e1		00 00 0a 82 8c 09 00 08		MIDI_INSTRUMENT_GTHARMS    .text $00, $00, $0A, $82, $8C, $09, $00, $08, $02, $B4, $EC, $00
+>3926e9		02 b4 ec 00
+>3926ed		00 21 13 ab 46 01 00 21		MIDI_INSTRUMENT_ACOUBASS   .text $00, $21, $13, $AB, $46, $01, $00, $21, $00, $93, $F7, $00
+>3926f5		00 93 f7 00
+>3926f9		00 01 0a f9 32 01 00 22		MIDI_INSTRUMENT_FINGBASS   .text $00, $01, $0A, $F9, $32, $01, $00, $22, $04, $C1, $58, $00
+>392701		04 c1 58 00
+>392705		00 21 07 fa 77 0b 00 22		MIDI_INSTRUMENT_PICKBASS   .text $00, $21, $07, $FA, $77, $0B, $00, $22, $02, $C3, $6A, $00
+>39270d		02 c3 6a 00
+>392711		00 21 17 71 57 0b 00 21		MIDI_INSTRUMENT_FRETLESS   .text $00, $21, $17, $71, $57, $0B, $00, $21, $00, $62, $87, $00
+>392719		00 62 87 00
+>39271d		00 25 01 fa 78 07 01 12		MIDI_INSTRUMENT_SLAPBAS1   .text $00, $25, $01, $FA, $78, $07, $01, $12, $00, $F3, $97, $00
+>392725		00 f3 97 00
+>392729		00 21 03 fa 88 0d 00 13		MIDI_INSTRUMENT_SLAPBAS2   .text $00, $21, $03, $FA, $88, $0D, $00, $13, $00, $B3, $97, $00
+>392731		00 b3 97 00
+>392735		00 21 09 f5 7f 09 01 23		MIDI_INSTRUMENT_SYNBASS1   .text $00, $21, $09, $F5, $7F, $09, $01, $23, $04, $F3, $CC, $00
+>39273d		04 f3 cc 00
+>392741		00 01 10 a3 9b 09 00 01		MIDI_INSTRUMENT_SYNBASS2   .text $00, $01, $10, $A3, $9B, $09, $00, $01, $00, $93, $AA, $00
+>392749		00 93 aa 00
+>39274d		00 e2 19 f6 29 0d 01 e1		MIDI_INSTRUMENT_VIOLIN     .text $00, $E2, $19, $F6, $29, $0D, $01, $E1, $00, $78, $08, $01
+>392755		00 78 08 01
+>392759		00 e2 1c f6 29 0d 01 e1		MIDI_INSTRUMENT_VIOLA      .text $00, $E2, $1C, $F6, $29, $0D, $01, $E1, $00, $78, $08, $01
+>392761		00 78 08 01
+>392765		00 61 19 69 16 0b 01 61		MIDI_INSTRUMENT_CELLO      .text $00, $61, $19, $69, $16, $0B, $01, $61, $00, $54, $27, $01
+>39276d		00 54 27 01
+>392771		00 71 18 82 31 0d 01 32		MIDI_INSTRUMENT_CONTRAB    .text $00, $71, $18, $82, $31, $0D, $01, $32, $00, $61, $56, $00
+>392779		00 61 56 00
+>39277d		00 e2 23 70 06 0d 01 e1		MIDI_INSTRUMENT_TREMSTR    .text $00, $E2, $23, $70, $06, $0D, $01, $E1, $00, $75, $16, $01
+>392785		00 75 16 01
+>392789		00 02 00 88 e6 08 00 61		MIDI_INSTRUMENT_PIZZ       .text $00, $02, $00, $88, $E6, $08, $00, $61, $00, $F5, $F6, $01
+>392791		00 f5 f6 01
+>392795		00 12 20 f6 d5 0f 01 11		MIDI_INSTRUMENT_HARP       .text $00, $12, $20, $F6, $D5, $0F, $01, $11, $80, $F3, $E3, $00
+>39279d		80 f3 e3 00
+>3927a1		00 61 0e f4 f4 01 01 00		MIDI_INSTRUMENT_TIMPANI    .text $00, $61, $0E, $F4, $F4, $01, $01, $00, $00, $B5, $F5, $00
+>3927a9		00 b5 f5 00
+>3927ad		00 61 1e 9c 04 0f 01 21		MIDI_INSTRUMENT_STRINGS    .text $00, $61, $1E, $9C, $04, $0F, $01, $21, $80, $71, $16, $00
+>3927b5		80 71 16 00
+>3927b9		00 a2 2a c0 d6 0f 02 21		MIDI_INSTRUMENT_SLOWSTR    .text $00, $A2, $2A, $C0, $D6, $0F, $02, $21, $00, $30, $55, $01
+>3927c1		00 30 55 01
+>3927c5		00 61 21 72 35 0f 01 61		MIDI_INSTRUMENT_SYNSTR1    .text $00, $61, $21, $72, $35, $0F, $01, $61, $00, $62, $36, $01
+>3927cd		00 62 36 01
+>3927d1		00 21 1a 72 23 0f 01 21		MIDI_INSTRUMENT_SYNSTR2    .text $00, $21, $1A, $72, $23, $0F, $01, $21, $02, $51, $07, $00
+>3927d9		02 51 07 00
+>3927dd		00 e1 16 97 31 09 00 61		MIDI_INSTRUMENT_CHOIR      .text $00, $E1, $16, $97, $31, $09, $00, $61, $00, $62, $39, $00
+>3927e5		00 62 39 00
+>3927e9		00 22 c3 79 45 01 00 21		MIDI_INSTRUMENT_OOHS       .text $00, $22, $C3, $79, $45, $01, $00, $21, $00, $66, $27, $00
+>3927f1		00 66 27 00
+>3927f5		00 21 de 63 55 01 01 21		MIDI_INSTRUMENT_SYNVOX     .text $00, $21, $DE, $63, $55, $01, $01, $21, $00, $73, $46, $00
+>3927fd		00 73 46 00
+>392801		00 42 05 86 f7 0a 00 50		MIDI_INSTRUMENT_ORCHIT     .text $00, $42, $05, $86, $F7, $0A, $00, $50, $00, $74, $76, $01
+>392809		00 74 76 01
+>39280d		00 31 1c 61 02 0f 00 61		MIDI_INSTRUMENT_TRUMPET    .text $00, $31, $1C, $61, $02, $0F, $00, $61, $81, $92, $38, $00
+>392815		81 92 38 00
+>392819		00 71 1e 52 23 0f 00 61		MIDI_INSTRUMENT_TROMBONE   .text $00, $71, $1E, $52, $23, $0F, $00, $61, $02, $71, $19, $00
+>392821		02 71 19 00
+>392825		00 21 1a 76 16 0f 00 21		MIDI_INSTRUMENT_TUBA       .text $00, $21, $1A, $76, $16, $0F, $00, $21, $01, $81, $09, $00
+>39282d		01 81 09 00
+>392831		00 25 28 89 2c 07 02 20		MIDI_INSTRUMENT_MUTETRP    .text $00, $25, $28, $89, $2C, $07, $02, $20, $00, $83, $4B, $02
+>392839		00 83 4b 02
+>39283d		00 21 1f 79 16 09 00 a2		MIDI_INSTRUMENT_FRHORN     .text $00, $21, $1F, $79, $16, $09, $00, $A2, $05, $71, $59, $00
+>392845		05 71 59 00
+>392849		00 21 19 87 16 0f 00 21		MIDI_INSTRUMENT_BRASS1     .text $00, $21, $19, $87, $16, $0F, $00, $21, $03, $82, $39, $00
+>392851		03 82 39 00
+>392855		00 21 17 75 35 0f 00 22		MIDI_INSTRUMENT_SYNBRAS1   .text $00, $21, $17, $75, $35, $0F, $00, $22, $82, $84, $17, $00
+>39285d		82 84 17 00
+>392861		00 21 22 62 58 0f 00 21		MIDI_INSTRUMENT_SYNBRAS2   .text $00, $21, $22, $62, $58, $0F, $00, $21, $02, $72, $16, $00
+>392869		02 72 16 00
+>39286d		00 b1 1b 59 07 01 01 a1		MIDI_INSTRUMENT_SOPSAX     .text $00, $B1, $1B, $59, $07, $01, $01, $A1, $00, $7B, $0A, $00
+>392875		00 7b 0a 00
+>392879		00 21 16 9f 04 0b 00 21		MIDI_INSTRUMENT_ALTOSAX    .text $00, $21, $16, $9F, $04, $0B, $00, $21, $00, $85, $0C, $01
+>392881		00 85 0c 01
+>392885		00 21 0f a8 20 0d 00 23		MIDI_INSTRUMENT_TENSAX     .text $00, $21, $0F, $A8, $20, $0D, $00, $23, $00, $7B, $0A, $01
+>39288d		00 7b 0a 01
+>392891		00 21 0f 88 04 09 00 26		MIDI_INSTRUMENT_BARISAX    .text $00, $21, $0F, $88, $04, $09, $00, $26, $00, $79, $18, $01
+>392899		00 79 18 01
+>39289d		00 31 18 8f 05 01 00 32		MIDI_INSTRUMENT_OBOE       .text $00, $31, $18, $8F, $05, $01, $00, $32, $01, $73, $08, $00
+>3928a5		01 73 08 00
+>3928a9		00 a1 0a 8c 37 01 01 24		MIDI_INSTRUMENT_ENGLHORN   .text $00, $A1, $0A, $8C, $37, $01, $01, $24, $04, $77, $0A, $00
+>3928b1		04 77 0a 00
+>3928b5		00 31 04 a8 67 0b 00 75		MIDI_INSTRUMENT_BASSOON    .text $00, $31, $04, $A8, $67, $0B, $00, $75, $00, $51, $19, $00
+>3928bd		00 51 19 00
+>3928c1		00 a2 1f 77 26 01 01 21		MIDI_INSTRUMENT_CLARINET   .text $00, $A2, $1F, $77, $26, $01, $01, $21, $01, $74, $09, $00
+>3928c9		01 74 09 00
+>3928cd		00 e1 07 b8 94 01 01 21		MIDI_INSTRUMENT_PICCOLO    .text $00, $E1, $07, $B8, $94, $01, $01, $21, $01, $63, $28, $00
+>3928d5		01 63 28 00
+>3928d9		00 a1 93 87 59 01 00 e1		MIDI_INSTRUMENT_FLUTE1     .text $00, $A1, $93, $87, $59, $01, $00, $E1, $00, $65, $0A, $00
+>3928e1		00 65 0a 00
+>3928e5		00 22 10 9f 38 01 00 61		MIDI_INSTRUMENT_RECORDER   .text $00, $22, $10, $9F, $38, $01, $00, $61, $00, $67, $29, $00
+>3928ed		00 67 29 00
+>3928f1		00 e2 0d 88 9a 01 01 21		MIDI_INSTRUMENT_PANFLUTE   .text $00, $E2, $0D, $88, $9A, $01, $01, $21, $00, $67, $09, $00
+>3928f9		00 67 09 00
+>3928fd		00 a2 10 98 94 0f 00 21		MIDI_INSTRUMENT_BOTTLEB    .text $00, $A2, $10, $98, $94, $0F, $00, $21, $01, $6A, $28, $00
+>392905		01 6a 28 00
+>392909		00 f1 1c 86 26 0f 00 f1		MIDI_INSTRUMENT_SHAKU      .text $00, $F1, $1C, $86, $26, $0F, $00, $F1, $00, $55, $27, $00
+>392911		00 55 27 00
+>392915		00 e1 3f 9f 09 00 00 e1		MIDI_INSTRUMENT_WHISTLE    .text $00, $E1, $3F, $9F, $09, $00, $00, $E1, $00, $6F, $08, $00
+>39291d		00 6f 08 00
+>392921		00 e2 3b f7 19 01 00 21		MIDI_INSTRUMENT_OCARINA    .text $00, $E2, $3B, $F7, $19, $01, $00, $21, $00, $7A, $07, $00
+>392929		00 7a 07 00
+>39292d		00 22 1e 92 0c 0f 00 61		MIDI_INSTRUMENT_SQUARWAV   .text $00, $22, $1E, $92, $0C, $0F, $00, $61, $06, $A2, $0D, $00
+>392935		06 a2 0d 00
+>392939		00 21 15 f4 22 0f 01 21		MIDI_INSTRUMENT_SAWWAV     .text $00, $21, $15, $F4, $22, $0F, $01, $21, $00, $A3, $5F, $00
+>392941		00 a3 5f 00
+>392945		00 f2 20 47 66 03 01 f1		MIDI_INSTRUMENT_SYNCALLI   .text $00, $F2, $20, $47, $66, $03, $01, $F1, $00, $42, $27, $00
+>39294d		00 42 27 00
+>392951		00 61 19 88 28 0f 00 61		MIDI_INSTRUMENT_CHIFLEAD   .text $00, $61, $19, $88, $28, $0F, $00, $61, $05, $B2, $49, $00
+>392959		05 b2 49 00
+>39295d		00 21 16 82 1b 01 00 23		MIDI_INSTRUMENT_CHARANG    .text $00, $21, $16, $82, $1B, $01, $00, $23, $00, $B2, $79, $01
+>392965		00 b2 79 01
+>392969		00 21 00 ca 93 01 00 22		MIDI_INSTRUMENT_SOLOVOX    .text $00, $21, $00, $CA, $93, $01, $00, $22, $00, $7A, $1A, $00
+>392971		00 7a 1a 00
+>392975		00 23 00 92 c9 08 01 22		MIDI_INSTRUMENT_FIFTHSAW   .text $00, $23, $00, $92, $C9, $08, $01, $22, $00, $82, $28, $01
+>39297d		00 82 28 01
+>392981		00 21 1d f3 7b 0f 00 22		MIDI_INSTRUMENT_BASSLEAD   .text $00, $21, $1D, $F3, $7B, $0F, $00, $22, $02, $C3, $5F, $00
+>392989		02 c3 5f 00
+>39298d		00 e1 00 81 25 00 01 a6		MIDI_INSTRUMENT_FANTASIA   .text $00, $E1, $00, $81, $25, $00, $01, $A6, $86, $C4, $95, $01
+>392995		86 c4 95 01
+>392999		00 21 27 31 01 0f 00 21		MIDI_INSTRUMENT_WARMPAD    .text $00, $21, $27, $31, $01, $0F, $00, $21, $00, $44, $15, $00
+>3929a1		00 44 15 00
+>3929a5		00 60 14 83 35 0d 02 61		MIDI_INSTRUMENT_POLYSYN    .text $00, $60, $14, $83, $35, $0D, $02, $61, $00, $D1, $06, $00
+>3929ad		00 d1 06 00
+>3929b1		00 e1 5c d3 01 01 01 62		MIDI_INSTRUMENT_SPACEVOX   .text $00, $E1, $5C, $D3, $01, $01, $01, $62, $00, $82, $37, $00
+>3929b9		00 82 37 00
+>3929bd		00 28 38 34 86 01 02 21		MIDI_INSTRUMENT_BOWEDGLS   .text $00, $28, $38, $34, $86, $01, $02, $21, $00, $41, $35, $00
+>3929c5		00 41 35 00
+>3929c9		00 24 12 52 f3 05 01 23		MIDI_INSTRUMENT_METALPAD   .text $00, $24, $12, $52, $F3, $05, $01, $23, $02, $32, $F5, $01
+>3929d1		02 32 f5 01
+>3929d5		00 61 1d 62 a6 0b 00 a1		MIDI_INSTRUMENT_HALOPAD    .text $00, $61, $1D, $62, $A6, $0B, $00, $A1, $00, $61, $26, $00
+>3929dd		00 61 26 00
+>3929e1		00 22 0f 22 d5 0b 01 21		MIDI_INSTRUMENT_SWEEPPAD   .text $00, $22, $0F, $22, $D5, $0B, $01, $21, $84, $3F, $05, $01
+>3929e9		84 3f 05 01
+>3929ed		00 e3 1f f9 24 01 00 31		MIDI_INSTRUMENT_ICERAIN    .text $00, $E3, $1F, $F9, $24, $01, $00, $31, $01, $D1, $F6, $00
+>3929f5		01 d1 f6 00
+>3929f9		00 63 00 41 55 06 01 a2		MIDI_INSTRUMENT_SOUNDTRK   .text $00, $63, $00, $41, $55, $06, $01, $A2, $00, $41, $05, $01
+>392a01		00 41 05 01
+>392a05		00 c7 25 a7 65 01 01 c1		MIDI_INSTRUMENT_CRYSTAL    .text $00, $C7, $25, $A7, $65, $01, $01, $C1, $05, $F3, $E4, $00
+>392a0d		05 f3 e4 00
+>392a11		00 e3 19 f7 b7 01 01 61		MIDI_INSTRUMENT_ATMOSPH    .text $00, $E3, $19, $F7, $B7, $01, $01, $61, $00, $92, $F5, $01
+>392a19		00 92 f5 01
+>392a1d		00 66 9b a8 44 0f 00 41		MIDI_INSTRUMENT_BRIGHT     .text $00, $66, $9B, $A8, $44, $0F, $00, $41, $04, $F2, $E4, $01
+>392a25		04 f2 e4 01
+>392a29		00 61 20 22 75 0d 00 61		MIDI_INSTRUMENT_GOBLIN     .text $00, $61, $20, $22, $75, $0D, $00, $61, $00, $45, $25, $00
+>392a31		00 45 25 00
+>392a35		00 e1 21 f6 84 0f 00 e1		MIDI_INSTRUMENT_ECHODROP   .text $00, $E1, $21, $F6, $84, $0F, $00, $E1, $01, $A3, $36, $00
+>392a3d		01 a3 36 00
+>392a41		00 e2 14 73 64 0b 01 e1		MIDI_INSTRUMENT_STARTHEM   .text $00, $E2, $14, $73, $64, $0B, $01, $E1, $01, $98, $05, $01
+>392a49		01 98 05 01
+>392a4d		00 21 0b 72 34 09 00 24		MIDI_INSTRUMENT_SITAR      .text $00, $21, $0B, $72, $34, $09, $00, $24, $02, $A3, $F6, $01
+>392a55		02 a3 f6 01
+>392a59		00 21 16 f4 53 0d 00 04		MIDI_INSTRUMENT_BANJO      .text $00, $21, $16, $F4, $53, $0D, $00, $04, $00, $F6, $F8, $00
+>392a61		00 f6 f8 00
+>392a65		00 21 18 da 02 0d 00 35		MIDI_INSTRUMENT_SHAMISEN   .text $00, $21, $18, $DA, $02, $0D, $00, $35, $00, $F3, $F5, $00
+>392a6d		00 f3 f5 00
+>392a71		00 25 0f fa 63 09 00 02		MIDI_INSTRUMENT_KOTO       .text $00, $25, $0F, $FA, $63, $09, $00, $02, $00, $94, $E5, $01
+>392a79		00 94 e5 01
+>392a7d		00 32 07 f9 96 01 00 11		MIDI_INSTRUMENT_KALIMBA    .text $00, $32, $07, $F9, $96, $01, $00, $11, $00, $84, $44, $00
+>392a85		00 84 44 00
+>392a89		00 20 0e 97 18 09 02 25		MIDI_INSTRUMENT_BAGPIPE    .text $00, $20, $0E, $97, $18, $09, $02, $25, $03, $83, $18, $01
+>392a91		03 83 18 01
+>392a95		00 61 18 f6 29 01 00 62		MIDI_INSTRUMENT_FIDDLE     .text $00, $61, $18, $F6, $29, $01, $00, $62, $01, $78, $08, $01
+>392a9d		01 78 08 01
+>392aa1		00 e6 21 76 19 0b 00 61		MIDI_INSTRUMENT_SHANNAI    .text $00, $E6, $21, $76, $19, $0B, $00, $61, $03, $8E, $08, $01
+>392aa9		03 8e 08 01
+>392aad		00 27 23 f0 d4 01 00 05		MIDI_INSTRUMENT_TINKLBEL   .text $00, $27, $23, $F0, $D4, $01, $00, $05, $09, $F2, $46, $00
+>392ab5		09 f2 46 00
+>392ab9		00 1c 0c f9 31 0f 01 15		MIDI_INSTRUMENT_AGOGO      .text $00, $1C, $0C, $F9, $31, $0F, $01, $15, $00, $96, $E8, $01
+>392ac1		00 96 e8 01
+>392ac5		00 02 00 75 16 06 02 01		MIDI_INSTRUMENT_STEELDRM   .text $00, $02, $00, $75, $16, $06, $02, $01, $00, $F6, $F6, $01
+>392acd		00 f6 f6 01
+>392ad1		00 25 1b fa f2 01 00 12		MIDI_INSTRUMENT_WOODBLOK   .text $00, $25, $1B, $FA, $F2, $01, $00, $12, $00, $F6, $9A, $00
+>392ad9		00 f6 9a 00
+>392add		00 02 1d f5 93 01 00 00		MIDI_INSTRUMENT_TAIKO      .text $00, $02, $1D, $F5, $93, $01, $00, $00, $00, $C6, $45, $00
+>392ae5		00 c6 45 00
+>392ae9		00 11 15 f5 32 05 00 10		MIDI_INSTRUMENT_MELOTOM    .text $00, $11, $15, $F5, $32, $05, $00, $10, $00, $F4, $B4, $00
+>392af1		00 f4 b4 00
+>392af5		00 22 06 fa 99 09 00 01		MIDI_INSTRUMENT_SYNDRUM    .text $00, $22, $06, $FA, $99, $09, $00, $01, $00, $D5, $25, $00
+>392afd		00 d5 25 00
+>392b01		00 2e 00 ff 00 0f 02 0e		MIDI_INSTRUMENT_REVRSCYM   .text $00, $2E, $00, $FF, $00, $0F, $02, $0E, $0E, $21, $2D, $00
+>392b09		0e 21 2d 00
+>392b0d		00 30 0b 56 e4 01 01 17		MIDI_INSTRUMENT_FRETNOIS   .text $00, $30, $0B, $56, $E4, $01, $01, $17, $00, $55, $87, $02
+>392b15		00 55 87 02
+>392b19		00 24 00 ff 03 0d 00 05		MIDI_INSTRUMENT_BRTHNOIS   .text $00, $24, $00, $FF, $03, $0D, $00, $05, $08, $98, $87, $01
+>392b21		08 98 87 01
+>392b25		00 0e 00 f0 00 0f 02 0a		MIDI_INSTRUMENT_SEASHORE   .text $00, $0E, $00, $F0, $00, $0F, $02, $0A, $04, $17, $04, $03
+>392b2d		04 17 04 03
+>392b31		00 20 08 f6 f7 01 00 0e		MIDI_INSTRUMENT_BIRDS      .text $00, $20, $08, $F6, $F7, $01, $00, $0E, $05, $77, $F9, $02
+>392b39		05 77 f9 02
+>392b3d		00 20 14 f1 08 01 00 2e		MIDI_INSTRUMENT_TELEPHON   .text $00, $20, $14, $F1, $08, $01, $00, $2E, $02, $F4, $08, $00
+>392b45		02 f4 08 00
+>392b49		00 20 04 f2 00 03 01 23		MIDI_INSTRUMENT_HELICOPT   .text $00, $20, $04, $F2, $00, $03, $01, $23, $00, $36, $05, $01
+>392b51		00 36 05 01
+>392b55		00 2e 00 ff 02 0f 00 2a		MIDI_INSTRUMENT_APPLAUSE   .text $00, $2E, $00, $FF, $02, $0F, $00, $2A, $05, $32, $55, $03
+>392b5d		05 32 55 03
+>392b61		00 20 00 a1 ef 0f 00 10		MIDI_INSTRUMENT_GUNSHOT    .text $00, $20, $00, $A1, $EF, $0F, $00, $10, $00, $F3, $DF, $00
+>392b69		00 f3 df 00
+>392b6d		6d 25 39 00 79 25 39 00		midiInstruments .dword MIDI_INSTRUMENT_PIANO1,   MIDI_INSTRUMENT_PIANO2,   MIDI_INSTRUMENT_PIANO3,   MIDI_INSTRUMENT_HONKTONK, MIDI_INSTRUMENT_EP1,      MIDI_INSTRUMENT_EP2
+>392b75		85 25 39 00 91 25 39 00 9d 25 39 00 a9 25 39 00
+>392b85		b5 25 39 00 c1 25 39 00		              	.dword MIDI_INSTRUMENT_HARPSIC,  MIDI_INSTRUMENT_CLAVIC,   MIDI_INSTRUMENT_CELESTA,  MIDI_INSTRUMENT_GLOCK,    MIDI_INSTRUMENT_MUSICBOX, MIDI_INSTRUMENT_VIBES
+>392b8d		cd 25 39 00 d9 25 39 00 e5 25 39 00 f1 25 39 00
+>392b9d		fd 25 39 00 09 26 39 00		              	.dword MIDI_INSTRUMENT_MARIMBA,  MIDI_INSTRUMENT_XYLO,     MIDI_INSTRUMENT_TUBEBELL, MIDI_INSTRUMENT_SANTUR,   MIDI_INSTRUMENT_ORGAN1,   MIDI_INSTRUMENT_ORGAN2
+>392ba5		15 26 39 00 21 26 39 00 2d 26 39 00 39 26 39 00
+>392bb5		45 26 39 00 51 26 39 00		              	.dword MIDI_INSTRUMENT_ORGAN3,   MIDI_INSTRUMENT_PIPEORG,  MIDI_INSTRUMENT_REEDORG,  MIDI_INSTRUMENT_ACORDIAN, MIDI_INSTRUMENT_HARMONIC, MIDI_INSTRUMENT_BANDNEON
+>392bbd		5d 26 39 00 69 26 39 00 75 26 39 00 81 26 39 00
+>392bcd		8d 26 39 00 99 26 39 00		              	.dword MIDI_INSTRUMENT_NYLONGT,  MIDI_INSTRUMENT_STEELGT,  MIDI_INSTRUMENT_JAZZGT,   MIDI_INSTRUMENT_CLEANGT,  MIDI_INSTRUMENT_MUTEGT,   MIDI_INSTRUMENT_OVERDGT
+>392bd5		a5 26 39 00 b1 26 39 00 bd 26 39 00 c9 26 39 00
+>392be5		d5 26 39 00 e1 26 39 00		              	.dword MIDI_INSTRUMENT_DISTGT,   MIDI_INSTRUMENT_GTHARMS,  MIDI_INSTRUMENT_ACOUBASS, MIDI_INSTRUMENT_FINGBASS, MIDI_INSTRUMENT_PICKBASS, MIDI_INSTRUMENT_FRETLESS
+>392bed		ed 26 39 00 f9 26 39 00 05 27 39 00 11 27 39 00
+>392bfd		1d 27 39 00 29 27 39 00		              	.dword MIDI_INSTRUMENT_SLAPBAS1, MIDI_INSTRUMENT_SLAPBAS2, MIDI_INSTRUMENT_SYNBASS1, MIDI_INSTRUMENT_SYNBASS2, MIDI_INSTRUMENT_VIOLIN,   MIDI_INSTRUMENT_VIOLA
+>392c05		35 27 39 00 41 27 39 00 4d 27 39 00 59 27 39 00
+>392c15		65 27 39 00 71 27 39 00		              	.dword MIDI_INSTRUMENT_CELLO,    MIDI_INSTRUMENT_CONTRAB,  MIDI_INSTRUMENT_TREMSTR,  MIDI_INSTRUMENT_PIZZ,     MIDI_INSTRUMENT_HARP,     MIDI_INSTRUMENT_TIMPANI
+>392c1d		7d 27 39 00 89 27 39 00 95 27 39 00 a1 27 39 00
+>392c2d		ad 27 39 00 b9 27 39 00		              	.dword MIDI_INSTRUMENT_STRINGS,  MIDI_INSTRUMENT_SLOWSTR,  MIDI_INSTRUMENT_SYNSTR1,  MIDI_INSTRUMENT_SYNSTR2,  MIDI_INSTRUMENT_CHOIR,    MIDI_INSTRUMENT_OOHS
+>392c35		c5 27 39 00 d1 27 39 00 dd 27 39 00 e9 27 39 00
+>392c45		f5 27 39 00 01 28 39 00		              	.dword MIDI_INSTRUMENT_SYNVOX,   MIDI_INSTRUMENT_ORCHIT,   MIDI_INSTRUMENT_TRUMPET,  MIDI_INSTRUMENT_TROMBONE, MIDI_INSTRUMENT_TUBA,     MIDI_INSTRUMENT_MUTETRP
+>392c4d		0d 28 39 00 19 28 39 00 25 28 39 00 31 28 39 00
+>392c5d		3d 28 39 00 49 28 39 00		              	.dword MIDI_INSTRUMENT_FRHORN,   MIDI_INSTRUMENT_BRASS1,   MIDI_INSTRUMENT_SYNBRAS1, MIDI_INSTRUMENT_SYNBRAS2, MIDI_INSTRUMENT_SOPSAX,   MIDI_INSTRUMENT_ALTOSAX
+>392c65		55 28 39 00 61 28 39 00 6d 28 39 00 79 28 39 00
+>392c75		85 28 39 00 91 28 39 00		              	.dword MIDI_INSTRUMENT_TENSAX,   MIDI_INSTRUMENT_BARISAX,  MIDI_INSTRUMENT_OBOE,     MIDI_INSTRUMENT_ENGLHORN, MIDI_INSTRUMENT_BASSOON,  MIDI_INSTRUMENT_CLARINET
+>392c7d		9d 28 39 00 a9 28 39 00 b5 28 39 00 c1 28 39 00
+>392c8d		cd 28 39 00 d9 28 39 00		              	.dword MIDI_INSTRUMENT_PICCOLO,  MIDI_INSTRUMENT_FLUTE1,   MIDI_INSTRUMENT_RECORDER, MIDI_INSTRUMENT_PANFLUTE, MIDI_INSTRUMENT_BOTTLEB,  MIDI_INSTRUMENT_SHAKU
+>392c95		e5 28 39 00 f1 28 39 00 fd 28 39 00 09 29 39 00
+>392ca5		15 29 39 00 21 29 39 00		              	.dword MIDI_INSTRUMENT_WHISTLE,  MIDI_INSTRUMENT_OCARINA,  MIDI_INSTRUMENT_SQUARWAV, MIDI_INSTRUMENT_SAWWAV,   MIDI_INSTRUMENT_SYNCALLI, MIDI_INSTRUMENT_CHIFLEAD
+>392cad		2d 29 39 00 39 29 39 00 45 29 39 00 51 29 39 00
+>392cbd		5d 29 39 00 69 29 39 00		              	.dword MIDI_INSTRUMENT_CHARANG,  MIDI_INSTRUMENT_SOLOVOX,  MIDI_INSTRUMENT_FIFTHSAW, MIDI_INSTRUMENT_BASSLEAD, MIDI_INSTRUMENT_FANTASIA, MIDI_INSTRUMENT_WARMPAD
+>392cc5		75 29 39 00 81 29 39 00 8d 29 39 00 99 29 39 00
+>392cd5		a5 29 39 00 b1 29 39 00		              	.dword MIDI_INSTRUMENT_POLYSYN,  MIDI_INSTRUMENT_SPACEVOX, MIDI_INSTRUMENT_BOWEDGLS, MIDI_INSTRUMENT_METALPAD, MIDI_INSTRUMENT_HALOPAD,  MIDI_INSTRUMENT_SWEEPPAD
+>392cdd		bd 29 39 00 c9 29 39 00 d5 29 39 00 e1 29 39 00
+>392ced		ed 29 39 00 f9 29 39 00		              	.dword MIDI_INSTRUMENT_ICERAIN,  MIDI_INSTRUMENT_SOUNDTRK, MIDI_INSTRUMENT_CRYSTAL,  MIDI_INSTRUMENT_ATMOSPH,  MIDI_INSTRUMENT_BRIGHT,   MIDI_INSTRUMENT_GOBLIN
+>392cf5		05 2a 39 00 11 2a 39 00 1d 2a 39 00 29 2a 39 00
+>392d05		35 2a 39 00 41 2a 39 00		              	.dword MIDI_INSTRUMENT_ECHODROP, MIDI_INSTRUMENT_STARTHEM, MIDI_INSTRUMENT_SITAR,    MIDI_INSTRUMENT_BANJO,    MIDI_INSTRUMENT_SHAMISEN, MIDI_INSTRUMENT_KOTO
+>392d0d		4d 2a 39 00 59 2a 39 00 65 2a 39 00 71 2a 39 00
+>392d1d		7d 2a 39 00 89 2a 39 00		              	.dword MIDI_INSTRUMENT_KALIMBA,  MIDI_INSTRUMENT_BAGPIPE,  MIDI_INSTRUMENT_FIDDLE,   MIDI_INSTRUMENT_SHANNAI,  MIDI_INSTRUMENT_TINKLBEL, MIDI_INSTRUMENT_AGOGO
+>392d25		95 2a 39 00 a1 2a 39 00 ad 2a 39 00 b9 2a 39 00
+>392d35		c5 2a 39 00 d1 2a 39 00		              	.dword MIDI_INSTRUMENT_STEELDRM, MIDI_INSTRUMENT_WOODBLOK, MIDI_INSTRUMENT_TAIKO,    MIDI_INSTRUMENT_MELOTOM,  MIDI_INSTRUMENT_SYNDRUM,  MIDI_INSTRUMENT_REVRSCYM
+>392d3d		dd 2a 39 00 e9 2a 39 00 f5 2a 39 00 01 2b 39 00
+>392d4d		0d 2b 39 00 19 2b 39 00		              	.dword MIDI_INSTRUMENT_FRETNOIS, MIDI_INSTRUMENT_BRTHNOIS, MIDI_INSTRUMENT_SEASHORE, MIDI_INSTRUMENT_BIRDS,    MIDI_INSTRUMENT_TELEPHON, MIDI_INSTRUMENT_HELICOPT
+>392d55		25 2b 39 00 31 2b 39 00 3d 2b 39 00 49 2b 39 00
+>392d65		55 2b 39 00 61 2b 39 00		              	.dword MIDI_INSTRUMENT_APPLAUSE, MIDI_INSTRUMENT_GUNSHOT
+
+;******  Return to file: src\Libraries/OPL2_Library.asm
+
+
+;******  Processing file: src\Libraries/OPL2_Midi_Instruments_Win31.asm
+
+>392d6d		00 01 8f f2 f4 38 00 01		MIDIW31_INSTRUMENT_PIANO1     .text $00, $01, $8F, $F2, $F4, $38, $00, $01, $0D, $F2, $F7, $00
+>392d75		0d f2 f7 00
+>392d79		00 01 4b f2 f4 38 00 01		MIDIW31_INSTRUMENT_PIANO2     .text $00, $01, $4B, $F2, $F4, $38, $00, $01, $07, $F2, $F7, $00
+>392d81		07 f2 f7 00
+>392d85		00 01 49 f2 f4 38 00 01		MIDIW31_INSTRUMENT_PIANO3     .text $00, $01, $49, $F2, $F4, $38, $00, $01, $07, $F2, $F6, $00
+>392d8d		07 f2 f6 00
+>392d91		00 81 12 f2 f7 00 00 41		MIDIW31_INSTRUMENT_HONKTONK   .text $00, $81, $12, $F2, $F7, $00, $00, $41, $07, $F2, $F7, $00
+>392d99		07 f2 f7 00
+>392d9d		00 01 57 f1 f7 00 00 01		MIDIW31_INSTRUMENT_EP1        .text $00, $01, $57, $F1, $F7, $00, $00, $01, $07, $F2, $F7, $00
+>392da5		07 f2 f7 00
+>392da9		00 01 93 f1 f7 00 00 01		MIDIW31_INSTRUMENT_EP2        .text $00, $01, $93, $F1, $F7, $00, $00, $01, $07, $F2, $F7, $00
+>392db1		07 f2 f7 00
+>392db5		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_HARPSIC    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392dbd		00 00 00 00
+>392dc1		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CLAVIC     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392dc9		00 00 00 00
+>392dcd		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CELESTA    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392dd5		00 00 00 00
+>392dd9		00 07 97 f3 f2 32 00 11		MIDIW31_INSTRUMENT_GLOCK      .text $00, $07, $97, $F3, $F2, $32, $00, $11, $87, $F2, $F1, $00
+>392de1		87 f2 f1 00
+>392de5		00 17 21 54 f4 32 00 01		MIDIW31_INSTRUMENT_MUSICBOX   .text $00, $17, $21, $54, $F4, $32, $00, $01, $07, $F4, $F4, $00
+>392ded		07 f4 f4 00
+>392df1		00 98 62 f3 f6 30 00 81		MIDIW31_INSTRUMENT_VIBES      .text $00, $98, $62, $F3, $F6, $30, $00, $81, $07, $F2, $F6, $00
+>392df9		07 f2 f6 00
+>392dfd		00 18 23 f6 f6 00 00 01		MIDIW31_INSTRUMENT_MARIMBA    .text $00, $18, $23, $F6, $F6, $00, $00, $01, $07, $E7, $F7, $00
+>392e05		07 e7 f7 00
+>392e09		00 15 91 f6 f6 00 00 01		MIDIW31_INSTRUMENT_XYLO       .text $00, $15, $91, $F6, $F6, $00, $00, $01, $07, $F6, $F6, $00
+>392e11		07 f6 f6 00
+>392e15		00 45 59 d3 f3 00 00 81		MIDIW31_INSTRUMENT_TUBEBELL   .text $00, $45, $59, $D3, $F3, $00, $00, $81, $87, $A3, $F3, $00
+>392e1d		87 a3 f3 00
+>392e21		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SANTUR     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392e29		00 00 00 00
+>392e2d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ORGAN1     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392e35		00 00 00 00
+>392e39		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ORGAN2     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392e41		00 00 00 00
+>392e45		00 70 44 aa 18 34 00 b1		MIDIW31_INSTRUMENT_ORGAN3     .text $00, $70, $44, $AA, $18, $34, $00, $B1, $07, $8A, $08, $00
+>392e4d		07 8a 08 00
+>392e51		00 23 93 97 23 34 01 b1		MIDIW31_INSTRUMENT_PIPEORG    .text $00, $23, $93, $97, $23, $34, $01, $B1, $07, $55, $14, $00
+>392e59		07 55 14 00
+>392e5d		00 61 13 97 04 30 01 b1		MIDIW31_INSTRUMENT_REEDORG    .text $00, $61, $13, $97, $04, $30, $01, $B1, $87, $55, $04, $00
+>392e65		87 55 04 00
+>392e69		00 24 48 98 2a 30 01 b1		MIDIW31_INSTRUMENT_ACORDIAN   .text $00, $24, $48, $98, $2A, $30, $01, $B1, $07, $46, $1A, $00
+>392e71		07 46 1a 00
+>392e75		00 61 13 91 06 00 01 21		MIDIW31_INSTRUMENT_HARMONIC   .text $00, $61, $13, $91, $06, $00, $01, $21, $07, $61, $07, $00
+>392e7d		07 61 07 00
+>392e81		00 21 13 71 06 00 00 a1		MIDIW31_INSTRUMENT_BANDNEON   .text $00, $21, $13, $71, $06, $00, $00, $A1, $90, $61, $07, $00
+>392e89		90 61 07 00
+>392e8d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_NYLONGT    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392e95		00 00 00 00
+>392e99		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_STEELGT    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392ea1		00 00 00 00
+>392ea5		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_JAZZGT     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392ead		00 00 00 00
+>392eb1		00 03 87 f6 22 36 01 21		MIDIW31_INSTRUMENT_CLEANGT    .text $00, $03, $87, $F6, $22, $36, $01, $21, $87, $F3, $F8, $00
+>392eb9		87 f3 f8 00
+>392ebd		00 03 47 f9 54 30 00 21		MIDIW31_INSTRUMENT_MUTEGT     .text $00, $03, $47, $F9, $54, $30, $00, $21, $07, $F6, $3A, $00
+>392ec5		07 f6 3a 00
+>392ec9		00 23 4a 91 41 38 01 21		MIDIW31_INSTRUMENT_OVERDGT    .text $00, $23, $4A, $91, $41, $38, $01, $21, $0C, $84, $19, $00
+>392ed1		0c 84 19 00
+>392ed5		00 23 4a 95 19 32 01 21		MIDIW31_INSTRUMENT_DISTGT     .text $00, $23, $4A, $95, $19, $32, $01, $21, $07, $94, $19, $00
+>392edd		07 94 19 00
+>392ee1		00 09 a1 20 4f 00 00 84		MIDIW31_INSTRUMENT_GTHARMS    .text $00, $09, $A1, $20, $4F, $00, $00, $84, $87, $D1, $F8, $00
+>392ee9		87 d1 f8 00
+>392eed		00 21 1e 94 06 00 00 a2		MIDIW31_INSTRUMENT_ACOUBASS   .text $00, $21, $1E, $94, $06, $00, $00, $A2, $07, $C3, $A6, $00
+>392ef5		07 c3 a6 00
+>392ef9		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FINGBASS   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392f01		00 00 00 00
+>392f05		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_PICKBASS   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392f0d		00 00 00 00
+>392f11		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FRETLESS   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392f19		00 00 00 00
+>392f1d		00 01 8b a1 9a 38 00 21		MIDIW31_INSTRUMENT_SLAPBAS1   .text $00, $01, $8B, $A1, $9A, $38, $00, $21, $47, $F2, $DF, $00
+>392f25		47 f2 df 00
+>392f29		00 21 8b a2 16 38 00 21		MIDIW31_INSTRUMENT_SLAPBAS2   .text $00, $21, $8B, $A2, $16, $38, $00, $21, $0F, $A1, $DF, $00
+>392f31		0f a1 df 00
+>392f35		00 31 8b f4 e8 3a 00 31		MIDIW31_INSTRUMENT_SYNBASS1   .text $00, $31, $8B, $F4, $E8, $3A, $00, $31, $07, $F1, $78, $00
+>392f3d		07 f1 78 00
+>392f41		00 31 12 f1 28 30 00 31		MIDIW31_INSTRUMENT_SYNBASS2   .text $00, $31, $12, $F1, $28, $30, $00, $31, $07, $F1, $18, $00
+>392f49		07 f1 18 00
+>392f4d		00 31 15 dd 13 00 01 21		MIDIW31_INSTRUMENT_VIOLIN     .text $00, $31, $15, $DD, $13, $00, $01, $21, $07, $56, $26, $00
+>392f55		07 56 26 00
+>392f59		00 31 16 dd 13 00 01 21		MIDIW31_INSTRUMENT_VIOLA      .text $00, $31, $16, $DD, $13, $00, $01, $21, $07, $66, $06, $00
+>392f61		07 66 06 00
+>392f65		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CELLO      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392f6d		00 00 00 00
+>392f71		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CONTRAB    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392f79		00 00 00 00
+>392f7d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_TREMSTR    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392f85		00 00 00 00
+>392f89		00 02 1a f5 75 30 01 01		MIDIW31_INSTRUMENT_PIZZ       .text $00, $02, $1A, $F5, $75, $30, $01, $01, $87, $85, $35, $00
+>392f91		87 85 35 00
+>392f95		00 02 1d f5 75 30 01 01		MIDIW31_INSTRUMENT_HARP       .text $00, $02, $1D, $F5, $75, $30, $01, $01, $87, $F3, $F4, $00
+>392f9d		87 f3 f4 00
+>392fa1		00 10 41 f5 05 32 01 11		MIDIW31_INSTRUMENT_TIMPANI    .text $00, $10, $41, $F5, $05, $32, $01, $11, $07, $F2, $C3, $00
+>392fa9		07 f2 c3 00
+>392fad		00 21 9b b1 25 3c 01 a2		MIDIW31_INSTRUMENT_STRINGS    .text $00, $21, $9B, $B1, $25, $3C, $01, $A2, $08, $72, $08, $00
+>392fb5		08 72 08 00
+>392fb9		00 a1 98 7f 03 00 01 21		MIDIW31_INSTRUMENT_SLOWSTR    .text $00, $A1, $98, $7F, $03, $00, $01, $21, $07, $3F, $07, $01
+>392fc1		07 3f 07 01
+>392fc5		00 a1 93 c1 12 00 00 61		MIDIW31_INSTRUMENT_SYNSTR1    .text $00, $A1, $93, $C1, $12, $00, $00, $61, $07, $4F, $05, $00
+>392fcd		07 4f 05 00
+>392fd1		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SYNSTR2    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392fd9		00 00 00 00
+>392fdd		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CHOIR      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392fe5		00 00 00 00
+>392fe9		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_OOHS       .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>392ff1		00 00 00 00
+>392ff5		00 71 57 54 05 3c 00 72		MIDIW31_INSTRUMENT_SYNVOX     .text $00, $71, $57, $54, $05, $3C, $00, $72, $07, $7A, $05, $00
+>392ffd		07 7a 05 00
+>393001		00 90 00 54 63 38 00 41		MIDIW31_INSTRUMENT_ORCHIT     .text $00, $90, $00, $54, $63, $38, $00, $41, $07, $A5, $45, $00
+>393009		07 a5 45 00
+>39300d		00 21 92 85 17 3c 00 21		MIDIW31_INSTRUMENT_TRUMPET    .text $00, $21, $92, $85, $17, $3C, $00, $21, $08, $8F, $09, $00
+>393015		08 8f 09 00
+>393019		00 21 94 75 17 32 00 21		MIDIW31_INSTRUMENT_TROMBONE   .text $00, $21, $94, $75, $17, $32, $00, $21, $0C, $8F, $09, $00
+>393021		0c 8f 09 00
+>393025		00 21 94 76 15 00 00 61		MIDIW31_INSTRUMENT_TUBA       .text $00, $21, $94, $76, $15, $00, $00, $61, $07, $82, $37, $00
+>39302d		07 82 37 00
+>393031		00 31 43 9e 17 00 01 21		MIDIW31_INSTRUMENT_MUTETRP    .text $00, $31, $43, $9E, $17, $00, $01, $21, $07, $62, $2C, $01
+>393039		07 62 2c 01
+>39303d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FRHORN     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393045		00 00 00 00
+>393049		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BRASS1     .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393051		00 00 00 00
+>393055		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SYNBRAS1   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>39305d		00 00 00 00
+>393061		00 21 4d 54 3c 38 00 21		MIDIW31_INSTRUMENT_SYNBRAS2   .text $00, $21, $4D, $54, $3C, $38, $00, $21, $07, $A6, $1C, $00
+>393069		07 a6 1c 00
+>39306d		00 31 8f 93 02 38 01 61		MIDIW31_INSTRUMENT_SOPSAX     .text $00, $31, $8F, $93, $02, $38, $01, $61, $07, $72, $0B, $00
+>393075		07 72 0b 00
+>393079		00 31 8e 93 03 38 01 61		MIDIW31_INSTRUMENT_ALTOSAX    .text $00, $31, $8E, $93, $03, $38, $01, $61, $07, $72, $09, $00
+>393081		07 72 09 00
+>393085		00 31 91 93 03 30 01 61		MIDIW31_INSTRUMENT_TENSAX     .text $00, $31, $91, $93, $03, $30, $01, $61, $07, $82, $09, $00
+>39308d		07 82 09 00
+>393091		00 31 8e 93 0f 00 01 61		MIDIW31_INSTRUMENT_BARISAX    .text $00, $31, $8E, $93, $0F, $00, $01, $61, $07, $72, $0F, $00
+>393099		07 72 0f 00
+>39309d		00 21 4b aa 16 00 01 21		MIDIW31_INSTRUMENT_OBOE       .text $00, $21, $4B, $AA, $16, $00, $01, $21, $07, $8F, $0A, $00
+>3930a5		07 8f 0a 00
+>3930a9		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ENGLHORN   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3930b1		00 00 00 00
+>3930b5		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BASSOON    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3930bd		00 00 00 00
+>3930c1		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CLARINET   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3930c9		00 00 00 00
+>3930cd		00 e1 1f 85 5f 30 00 e1		MIDIW31_INSTRUMENT_PICCOLO    .text $00, $E1, $1F, $85, $5F, $30, $00, $E1, $07, $65, $1A, $00
+>3930d5		07 65 1a 00
+>3930d9		00 e1 46 88 5f 30 00 e1		MIDIW31_INSTRUMENT_FLUTE1     .text $00, $E1, $46, $88, $5F, $30, $00, $E1, $07, $65, $1A, $00
+>3930e1		07 65 1a 00
+>3930e5		00 a1 9c 75 1f 32 00 21		MIDIW31_INSTRUMENT_RECORDER   .text $00, $A1, $9C, $75, $1F, $32, $00, $21, $07, $75, $0A, $00
+>3930ed		07 75 0a 00
+>3930f1		00 31 8b 84 58 30 00 21		MIDIW31_INSTRUMENT_PANFLUTE   .text $00, $31, $8B, $84, $58, $30, $00, $21, $07, $65, $1A, $00
+>3930f9		07 65 1a 00
+>3930fd		00 e1 4c 66 56 00 00 a1		MIDIW31_INSTRUMENT_BOTTLEB    .text $00, $E1, $4C, $66, $56, $00, $00, $A1, $07, $65, $26, $00
+>393105		07 65 26 00
+>393109		00 62 cb 76 46 00 00 a1		MIDIW31_INSTRUMENT_SHAKU      .text $00, $62, $CB, $76, $46, $00, $00, $A1, $07, $55, $36, $00
+>393111		07 55 36 00
+>393115		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_WHISTLE    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>39311d		00 00 00 00
+>393121		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_OCARINA    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393129		00 00 00 00
+>39312d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SQUARWAV   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393135		00 00 00 00
+>393139		00 21 0e ff 0f 30 01 21		MIDIW31_INSTRUMENT_SAWWAV     .text $00, $21, $0E, $FF, $0F, $30, $01, $21, $07, $FF, $0F, $01
+>393141		07 ff 0f 01
+>393145		00 22 46 86 55 30 00 21		MIDIW31_INSTRUMENT_SYNCALLI   .text $00, $22, $46, $86, $55, $30, $00, $21, $87, $64, $18, $00
+>39314d		87 64 18 00
+>393151		00 21 45 66 12 30 00 a1		MIDIW31_INSTRUMENT_CHIFLEAD   .text $00, $21, $45, $66, $12, $30, $00, $A1, $07, $96, $0A, $00
+>393159		07 96 0a 00
+>39315d		00 21 8b 92 2a 34 01 22		MIDIW31_INSTRUMENT_CHARANG    .text $00, $21, $8B, $92, $2A, $34, $01, $22, $07, $91, $2A, $00
+>393165		07 91 2a 00
+>393169		00 a2 9e df 05 00 00 61		MIDIW31_INSTRUMENT_SOLOVOX    .text $00, $A2, $9E, $DF, $05, $00, $00, $61, $47, $6F, $07, $00
+>393171		47 6f 07 00
+>393175		00 20 1a ef 01 00 00 60		MIDIW31_INSTRUMENT_FIFTHSAW   .text $00, $20, $1A, $EF, $01, $00, $00, $60, $07, $8F, $06, $02
+>39317d		07 8f 06 02
+>393181		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BASSLEAD   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393189		00 00 00 00
+>39318d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_FANTASIA   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393195		00 00 00 00
+>393199		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_WARMPAD    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3931a1		00 00 00 00
+>3931a5		00 61 17 91 34 3c 00 61		MIDIW31_INSTRUMENT_POLYSYN    .text $00, $61, $17, $91, $34, $3C, $00, $61, $07, $55, $16, $00
+>3931ad		07 55 16 00
+>3931b1		00 71 5d 54 01 30 00 72		MIDIW31_INSTRUMENT_SPACEVOX   .text $00, $71, $5D, $54, $01, $30, $00, $72, $07, $6A, $03, $00
+>3931b9		07 6a 03 00
+>3931bd		00 21 97 21 43 38 00 a2		MIDIW31_INSTRUMENT_BOWEDGLS   .text $00, $21, $97, $21, $43, $38, $00, $A2, $07, $42, $35, $00
+>3931c5		07 42 35 00
+>3931c9		00 a1 1c a1 77 30 01 21		MIDIW31_INSTRUMENT_METALPAD   .text $00, $A1, $1C, $A1, $77, $30, $01, $21, $07, $31, $47, $01
+>3931d1		07 31 47 01
+>3931d5		00 21 89 11 33 00 00 61		MIDIW31_INSTRUMENT_HALOPAD    .text $00, $21, $89, $11, $33, $00, $00, $61, $0A, $42, $25, $00
+>3931dd		0a 42 25 00
+>3931e1		00 a1 15 11 47 00 01 21		MIDIW31_INSTRUMENT_SWEEPPAD   .text $00, $A1, $15, $11, $47, $00, $01, $21, $07, $CF, $07, $00
+>3931e9		07 cf 07 00
+>3931ed		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_ICERAIN    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3931f5		00 00 00 00
+>3931f9		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SOUNDTRK   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393201		00 00 00 00
+>393205		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_CRYSTAL    .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>39320d		00 00 00 00
+>393211		00 22 92 b1 81 3c 00 61		MIDIW31_INSTRUMENT_ATMOSPH    .text $00, $22, $92, $B1, $81, $3C, $00, $61, $8A, $F2, $26, $00
+>393219		8a f2 26 00
+>39321d		00 41 4d f1 51 30 01 42		MIDIW31_INSTRUMENT_BRIGHT     .text $00, $41, $4D, $F1, $51, $30, $01, $42, $07, $F2, $F5, $00
+>393225		07 f2 f5 00
+>393229		00 61 94 11 51 36 01 a3		MIDIW31_INSTRUMENT_GOBLIN     .text $00, $61, $94, $11, $51, $36, $01, $A3, $87, $11, $13, $00
+>393231		87 11 13 00
+>393235		00 61 8c 11 31 3a 00 a1		MIDIW31_INSTRUMENT_ECHODROP   .text $00, $61, $8C, $11, $31, $3A, $00, $A1, $87, $1D, $03, $00
+>39323d		87 1d 03 00
+>393241		00 a4 4c f3 73 00 01 61		MIDIW31_INSTRUMENT_STARTHEM   .text $00, $A4, $4C, $F3, $73, $00, $01, $61, $07, $81, $23, $00
+>393249		07 81 23 00
+>39324d		00 02 85 d2 53 00 00 07		MIDIW31_INSTRUMENT_SITAR      .text $00, $02, $85, $D2, $53, $00, $00, $07, $0A, $F2, $F6, $01
+>393255		0a f2 f6 01
+>393259		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BANJO      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393261		00 00 00 00
+>393265		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_SHAMISEN   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>39326d		00 00 00 00
+>393271		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_KOTO       .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393279		00 00 00 00
+>39327d		00 04 4f fa 56 3c 00 01		MIDIW31_INSTRUMENT_KALIMBA    .text $00, $04, $4F, $FA, $56, $3C, $00, $01, $07, $C2, $05, $00
+>393285		07 c2 05 00
+>393289		00 21 49 7c 20 36 00 22		MIDIW31_INSTRUMENT_BAGPIPE    .text $00, $21, $49, $7C, $20, $36, $00, $22, $07, $6F, $0C, $01
+>393291		07 6f 0c 01
+>393295		00 31 85 dd 33 3a 01 21		MIDIW31_INSTRUMENT_FIDDLE     .text $00, $31, $85, $DD, $33, $3A, $01, $21, $07, $56, $16, $00
+>39329d		07 56 16 00
+>3932a1		00 20 04 da 05 30 02 21		MIDIW31_INSTRUMENT_SHANNAI    .text $00, $20, $04, $DA, $05, $30, $02, $21, $88, $8F, $0B, $00
+>3932a9		88 8f 0b 00
+>3932ad		00 05 6a f1 e5 00 00 03		MIDIW31_INSTRUMENT_TINKLBEL   .text $00, $05, $6A, $F1, $E5, $00, $00, $03, $87, $C3, $E5, $00
+>3932b5		87 c3 e5 00
+>3932b9		00 07 15 ec 26 00 00 02		MIDIW31_INSTRUMENT_AGOGO      .text $00, $07, $15, $EC, $26, $00, $00, $02, $07, $F8, $16, $00
+>3932c1		07 f8 16 00
+>3932c5		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_STEELDRM   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3932cd		00 00 00 00
+>3932d1		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_WOODBLOK   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3932d9		00 00 00 00
+>3932dd		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_TAIKO      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3932e5		00 00 00 00
+>3932e9		00 11 41 f8 47 34 02 10		MIDIW31_INSTRUMENT_MELOTOM    .text $00, $11, $41, $F8, $47, $34, $02, $10, $0A, $F3, $03, $00
+>3932f1		0a f3 03 00
+>3932f5		00 01 8e f1 06 3e 02 10		MIDIW31_INSTRUMENT_SYNDRUM    .text $00, $01, $8E, $F1, $06, $3E, $02, $10, $07, $F3, $02, $00
+>3932fd		07 f3 02 00
+>393301		00 0e 00 1f 00 3e 00 c0		MIDIW31_INSTRUMENT_REVRSCYM   .text $00, $0E, $00, $1F, $00, $3E, $00, $C0, $07, $1F, $FF, $03
+>393309		07 1f ff 03
+>39330d		00 06 80 f8 24 38 00 03		MIDIW31_INSTRUMENT_FRETNOIS   .text $00, $06, $80, $F8, $24, $38, $00, $03, $8F, $56, $84, $02
+>393315		8f 56 84 02
+>393319		00 0e 00 f8 00 00 00 d0		MIDIW31_INSTRUMENT_BRTHNOIS   .text $00, $0E, $00, $F8, $00, $00, $00, $D0, $0C, $34, $04, $03
+>393321		0c 34 04 03
+>393325		00 0e 00 f6 00 00 00 c0		MIDIW31_INSTRUMENT_SEASHORE   .text $00, $0E, $00, $F6, $00, $00, $00, $C0, $07, $1F, $02, $03
+>39332d		07 1f 02 03
+>393331		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_BIRDS      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393339		00 00 00 00
+>39333d		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_TELEPHON   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393345		00 00 00 00
+>393349		00 00 00 00 00 00 00 00		MIDIW31_INSTRUMENT_HELICOPT   .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>393351		00 00 00 00
+>393355		00 26 00 ff 01 3e 00 e4		MIDIW31_INSTRUMENT_APPLAUSE   .text $00, $26, $00, $FF, $01, $3E, $00, $E4, $07, $12, $16, $01
+>39335d		07 12 16 01
+>393361		00 00 00 f3 f0 3e 00 00		MIDIW31_INSTRUMENT_GUNSHOT    .text $00, $00, $00, $F3, $F0, $3E, $00, $00, $07, $F6, $C9, $02
+>393369		07 f6 c9 02
+>39336d		6d 2d 39 00 79 2d 39 00		midiInstrumentsw31 .dword MIDIW31_INSTRUMENT_PIANO1,   MIDIW31_INSTRUMENT_PIANO2,   MIDIW31_INSTRUMENT_PIANO3,   MIDIW31_INSTRUMENT_HONKTONK, MIDIW31_INSTRUMENT_EP1, MIDIW31_INSTRUMENT_EP2
+>393375		85 2d 39 00 91 2d 39 00 9d 2d 39 00 a9 2d 39 00
+>393385		b5 2d 39 00 c1 2d 39 00		                   .dword MIDIW31_INSTRUMENT_HARPSIC,  MIDIW31_INSTRUMENT_CLAVIC,   MIDIW31_INSTRUMENT_CELESTA,  MIDIW31_INSTRUMENT_GLOCK,    MIDIW31_INSTRUMENT_MUSICBOX, MIDIW31_INSTRUMENT_VIBES
+>39338d		cd 2d 39 00 d9 2d 39 00 e5 2d 39 00 f1 2d 39 00
+>39339d		fd 2d 39 00 09 2e 39 00			                 .dword MIDIW31_INSTRUMENT_MARIMBA,  MIDIW31_INSTRUMENT_XYLO,     MIDIW31_INSTRUMENT_TUBEBELL, MIDIW31_INSTRUMENT_SANTUR,   MIDIW31_INSTRUMENT_ORGAN1,   MIDIW31_INSTRUMENT_ORGAN2
+>3933a5		15 2e 39 00 21 2e 39 00 2d 2e 39 00 39 2e 39 00
+>3933b5		45 2e 39 00 51 2e 39 00			                 .dword MIDIW31_INSTRUMENT_ORGAN3,   MIDIW31_INSTRUMENT_PIPEORG,  MIDIW31_INSTRUMENT_REEDORG,  MIDIW31_INSTRUMENT_ACORDIAN, MIDIW31_INSTRUMENT_HARMONIC, MIDIW31_INSTRUMENT_BANDNEON
+>3933bd		5d 2e 39 00 69 2e 39 00 75 2e 39 00 81 2e 39 00
+>3933cd		8d 2e 39 00 99 2e 39 00		                     .dword MIDIW31_INSTRUMENT_NYLONGT,  MIDIW31_INSTRUMENT_STEELGT,  MIDIW31_INSTRUMENT_JAZZGT,   MIDIW31_INSTRUMENT_CLEANGT,  MIDIW31_INSTRUMENT_MUTEGT,   MIDIW31_INSTRUMENT_OVERDGT
+>3933d5		a5 2e 39 00 b1 2e 39 00 bd 2e 39 00 c9 2e 39 00
+>3933e5		d5 2e 39 00 e1 2e 39 00			                 .dword MIDIW31_INSTRUMENT_DISTGT,   MIDIW31_INSTRUMENT_GTHARMS,  MIDIW31_INSTRUMENT_ACOUBASS, MIDIW31_INSTRUMENT_FINGBASS, MIDIW31_INSTRUMENT_PICKBASS, MIDIW31_INSTRUMENT_FRETLESS
+>3933ed		ed 2e 39 00 f9 2e 39 00 05 2f 39 00 11 2f 39 00
+>3933fd		1d 2f 39 00 29 2f 39 00			                 .dword MIDIW31_INSTRUMENT_SLAPBAS1, MIDIW31_INSTRUMENT_SLAPBAS2, MIDIW31_INSTRUMENT_SYNBASS1, MIDIW31_INSTRUMENT_SYNBASS2, MIDIW31_INSTRUMENT_VIOLIN,   MIDIW31_INSTRUMENT_VIOLA
+>393405		35 2f 39 00 41 2f 39 00 4d 2f 39 00 59 2f 39 00
+>393415		65 2f 39 00 71 2f 39 00			                 .dword MIDIW31_INSTRUMENT_CELLO,    MIDIW31_INSTRUMENT_CONTRAB,  MIDIW31_INSTRUMENT_TREMSTR,  MIDIW31_INSTRUMENT_PIZZ,     MIDIW31_INSTRUMENT_HARP,     MIDIW31_INSTRUMENT_TIMPANI
+>39341d		7d 2f 39 00 89 2f 39 00 95 2f 39 00 a1 2f 39 00
+>39342d		ad 2f 39 00 b9 2f 39 00			                 .dword MIDIW31_INSTRUMENT_STRINGS,  MIDIW31_INSTRUMENT_SLOWSTR,  MIDIW31_INSTRUMENT_SYNSTR1,  MIDIW31_INSTRUMENT_SYNSTR2,  MIDIW31_INSTRUMENT_CHOIR,    MIDIW31_INSTRUMENT_OOHS
+>393435		c5 2f 39 00 d1 2f 39 00 dd 2f 39 00 e9 2f 39 00
+>393445		f5 2f 39 00 01 30 39 00			                 .dword MIDIW31_INSTRUMENT_SYNVOX,   MIDIW31_INSTRUMENT_ORCHIT,   MIDIW31_INSTRUMENT_TRUMPET,  MIDIW31_INSTRUMENT_TROMBONE, MIDIW31_INSTRUMENT_TUBA,     MIDIW31_INSTRUMENT_MUTETRP
+>39344d		0d 30 39 00 19 30 39 00 25 30 39 00 31 30 39 00
+>39345d		3d 30 39 00 49 30 39 00			                 .dword MIDIW31_INSTRUMENT_FRHORN,   MIDIW31_INSTRUMENT_BRASS1,   MIDIW31_INSTRUMENT_SYNBRAS1, MIDIW31_INSTRUMENT_SYNBRAS2, MIDIW31_INSTRUMENT_SOPSAX,   MIDIW31_INSTRUMENT_ALTOSAX
+>393465		55 30 39 00 61 30 39 00 6d 30 39 00 79 30 39 00
+>393475		85 30 39 00 91 30 39 00			                 .dword MIDIW31_INSTRUMENT_TENSAX,   MIDIW31_INSTRUMENT_BARISAX,  MIDIW31_INSTRUMENT_OBOE,     MIDIW31_INSTRUMENT_ENGLHORN, MIDIW31_INSTRUMENT_BASSOON,  MIDIW31_INSTRUMENT_CLARINET
+>39347d		9d 30 39 00 a9 30 39 00 b5 30 39 00 c1 30 39 00
+>39348d		cd 30 39 00 d9 30 39 00			                 .dword MIDIW31_INSTRUMENT_PICCOLO,  MIDIW31_INSTRUMENT_FLUTE1,   MIDIW31_INSTRUMENT_RECORDER, MIDIW31_INSTRUMENT_PANFLUTE, MIDIW31_INSTRUMENT_BOTTLEB,  MIDIW31_INSTRUMENT_SHAKU
+>393495		e5 30 39 00 f1 30 39 00 fd 30 39 00 09 31 39 00
+>3934a5		15 31 39 00 21 31 39 00			                 .dword MIDIW31_INSTRUMENT_WHISTLE,  MIDIW31_INSTRUMENT_OCARINA,  MIDIW31_INSTRUMENT_SQUARWAV, MIDIW31_INSTRUMENT_SAWWAV,   MIDIW31_INSTRUMENT_SYNCALLI, MIDIW31_INSTRUMENT_CHIFLEAD
+>3934ad		2d 31 39 00 39 31 39 00 45 31 39 00 51 31 39 00
+>3934bd		5d 31 39 00 69 31 39 00			                 .dword MIDIW31_INSTRUMENT_CHARANG,  MIDIW31_INSTRUMENT_SOLOVOX,  MIDIW31_INSTRUMENT_FIFTHSAW, MIDIW31_INSTRUMENT_BASSLEAD, MIDIW31_INSTRUMENT_FANTASIA, MIDIW31_INSTRUMENT_WARMPAD
+>3934c5		75 31 39 00 81 31 39 00 8d 31 39 00 99 31 39 00
+>3934d5		a5 31 39 00 b1 31 39 00			                 .dword MIDIW31_INSTRUMENT_POLYSYN,  MIDIW31_INSTRUMENT_SPACEVOX, MIDIW31_INSTRUMENT_BOWEDGLS, MIDIW31_INSTRUMENT_METALPAD, MIDIW31_INSTRUMENT_HALOPAD,  MIDIW31_INSTRUMENT_SWEEPPAD
+>3934dd		bd 31 39 00 c9 31 39 00 d5 31 39 00 e1 31 39 00
+>3934ed		ed 31 39 00 f9 31 39 00			                 .dword MIDIW31_INSTRUMENT_ICERAIN,  MIDIW31_INSTRUMENT_SOUNDTRK, MIDIW31_INSTRUMENT_CRYSTAL,  MIDIW31_INSTRUMENT_ATMOSPH,  MIDIW31_INSTRUMENT_BRIGHT,   MIDIW31_INSTRUMENT_GOBLIN
+>3934f5		05 32 39 00 11 32 39 00 1d 32 39 00 29 32 39 00
+>393505		35 32 39 00 41 32 39 00			                 .dword MIDIW31_INSTRUMENT_ECHODROP, MIDIW31_INSTRUMENT_STARTHEM, MIDIW31_INSTRUMENT_SITAR,    MIDIW31_INSTRUMENT_BANJO,    MIDIW31_INSTRUMENT_SHAMISEN, MIDIW31_INSTRUMENT_KOTO
+>39350d		4d 32 39 00 59 32 39 00 65 32 39 00 71 32 39 00
+>39351d		7d 32 39 00 89 32 39 00			                 .dword MIDIW31_INSTRUMENT_KALIMBA,  MIDIW31_INSTRUMENT_BAGPIPE,  MIDIW31_INSTRUMENT_FIDDLE,   MIDIW31_INSTRUMENT_SHANNAI,  MIDIW31_INSTRUMENT_TINKLBEL, MIDIW31_INSTRUMENT_AGOGO
+>393525		95 32 39 00 a1 32 39 00 ad 32 39 00 b9 32 39 00
+>393535		c5 32 39 00 d1 32 39 00			                 .dword MIDIW31_INSTRUMENT_STEELDRM, MIDIW31_INSTRUMENT_WOODBLOK, MIDIW31_INSTRUMENT_TAIKO,    MIDIW31_INSTRUMENT_MELOTOM,  MIDIW31_INSTRUMENT_SYNDRUM,  MIDIW31_INSTRUMENT_REVRSCYM
+>39353d		dd 32 39 00 e9 32 39 00 f5 32 39 00 01 33 39 00
+>39354d		0d 33 39 00 19 33 39 00			                 .dword MIDIW31_INSTRUMENT_FRETNOIS, MIDIW31_INSTRUMENT_BRTHNOIS, MIDIW31_INSTRUMENT_SEASHORE, MIDIW31_INSTRUMENT_BIRDS,    MIDIW31_INSTRUMENT_TELEPHON, MIDIW31_INSTRUMENT_HELICOPT
+>393555		25 33 39 00 31 33 39 00 3d 33 39 00 49 33 39 00
+>393565		55 33 39 00 61 33 39 00			                 .dword MIDIW31_INSTRUMENT_APPLAUSE, MIDIW31_INSTRUMENT_GUNSHOT
+
+;******  Return to file: src\Libraries/OPL2_Library.asm
+
+>39356d		3c 42 44 45 47 49 4b 4c		NOTE_INTRO  .byte  $3C, $42, $44, $45, $47, $49, $4B, $4C
+.393575						IOPL2_TONE_TEST
+.393575		e2 20		sep #$20	                SEP #$20        ; set A short
+.393577		c2 10		rep #$10	                REP #$10        ; set X long
+.393579		a2 00 00	ldx #$0000	                LDX #0
+.39357c						OPL2_TONE_TESTING_L1
+.39357c		bf 6d 35 39	lda $39356d,x	                LDA NOTE_INTRO, X
+.393580		29 0f		and #$0f	                AND #$F
+.393582		85 30		sta $30		                STA OPL2_NOTE ; start at C
+.393584		bf 6d 35 39	lda $39356d,x	                LDA NOTE_INTRO, X
+.393588		29 70		and #$70	                AND #$70
+.39358a		4a		lsr a		                LSR A
+.39358b		4a		lsr a		                LSR A
+.39358c		4a		lsr a		                LSR A
+.39358d		4a		lsr a		                LSR A
+.39358e		85 31		sta $31		                STA OPL2_OCTAVE
+.393590		8a		txa		                TXA
+.393591		29 03		and #$03	                AND #$03        ; replace modulo 3 -  play each note on a different channel
+.393593		85 27		sta $27		                STA OPL2_CHANNEL
+.393595		22 65 37 39	jsl $393765	                JSL OPL2_PLAYNOTE
+.393599		a0 00 00	ldy #$0000	                LDY #$0000
+.39359c						OPL2_TONE_TESTING_L2
+.39359c		ea		nop		                NOP
+.39359d		ea		nop		                NOP
+.39359e		ea		nop		                NOP
+.39359f		ea		nop		                NOP
+.3935a0		c8		iny		                INY
+.3935a1		c0 ff ff	cpy #$ffff	                CPY #$FFFF
+.3935a4		d0 f6		bne $39359c	                BNE OPL2_TONE_TESTING_L2
+.3935a6		e8		inx		                INX
+.3935a7		e0 08 00	cpx #$0008	                CPX #8
+.3935aa		d0 d0		bne $39357c	                BNE OPL2_TONE_TESTING_L1
+.3935ac		6b		rtl		                RTL
+.3935ad						OPL2_INIT
+.3935ad		c2 20		rep #$20	                REP #$20        ; set A long
+.3935af		a9 00 00	lda #$0000	                LDA #$0000
+.3935b2		85 28		sta $28		                STA OPL2_REG_REGION
+.3935b4		85 2a		sta $2a		                STA OPL2_REG_OFFSET
+.3935b6		85 30		sta $30		                STA OPL2_NOTE
+.3935b8		85 32		sta $32		                STA OPL2_PARAMETER0
+.3935ba		85 34		sta $34		                STA OPL2_PARAMETER2
+.3935bc		a9 37 15	lda #$1537	                LDA #<>INSTRUMENT_ACCORDN
+.3935bf		85 50		sta $50		                STA RAD_ADDR
+.3935c1		a9 39 00	lda #$0039	                LDA #<`INSTRUMENT_ACCORDN
+.3935c4		85 52		sta $52		                STA RAD_ADDR + 2
+.3935c6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3935c8		6b		rtl		                RTL
+.3935c9						OPL2_Reset
+.3935c9		6b		rtl		                RTL
+.3935ca						OPL2_Get_FrequencyBlock
+.3935ca		6b		rtl		                RTL
+.3935cb						OPL2_GET_REGISTER
+.3935cb		48		pha		                PHA             ; begin setdp macro
+.3935cc		08		php		                PHP
+.3935cd		c2 20		rep #$20	                REP #$20        ; set A long
+.3935cf		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3935d2		5b		tcd		                TCD
+.3935d3		28		plp		                PLP
+.3935d4		68		pla		                PLA             ; end setdp macro
+.3935d5		c2 20		rep #$20	                REP #$20        ; set A long
+.3935d7		18		clc		              CLC
+.3935d8		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.3935db		65 32		adc $32		              ADC OPL2_PARAMETER0
+.3935dd		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.3935df		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.3935e2		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.3935e4		e2 20		sep #$20	                SEP #$20        ; set A short
+.3935e6		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.3935e8		6b		rtl		              RTL
+.3935e9						OPL2_GET_WAVEFORM_SELECT
+.3935e9		48		pha		                PHA             ; begin setdp macro
+.3935ea		08		php		                PHP
+.3935eb		c2 20		rep #$20	                REP #$20        ; set A long
+.3935ed		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3935f0		5b		tcd		                TCD
+.3935f1		28		plp		                PLP
+.3935f2		68		pla		                PLA             ; end setdp macro
+.3935f3		c2 20		rep #$20	                REP #$20        ; set A long
+.3935f5		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.3935f8		69 01 00	adc #$0001	              ADC #$0001
+.3935fb		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.3935fd		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393600		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393602		e2 20		sep #$20	                SEP #$20        ; set A short
+.393604		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393606		29 20		and #$20	              AND #$20
+.393608		6b		rtl		              RTL
+.393609						OPL2_GET_SCALINGLEVEL
+.393609		48		pha		                PHA             ; begin setdp macro
+.39360a		08		php		                PHP
+.39360b		c2 20		rep #$20	                REP #$20        ; set A long
+.39360d		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393610		5b		tcd		                TCD
+.393611		28		plp		                PLP
+.393612		68		pla		                PLA             ; end setdp macro
+.393613		c2 20		rep #$20	                REP #$20        ; set A long
+.393615		a9 40 00	lda #$0040	              LDA #$0040  ;
+.393618		85 28		sta $28		              STA OPL2_REG_REGION
+.39361a		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.39361d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39361f		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393621		29 c0		and #$c0	              AND #$C0
+.393623		4a		lsr a		              LSR A
+.393624		4a		lsr a		              LSR A
+.393625		4a		lsr a		              LSR A
+.393626		4a		lsr a		              LSR A
+.393627		4a		lsr a		              LSR A
+.393628		4a		lsr a		              LSR A
+.393629		6b		rtl		              RTL
+.39362a						OPL2_GET_BLOCK
+.39362a		48		pha		                PHA             ; begin setdp macro
+.39362b		08		php		                PHP
+.39362c		c2 20		rep #$20	                REP #$20        ; set A long
+.39362e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393631		5b		tcd		                TCD
+.393632		28		plp		                PLP
+.393633		68		pla		                PLA             ; end setdp macro
+.393634		e2 20		sep #$20	                SEP #$20        ; set A short
+.393636		18		clc		              CLC
+.393637		a5 27		lda $27		              LDA OPL2_CHANNEL
+.393639		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
+.39363b		69 b0		adc #$b0	              ADC #$B0
+.39363d		85 2a		sta $2a		              STA OPL2_REG_OFFSET
+.39363f		a9 00		lda #$00	              LDA #$00
+.393641		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
+.393643		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393645		18		clc		              CLC
+.393646		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.393649		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
+.39364b		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.39364d		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393650		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393652		e2 20		sep #$20	                SEP #$20        ; set A short
+.393654		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393656		29 1c		and #$1c	              AND #$1C
+.393658		4a		lsr a		              LSR A
+.393659		4a		lsr a		              LSR A
+.39365a		6b		rtl		              RTL
+.39365b						OPL2_GET_KEYON
+.39365b		48		pha		                PHA             ; begin setdp macro
+.39365c		08		php		                PHP
+.39365d		c2 20		rep #$20	                REP #$20        ; set A long
+.39365f		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393662		5b		tcd		                TCD
+.393663		28		plp		                PLP
+.393664		68		pla		                PLA             ; end setdp macro
+.393665		e2 20		sep #$20	                SEP #$20        ; set A short
+.393667		18		clc		              CLC
+.393668		a5 27		lda $27		              LDA OPL2_CHANNEL
+.39366a		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
+.39366c		69 b0		adc #$b0	              ADC #$B0
+.39366e		85 2a		sta $2a		              STA OPL2_REG_OFFSET
+.393670		a9 00		lda #$00	              LDA #$00
+.393672		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
+.393674		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393676		18		clc		              CLC
+.393677		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.39367a		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
+.39367c		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.39367e		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393681		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393683		e2 20		sep #$20	                SEP #$20        ; set A short
+.393685		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393687		29 20		and #$20	              AND #$20
+.393689		6b		rtl		              RTL
+.39368a						OPL2_GET_FEEDBACK
+.39368a		48		pha		                PHA             ; begin setdp macro
+.39368b		08		php		                PHP
+.39368c		c2 20		rep #$20	                REP #$20        ; set A long
+.39368e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393691		5b		tcd		                TCD
+.393692		28		plp		                PLP
+.393693		68		pla		                PLA             ; end setdp macro
+.393694		e2 20		sep #$20	                SEP #$20        ; set A short
+.393696		18		clc		              CLC
+.393697		a5 27		lda $27		              LDA OPL2_CHANNEL
+.393699		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
+.39369b		69 c0		adc #$c0	              ADC #$C0
+.39369d		85 2a		sta $2a		              STA OPL2_REG_OFFSET
+.39369f		a9 00		lda #$00	              LDA #$00
+.3936a1		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
+.3936a3		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3936a5		18		clc		              CLC
+.3936a6		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.3936a9		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
+.3936ab		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.3936ad		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.3936b0		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.3936b2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3936b4		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.3936b6		29 e0		and #$e0	              AND #$E0
+.3936b8		4a		lsr a		              LSR
+.3936b9		6b		rtl		              RTL
+.3936ba						OPL2_GET_SYNTHMODE
+.3936ba		48		pha		                PHA             ; begin setdp macro
+.3936bb		08		php		                PHP
+.3936bc		c2 20		rep #$20	                REP #$20        ; set A long
+.3936be		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3936c1		5b		tcd		                TCD
+.3936c2		28		plp		                PLP
+.3936c3		68		pla		                PLA             ; end setdp macro
+.3936c4		e2 20		sep #$20	                SEP #$20        ; set A short
+.3936c6		18		clc		              CLC
+.3936c7		a5 27		lda $27		              LDA OPL2_CHANNEL
+.3936c9		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
+.3936cb		69 c0		adc #$c0	              ADC #$C0
+.3936cd		85 2a		sta $2a		              STA OPL2_REG_OFFSET
+.3936cf		a9 00		lda #$00	              LDA #$00
+.3936d1		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
+.3936d3		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3936d5		18		clc		              CLC
+.3936d6		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.3936d9		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
+.3936db		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.3936dd		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.3936e0		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.3936e2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3936e4		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.3936e6		29 01		and #$01	              AND #$01
+.3936e8		6b		rtl		              RTL
+.3936e9						OPL2_GET_DEEPTREMOLO
+.3936e9		48		pha		                PHA             ; begin setdp macro
+.3936ea		08		php		                PHP
+.3936eb		c2 20		rep #$20	                REP #$20        ; set A long
+.3936ed		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3936f0		5b		tcd		                TCD
+.3936f1		28		plp		                PLP
+.3936f2		68		pla		                PLA             ; end setdp macro
+.3936f3		c2 20		rep #$20	                REP #$20        ; set A long
+.3936f5		a9 bd 00	lda #$00bd	              LDA #$00BD;
+.3936f8		85 28		sta $28		              STA OPL2_REG_REGION
+.3936fa		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.3936fd		e2 20		sep #$20	                SEP #$20        ; set A short
+.3936ff		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393701		29 80		and #$80	              AND #$80
+.393703		6b		rtl		              RTL
+.393704						OPL2_GET_DEEPVIBRATO
+.393704		48		pha		                PHA             ; begin setdp macro
+.393705		08		php		                PHP
+.393706		c2 20		rep #$20	                REP #$20        ; set A long
+.393708		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.39370b		5b		tcd		                TCD
+.39370c		28		plp		                PLP
+.39370d		68		pla		                PLA             ; end setdp macro
+.39370e		c2 20		rep #$20	                REP #$20        ; set A long
+.393710		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.393713		69 bd 00	adc #$00bd	              ADC #$00BD
+.393716		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393718		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.39371b		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.39371d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39371f		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393721		29 40		and #$40	              AND #$40
+.393723		6b		rtl		              RTL
+.393724						OPL2_GET_PERCUSSION
+.393724		48		pha		                PHA             ; begin setdp macro
+.393725		08		php		                PHP
+.393726		c2 20		rep #$20	                REP #$20        ; set A long
+.393728		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.39372b		5b		tcd		                TCD
+.39372c		28		plp		                PLP
+.39372d		68		pla		                PLA             ; end setdp macro
+.39372e		c2 20		rep #$20	                REP #$20        ; set A long
+.393730		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.393733		69 bd 00	adc #$00bd	              ADC #$00BD
+.393736		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393738		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.39373b		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.39373d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39373f		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393741		29 20		and #$20	              AND #$20
+.393743		6b		rtl		              RTL
+.393744						OPL2_GET_DRUMS
+.393744		48		pha		                PHA             ; begin setdp macro
+.393745		08		php		                PHP
+.393746		c2 20		rep #$20	                REP #$20        ; set A long
+.393748		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.39374b		5b		tcd		                TCD
+.39374c		28		plp		                PLP
+.39374d		68		pla		                PLA             ; end setdp macro
+.39374e		c2 20		rep #$20	                REP #$20        ; set A long
+.393750		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.393753		69 bd 00	adc #$00bd	              ADC #$00BD
+.393756		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393758		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.39375b		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.39375d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39375f		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393761		29 1f		and #$1f	              AND #$1F
+.393763		6b		rtl		              RTL
+.393764						OPL2_Get_WaveForm
+.393764		6b		rtl		                RTL
+.393765						OPL2_PLAYNOTE
+.393765		48		pha		                PHA             ; begin setdp macro
+.393766		08		php		                PHP
+.393767		c2 20		rep #$20	                REP #$20        ; set A long
+.393769		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.39376c		5b		tcd		                TCD
+.39376d		28		plp		                PLP
+.39376e		68		pla		                PLA             ; end setdp macro
+.39376f		e2 20		sep #$20	                SEP #$20        ; set A short
+.393771		da		phx		                PHX
+.393772		a9 00		lda #$00	                LDA #$00
+.393774		85 32		sta $32		                STA OPL2_PARAMETER0 ; Set Keyon False
+.393776		20 4d 3d	jsr $393d4d	                JSR OPL2_SET_KEYON
+.393779		20 12 3d	jsr $393d12	                JSR OPL2_SET_BLOCK  ; OPL2_SET_BLOCK Already to OPL2_OCTAVE
+.39377c		e2 10		sep #$10	                SEP #$10        ; set X short
+.39377e		a5 30		lda $30		                LDA OPL2_NOTE
+.393780		3a		dec a		                DEC A
+.393781		0a		asl a		                ASL A
+.393782		aa		tax		                TAX
+.393783		bf fc 14 39	lda $3914fc,x	                LDA @lnoteFNumbers,X
+.393787		85 32		sta $32		                STA OPL2_PARAMETER0 ; Store the 8it in Param OPL2_PARAMETER0
+.393789		e8		inx		                INX
+.39378a		bf fc 14 39	lda $3914fc,x	                LDA @lnoteFNumbers,X
+.39378e		85 33		sta $33		                STA OPL2_PARAMETER1 ; Store the 8bit in Param OPL2_PARAMETER1
+.393790		22 90 3c 39	jsl $393c90	                JSL OPL2_SET_FNUMBER
+.393794		a9 01		lda #$01	                LDA #$01
+.393796		85 32		sta $32		                STA OPL2_PARAMETER0 ; Set Keyon False
+.393798		20 4d 3d	jsr $393d4d	                JSR OPL2_SET_KEYON
+.39379b		c2 10		rep #$10	                REP #$10        ; set X long
+.39379d		fa		plx		                PLX
+.39379e		6b		rtl		                RTL
+.39379f						OPL2_PLAYDRUM
+.39379f		6b		rtl		                RTL
+.3937a0						OPL2_SET_INSTRUMENT
+.3937a0		48		pha		                PHA             ; begin setdp macro
+.3937a1		08		php		                PHP
+.3937a2		c2 20		rep #$20	                REP #$20        ; set A long
+.3937a4		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3937a7		5b		tcd		                TCD
+.3937a8		28		plp		                PLP
+.3937a9		68		pla		                PLA             ; end setdp macro
+.3937aa		38		sec		              SEC ; Set the WaveFormSelect to True
+.3937ab		22 8e 39 39	jsl $39398e	              JSL OPL2_SET_WAVEFORMSELECT;
+.3937af		e2 20		sep #$20	                SEP #$20        ; set A short
+.3937b1		c2 10		rep #$10	                REP #$10        ; set X long
+.3937b3		a0 00 00	ldy #$0000	              LDY #$0000
+.3937b6		a2 00 00	ldx #$0000	              LDX #$0000
+.3937b9		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO],Y ; Pointer Location 0 in Instrument Profile
+.3937bb		85 35		sta $35		              STA OPL2_PARAMETER3
+.3937bd		c8		iny		              INY
+.3937be		c9 06		cmp #$06	              CMP #$06
+.3937c0		d0 03		bne $3937c5	              BNE PERCUSSION_NEXT07
+.3937c2		82 70 01	brl $393935	              BRL Percussion_6
+.3937c5						PERCUSSION_NEXT07
+.3937c5		c9 07		cmp #$07	              CMP #$07
+.3937c7		d0 03		bne $3937cc	              BNE PERCUSSION_NEXT08
+.3937c9		82 44 01	brl $393910	              BRL Percussion_7
+.3937cc						PERCUSSION_NEXT08
+.3937cc		c9 08		cmp #$08	              CMP #$08
+.3937ce		d0 03		bne $3937d3	              BNE PERCUSSION_NEXT09
+.3937d0		82 18 01	brl $3938eb	              BRL Percussion_8
+.3937d3						PERCUSSION_NEXT09
+.3937d3		c9 09		cmp #$09	              CMP #$09
+.3937d5		d0 03		bne $3937da	              BNE PERCUSSION_NEXT0A
+.3937d7		82 ec 00	brl $3938c6	              BRL Percussion_9
+.3937da						PERCUSSION_NEXT0A
+.3937da		c9 0a		cmp #$0a	              CMP #$0A
+.3937dc		d0 03		bne $3937e1	              BNE Percussion_Default
+.3937de		82 c0 00	brl $3938a1	              BRL Percussion_A
+.3937e1						Percussion_Default
+.3937e1		a9 00		lda #$00	              LDA #$00
+.3937e3		85 26		sta $26		              STA OPL2_OPERATOR
+.3937e5		c2 20		rep #$20	                REP #$20        ; set A long
+.3937e7		a9 20 00	lda #$0020	              LDA #$0020;
+.3937ea		85 28		sta $28		              STA OPL2_REG_REGION
+.3937ec		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.3937ef		e2 20		sep #$20	                SEP #$20        ; set A short
+.3937f1		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
+.3937f3		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.3937f5		c8		iny		              INY
+.3937f6		c2 20		rep #$20	                REP #$20        ; set A long
+.3937f8		a9 40 00	lda #$0040	              LDA #$0040;
+.3937fb		85 28		sta $28		              STA OPL2_REG_REGION
+.3937fd		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393800		e2 20		sep #$20	                SEP #$20        ; set A short
+.393802		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
+.393804		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393806		c8		iny		              INY
+.393807		c2 20		rep #$20	                REP #$20        ; set A long
+.393809		a9 60 00	lda #$0060	              LDA #$0060;
+.39380c		85 28		sta $28		              STA OPL2_REG_REGION
+.39380e		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393811		e2 20		sep #$20	                SEP #$20        ; set A short
+.393813		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
+.393815		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393817		c8		iny		              INY
+.393818		c2 20		rep #$20	                REP #$20        ; set A long
+.39381a		a9 80 00	lda #$0080	              LDA #$0080;
+.39381d		85 28		sta $28		              STA OPL2_REG_REGION
+.39381f		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393822		e2 20		sep #$20	                SEP #$20        ; set A short
+.393824		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
+.393826		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393828		c8		iny		              INY
+.393829		c2 20		rep #$20	                REP #$20        ; set A long
+.39382b		a9 e0 00	lda #$00e0	              LDA #$00E0;
+.39382e		85 28		sta $28		              STA OPL2_REG_REGION
+.393830		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393833		e2 20		sep #$20	                SEP #$20        ; set A short
+.393835		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
+.393837		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393839		c8		iny		              INY
+.39383a		e2 10		sep #$10	                SEP #$10        ; set X short
+.39383c		a5 27		lda $27		              LDA OPL2_CHANNEL
+.39383e		29 0f		and #$0f	              AND #$0F
+.393840		aa		tax		              TAX
+.393841		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 6 in Instrument Profile
+.393843		9f c0 e6 af	sta $afe6c0,x	              STA @lOPL3_R_FEEDBACK,X
+.393847		c8		iny		              INY
+.393848		a9 01		lda #$01	              LDA #$01
+.39384a		85 26		sta $26		              STA OPL2_OPERATOR
+.39384c		c2 20		rep #$20	                REP #$20        ; set A long
+.39384e		a9 20 00	lda #$0020	              LDA #$0020;
+.393851		85 28		sta $28		              STA OPL2_REG_REGION
+.393853		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393856		e2 20		sep #$20	                SEP #$20        ; set A short
+.393858		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 7 in Instrument Profile
+.39385a		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.39385c		c8		iny		              INY
+.39385d		c2 20		rep #$20	                REP #$20        ; set A long
+.39385f		a9 40 00	lda #$0040	              LDA #$0040;
+.393862		85 28		sta $28		              STA OPL2_REG_REGION
+.393864		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393867		e2 20		sep #$20	                SEP #$20        ; set A short
+.393869		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 8 in Instrument Profile
+.39386b		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.39386d		c8		iny		              INY
+.39386e		c2 20		rep #$20	                REP #$20        ; set A long
+.393870		a9 60 00	lda #$0060	              LDA #$0060;
+.393873		85 28		sta $28		              STA OPL2_REG_REGION
+.393875		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393878		e2 20		sep #$20	                SEP #$20        ; set A short
+.39387a		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 9 in Instrument Profile
+.39387c		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.39387e		c8		iny		              INY
+.39387f		c2 20		rep #$20	                REP #$20        ; set A long
+.393881		a9 80 00	lda #$0080	              LDA #$0080;
+.393884		85 28		sta $28		              STA OPL2_REG_REGION
+.393886		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393889		e2 20		sep #$20	                SEP #$20        ; set A short
+.39388b		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location A in Instrument Profile
+.39388d		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.39388f		c8		iny		              INY
+.393890		c2 20		rep #$20	                REP #$20        ; set A long
+.393892		a9 e0 00	lda #$00e0	              LDA #$00E0;
+.393895		85 28		sta $28		              STA OPL2_REG_REGION
+.393897		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.39389a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39389c		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location B in Instrument Profile
+.39389e		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.3938a0		6b		rtl		                RTL
+.3938a1						Percussion_A
+.3938a1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3938a3		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
+.3938a5		8f 31 e6 af	sta $afe631	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $11
+.3938a9		c8		iny		              INY
+.3938aa		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
+.3938ac		8f 51 e6 af	sta $afe651	              STA @lOPL3_R_KSL_TL + $11
+.3938b0		c8		iny		              INY
+.3938b1		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
+.3938b3		8f 71 e6 af	sta $afe671	              STA @lOPL3_R_AR_DR + $11
+.3938b7		c8		iny		              INY
+.3938b8		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
+.3938ba		8f 91 e6 af	sta $afe691	              STA @lOPL3_R_SL_RR + $11
+.3938be		c8		iny		              INY
+.3938bf		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
+.3938c1		8f f1 e6 af	sta $afe6f1	              STA @lOPL3_R_WAVE_SELECT + $11
+.3938c5		6b		rtl		                RTL
+.3938c6						Percussion_9
+.3938c6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3938c8		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
+.3938ca		8f 35 e6 af	sta $afe635	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $15
+.3938ce		c8		iny		              INY
+.3938cf		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
+.3938d1		8f 55 e6 af	sta $afe655	              STA @lOPL3_R_KSL_TL + $15
+.3938d5		c8		iny		              INY
+.3938d6		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
+.3938d8		8f 75 e6 af	sta $afe675	              STA @lOPL3_R_AR_DR + $15
+.3938dc		c8		iny		              INY
+.3938dd		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
+.3938df		8f 95 e6 af	sta $afe695	              STA @lOPL3_R_SL_RR + $15
+.3938e3		c8		iny		              INY
+.3938e4		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
+.3938e6		8f f5 e6 af	sta $afe6f5	              STA @lOPL3_R_WAVE_SELECT + $15
+.3938ea		6b		rtl		              RTL
+.3938eb						Percussion_8
+.3938eb		e2 20		sep #$20	                SEP #$20        ; set A short
+.3938ed		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
+.3938ef		8f 32 e6 af	sta $afe632	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $12
+.3938f3		c8		iny		              INY
+.3938f4		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
+.3938f6		8f 52 e6 af	sta $afe652	              STA @lOPL3_R_KSL_TL + $12
+.3938fa		c8		iny		              INY
+.3938fb		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
+.3938fd		8f 72 e6 af	sta $afe672	              STA @lOPL3_R_AR_DR + $12
+.393901		c8		iny		              INY
+.393902		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
+.393904		8f 92 e6 af	sta $afe692	              STA @lOPL3_R_SL_RR + $12
+.393908		c8		iny		              INY
+.393909		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
+.39390b		8f f2 e6 af	sta $afe6f2	              STA @lOPL3_R_WAVE_SELECT + $12
+.39390f		6b		rtl		              RTL
+.393910						Percussion_7
+.393910		e2 20		sep #$20	                SEP #$20        ; set A short
+.393912		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
+.393914		8f 34 e6 af	sta $afe634	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $14
+.393918		c8		iny		              INY
+.393919		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
+.39391b		8f 54 e6 af	sta $afe654	              STA @lOPL3_R_KSL_TL + $14
+.39391f		c8		iny		              INY
+.393920		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
+.393922		8f 74 e6 af	sta $afe674	              STA @lOPL3_R_AR_DR + $14
+.393926		c8		iny		              INY
+.393927		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
+.393929		8f 94 e6 af	sta $afe694	              STA @lOPL3_R_SL_RR + $14
+.39392d		c8		iny		              INY
+.39392e		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
+.393930		8f f4 e6 af	sta $afe6f4	              STA @lOPL3_R_WAVE_SELECT + $14
+.393934		6b		rtl		              RTL
+.393935						Percussion_6
+.393935		e2 20		sep #$20	                SEP #$20        ; set A short
+.393937		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 1 in Instrument Profile
+.393939		8f 30 e6 af	sta $afe630	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $10
+.39393d		8f 33 e6 af	sta $afe633	              STA @lOPL3_R_AM_VID_EG_KSR_MULT + $13
+.393941		c8		iny		              INY
+.393942		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 2 in Instrument Profile
+.393944		8f 50 e6 af	sta $afe650	              STA @lOPL3_R_KSL_TL + $10
+.393948		8f 53 e6 af	sta $afe653	              STA @lOPL3_R_KSL_TL + $13
+.39394c		c8		iny		              INY
+.39394d		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 3 in Instrument Profile
+.39394f		8f 70 e6 af	sta $afe670	              STA @lOPL3_R_AR_DR + $10
+.393953		8f 73 e6 af	sta $afe673	              STA @lOPL3_R_AR_DR + $13
+.393957		c8		iny		              INY
+.393958		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 4 in Instrument Profile
+.39395a		8f 90 e6 af	sta $afe690	              STA @lOPL3_R_SL_RR + $10
+.39395e		8f 93 e6 af	sta $afe693	              STA @lOPL3_R_SL_RR + $13
+.393962		c8		iny		              INY
+.393963		b7 08		lda [$08],y	              LDA [OPL2_ADDY_PTR_LO], Y ; Pointer Location 5 in Instrument Profile
+.393965		8f f0 e6 af	sta $afe6f0	              STA @lOPL3_R_WAVE_SELECT + $10
+.393969		8f f3 e6 af	sta $afe6f3	              STA @lOPL3_R_WAVE_SELECT + $13
+.39396d		6b		rtl		              RTL
+.39396e						OPL2_SET_REGISTER
+.39396e		48		pha		                PHA             ; begin setdp macro
+.39396f		08		php		                PHP
+.393970		c2 20		rep #$20	                REP #$20        ; set A long
+.393972		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393975		5b		tcd		                TCD
+.393976		28		plp		                PLP
+.393977		68		pla		                PLA             ; end setdp macro
+.393978		c2 20		rep #$20	                REP #$20        ; set A long
+.39397a		18		clc		              CLC
+.39397b		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.39397e		65 32		adc $32		              ADC OPL2_PARAMETER0
+.393980		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393982		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393985		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393987		e2 20		sep #$20	                SEP #$20        ; set A short
+.393989		a5 33		lda $33		              LDA OPL2_PARAMETER1
+.39398b		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.39398d		6b		rtl		              RTL
+.39398e						OPL2_SET_WAVEFORMSELECT
+.39398e		48		pha		                PHA             ; begin setdp macro
+.39398f		08		php		                PHP
+.393990		c2 20		rep #$20	                REP #$20        ; set A long
+.393992		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393995		5b		tcd		                TCD
+.393996		28		plp		                PLP
+.393997		68		pla		                PLA             ; end setdp macro
+.393998		c2 20		rep #$20	                REP #$20        ; set A long
+.39399a		a9 01 e6	lda #$e601	              LDA #<>OPL3_R_BASE + $0001
+.39399d		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.39399f		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.3939a2		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.3939a4		e2 20		sep #$20	                SEP #$20        ; set A short
+.3939a6		b0 07		bcs $3939af	              BCS OPL2_Set_WaveFormSelect_set
+.3939a8		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.3939aa		29 df		and #$df	              AND #$DF
+.3939ac		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.3939ae		6b		rtl		              RTL
+.3939af						OPL2_Set_WaveFormSelect_set
+.3939af		48		pha		                PHA             ; begin setdp macro
+.3939b0		08		php		                PHP
+.3939b1		c2 20		rep #$20	                REP #$20        ; set A long
+.3939b3		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3939b6		5b		tcd		                TCD
+.3939b7		28		plp		                PLP
+.3939b8		68		pla		                PLA             ; end setdp macro
+.3939b9		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.3939bb		09 20 00	ora #$0020	              ORA #$20
+.3939be		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.3939c0		6b		rtl		                RTL
+.3939c1						OPL2_SET_TREMOLO
+.3939c1		48		pha		                PHA             ; begin setdp macro
+.3939c2		08		php		                PHP
+.3939c3		c2 20		rep #$20	                REP #$20        ; set A long
+.3939c5		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3939c8		5b		tcd		                TCD
+.3939c9		28		plp		                PLP
+.3939ca		68		pla		                PLA             ; end setdp macro
+.3939cb		08		php		                PHP ; Push the Carry
+.3939cc		c2 20		rep #$20	                REP #$20        ; set A long
+.3939ce		18		clc		                CLC
+.3939cf		a9 20 00	lda #$0020	                LDA #$0020 ;
+.3939d2		85 28		sta $28		                STA OPL2_REG_REGION
+.3939d4		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.3939d7		28		plp		                PLP ; Pull the Carry out
+.3939d8		e2 20		sep #$20	                SEP #$20        ; set A short
+.3939da		b0 08		bcs $3939e4	                BCS OPL2_Set_Tremolo_Set;
+.3939dc		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.3939de		29 7f		and #$7f	                AND #$7F
+.3939e0		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.3939e2		80 06		bra $3939ea	                BRA OPL2_Set_Tremolo_Exit
+.3939e4						OPL2_Set_Tremolo_Set
+.3939e4		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.3939e6		09 80		ora #$80	                ORA #$80
+.3939e8		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.3939ea						OPL2_Set_Tremolo_Exit
+.3939ea		6b		rtl		                RTL
+.3939eb						OPL2_GET_TREMOLO
+.3939eb		48		pha		                PHA             ; begin setdp macro
+.3939ec		08		php		                PHP
+.3939ed		c2 20		rep #$20	                REP #$20        ; set A long
+.3939ef		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.3939f2		5b		tcd		                TCD
+.3939f3		28		plp		                PLP
+.3939f4		68		pla		                PLA             ; end setdp macro
+.3939f5		c2 20		rep #$20	                REP #$20        ; set A long
+.3939f7		a9 20 00	lda #$0020	                LDA #$0020;
+.3939fa		85 28		sta $28		                STA OPL2_REG_REGION
+.3939fc		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.3939ff		e2 20		sep #$20	                SEP #$20        ; set A short
+.393a01		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393a03		29 80		and #$80	                AND #$80
+.393a05		6b		rtl		                RTL
+.393a06						OPL2_SET_VIBRATO
+.393a06		48		pha		                PHA             ; begin setdp macro
+.393a07		08		php		                PHP
+.393a08		c2 20		rep #$20	                REP #$20        ; set A long
+.393a0a		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393a0d		5b		tcd		                TCD
+.393a0e		28		plp		                PLP
+.393a0f		68		pla		                PLA             ; end setdp macro
+.393a10		08		php		                PHP ; Push the Carry
+.393a11		c2 20		rep #$20	                REP #$20        ; set A long
+.393a13		18		clc		                CLC
+.393a14		a9 20 00	lda #$0020	                LDA #$0020;
+.393a17		85 28		sta $28		                STA OPL2_REG_REGION
+.393a19		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393a1c		28		plp		                PLP ; Pull the Carry out
+.393a1d		e2 20		sep #$20	                SEP #$20        ; set A short
+.393a1f		b0 08		bcs $393a29	                BCS OPL2_Set_Vibrato_Set;
+.393a21		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393a23		29 bf		and #$bf	                AND #$BF
+.393a25		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393a27		80 06		bra $393a2f	                BRA OPL2_Set_Vibrato_Exit
+.393a29						OPL2_Set_Vibrato_Set
+.393a29		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393a2b		09 40		ora #$40	                ORA #$40
+.393a2d		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393a2f						OPL2_Set_Vibrato_Exit
+.393a2f		6b		rtl		                RTL
+.393a30						OPL2_GET_VIBRATO
+.393a30		48		pha		                PHA             ; begin setdp macro
+.393a31		08		php		                PHP
+.393a32		c2 20		rep #$20	                REP #$20        ; set A long
+.393a34		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393a37		5b		tcd		                TCD
+.393a38		28		plp		                PLP
+.393a39		68		pla		                PLA             ; end setdp macro
+.393a3a		c2 20		rep #$20	                REP #$20        ; set A long
+.393a3c		a9 20 00	lda #$0020	                LDA #$0020;
+.393a3f		85 28		sta $28		                STA OPL2_REG_REGION
+.393a41		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393a44		e2 20		sep #$20	                SEP #$20        ; set A short
+.393a46		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393a48		29 40		and #$40	                AND #$40
+.393a4a		6b		rtl		                RTL
+.393a4b						OPL2_SET_MAINTAINSUSTAIN
+.393a4b		48		pha		                PHA             ; begin setdp macro
+.393a4c		08		php		                PHP
+.393a4d		c2 20		rep #$20	                REP #$20        ; set A long
+.393a4f		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393a52		5b		tcd		                TCD
+.393a53		28		plp		                PLP
+.393a54		68		pla		                PLA             ; end setdp macro
+.393a55		08		php		              PHP ; Push the Carry
+.393a56		c2 20		rep #$20	                REP #$20        ; set A long
+.393a58		18		clc		              CLC
+.393a59		a9 20 00	lda #$0020	              LDA #$0020;
+.393a5c		85 28		sta $28		              STA OPL2_REG_REGION
+.393a5e		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393a61		28		plp		              PLP ; Pull the Carry out
+.393a62		e2 20		sep #$20	                SEP #$20        ; set A short
+.393a64		b0 08		bcs $393a6e	              BCS OPL2_Set_MaintainSustain_Set;
+.393a66		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393a68		29 df		and #$df	              AND #$DF
+.393a6a		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393a6c		80 06		bra $393a74	              BRA OPL2_Set_MaintainSustain_Exit
+.393a6e						OPL2_Set_MaintainSustain_Set
+.393a6e		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393a70		09 20		ora #$20	              ORA #$20
+.393a72		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393a74						OPL2_Set_MaintainSustain_Exit
+.393a74		6b		rtl		                RTL
+.393a75						OPL2_GET_MAINTAINSUSTAIN
+.393a75		48		pha		                PHA             ; begin setdp macro
+.393a76		08		php		                PHP
+.393a77		c2 20		rep #$20	                REP #$20        ; set A long
+.393a79		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393a7c		5b		tcd		                TCD
+.393a7d		28		plp		                PLP
+.393a7e		68		pla		                PLA             ; end setdp macro
+.393a7f		c2 20		rep #$20	                REP #$20        ; set A long
+.393a81		a9 20 00	lda #$0020	              LDA #$0020;
+.393a84		85 28		sta $28		              STA OPL2_REG_REGION
+.393a86		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393a89		e2 20		sep #$20	                SEP #$20        ; set A short
+.393a8b		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393a8d		29 20		and #$20	              AND #$20
+.393a8f		6b		rtl		                RTL
+.393a90						OPL2_SET_ENVELOPESCALING
+.393a90		48		pha		                PHA             ; begin setdp macro
+.393a91		08		php		                PHP
+.393a92		c2 20		rep #$20	                REP #$20        ; set A long
+.393a94		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393a97		5b		tcd		                TCD
+.393a98		28		plp		                PLP
+.393a99		68		pla		                PLA             ; end setdp macro
+.393a9a		08		php		              PHP ; Push the Carry
+.393a9b		c2 20		rep #$20	                REP #$20        ; set A long
+.393a9d		18		clc		              CLC
+.393a9e		a9 20 00	lda #$0020	              LDA #$0020;
+.393aa1		85 28		sta $28		              STA OPL2_REG_REGION
+.393aa3		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393aa6		28		plp		              PLP ; Pull the Carry out
+.393aa7		e2 20		sep #$20	                SEP #$20        ; set A short
+.393aa9		b0 08		bcs $393ab3	              BCS OPL2_Set_EnvelopeScaling_Set;
+.393aab		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393aad		29 ef		and #$ef	              AND #$EF
+.393aaf		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393ab1		80 06		bra $393ab9	              BRA OPL2_Set_EnvelopeScaling_Exit
+.393ab3						OPL2_Set_EnvelopeScaling_Set
+.393ab3		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393ab5		09 10		ora #$10	              ORA #$10
+.393ab7		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393ab9						OPL2_Set_EnvelopeScaling_Exit
+.393ab9		6b		rtl		                RTL
+.393aba						OPL2_GET_ENVELOPESCALING
+.393aba		48		pha		                PHA             ; begin setdp macro
+.393abb		08		php		                PHP
+.393abc		c2 20		rep #$20	                REP #$20        ; set A long
+.393abe		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393ac1		5b		tcd		                TCD
+.393ac2		28		plp		                PLP
+.393ac3		68		pla		                PLA             ; end setdp macro
+.393ac4		c2 20		rep #$20	                REP #$20        ; set A long
+.393ac6		a9 20 00	lda #$0020	              LDA #$0020;
+.393ac9		85 28		sta $28		              STA OPL2_REG_REGION
+.393acb		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393ace		e2 20		sep #$20	                SEP #$20        ; set A short
+.393ad0		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393ad2		29 10		and #$10	              AND #$10
+.393ad4		6b		rtl		                RTL
+.393ad5						OPL2_GET_MODFREQMULTIPLE
+.393ad5		48		pha		                PHA             ; begin setdp macro
+.393ad6		08		php		                PHP
+.393ad7		c2 20		rep #$20	                REP #$20        ; set A long
+.393ad9		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393adc		5b		tcd		                TCD
+.393add		28		plp		                PLP
+.393ade		68		pla		                PLA             ; end setdp macro
+.393adf		c2 20		rep #$20	                REP #$20        ; set A long
+.393ae1		a9 20 00	lda #$0020	              LDA #$0020;
+.393ae4		85 28		sta $28		              STA OPL2_REG_REGION
+.393ae6		20 cc 3e	jsr $393ecc	              JSR OPL2_GET_REG_OFFSET
+.393ae9		e2 20		sep #$20	                SEP #$20        ; set A short
+.393aeb		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393aed		29 0f		and #$0f	              AND #$0F
+.393aef		6b		rtl		              RTL
+.393af0						OPL2_SET_MODFREQMULTIPLE
+.393af0		48		pha		                PHA             ; begin setdp macro
+.393af1		08		php		                PHP
+.393af2		c2 20		rep #$20	                REP #$20        ; set A long
+.393af4		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393af7		5b		tcd		                TCD
+.393af8		28		plp		                PLP
+.393af9		68		pla		                PLA             ; end setdp macro
+.393afa		c2 20		rep #$20	                REP #$20        ; set A long
+.393afc		a9 20 00	lda #$0020	                LDA #$0020;
+.393aff		85 28		sta $28		                STA OPL2_REG_REGION
+.393b01		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393b04		e2 20		sep #$20	                SEP #$20        ; set A short
+.393b06		a5 32		lda $32		                LDA OPL2_PARAMETER0
+.393b08		29 0f		and #$0f	                AND #$0F
+.393b0a		85 32		sta $32		                STA OPL2_PARAMETER0
+.393b0c		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393b0e		29 f0		and #$f0	                AND #$F0
+.393b10		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393b12		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393b14		6b		rtl		                RTL
+.393b15						OPL2_SET_SCALINGLEVEL
+.393b15		48		pha		                PHA             ; begin setdp macro
+.393b16		08		php		                PHP
+.393b17		c2 20		rep #$20	                REP #$20        ; set A long
+.393b19		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393b1c		5b		tcd		                TCD
+.393b1d		28		plp		                PLP
+.393b1e		68		pla		                PLA             ; end setdp macro
+.393b1f		c2 20		rep #$20	                REP #$20        ; set A long
+.393b21		a9 40 00	lda #$0040	                LDA #$0040;
+.393b24		85 28		sta $28		                STA OPL2_REG_REGION
+.393b26		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393b29		e2 20		sep #$20	                SEP #$20        ; set A short
+.393b2b		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
+.393b2d		29 03		and #$03	                AND #$03
+.393b2f		0a		asl a		                ASL
+.393b30		0a		asl a		                ASL
+.393b31		0a		asl a		                ASL
+.393b32		0a		asl a		                ASL
+.393b33		0a		asl a		                ASL
+.393b34		0a		asl a		                ASL
+.393b35		85 32		sta $32		                STA OPL2_PARAMETER0
+.393b37		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393b39		29 3f		and #$3f	                AND #$3F
+.393b3b		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393b3d		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393b3f		6b		rtl		                RTL
+.393b40						OPL2_SET_VOLUME
+.393b40		48		pha		                PHA             ; begin setdp macro
+.393b41		08		php		                PHP
+.393b42		c2 20		rep #$20	                REP #$20        ; set A long
+.393b44		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393b47		5b		tcd		                TCD
+.393b48		28		plp		                PLP
+.393b49		68		pla		                PLA             ; end setdp macro
+.393b4a		c2 20		rep #$20	                REP #$20        ; set A long
+.393b4c		a9 40 00	lda #$0040	                LDA #$0040  ;
+.393b4f		85 28		sta $28		                STA OPL2_REG_REGION
+.393b51		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393b54		e2 20		sep #$20	                SEP #$20        ; set A short
+.393b56		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Volume
+.393b58		29 3f		and #$3f	                AND #$3F
+.393b5a		85 32		sta $32		                STA OPL2_PARAMETER0
+.393b5c		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393b5e		29 c0		and #$c0	                AND #$C0
+.393b60		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393b62		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393b64		6b		rtl		                RTL
+.393b65						OPL2_GET_VOLUME
+.393b65		48		pha		                PHA             ; begin setdp macro
+.393b66		08		php		                PHP
+.393b67		c2 20		rep #$20	                REP #$20        ; set A long
+.393b69		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393b6c		5b		tcd		                TCD
+.393b6d		28		plp		                PLP
+.393b6e		68		pla		                PLA             ; end setdp macro
+.393b6f		c2 20		rep #$20	                REP #$20        ; set A long
+.393b71		a9 40 00	lda #$0040	                LDA #$0040  ;
+.393b74		85 28		sta $28		                STA OPL2_REG_REGION
+.393b76		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393b79		e2 20		sep #$20	                SEP #$20        ; set A short
+.393b7b		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393b7d		29 3f		and #$3f	                AND #$3F
+.393b7f		6b		rtl		                RTL
+.393b80						OPL2_SET_ATTACK
+.393b80		48		pha		                PHA             ; begin setdp macro
+.393b81		08		php		                PHP
+.393b82		c2 20		rep #$20	                REP #$20        ; set A long
+.393b84		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393b87		5b		tcd		                TCD
+.393b88		28		plp		                PLP
+.393b89		68		pla		                PLA             ; end setdp macro
+.393b8a		c2 20		rep #$20	                REP #$20        ; set A long
+.393b8c		a9 60 00	lda #$0060	                LDA #$0060  ;
+.393b8f		85 28		sta $28		                STA OPL2_REG_REGION
+.393b91		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393b94		e2 20		sep #$20	                SEP #$20        ; set A short
+.393b96		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
+.393b98		29 0f		and #$0f	                AND #$0F
+.393b9a		0a		asl a		                ASL
+.393b9b		0a		asl a		                ASL
+.393b9c		0a		asl a		                ASL
+.393b9d		0a		asl a		                ASL
+.393b9e		85 32		sta $32		                STA OPL2_PARAMETER0
+.393ba0		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393ba2		29 0f		and #$0f	                AND #$0F
+.393ba4		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393ba6		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393ba8		6b		rtl		                RTL
+.393ba9						OPL2_GET_ATTACK
+.393ba9		48		pha		                PHA             ; begin setdp macro
+.393baa		08		php		                PHP
+.393bab		c2 20		rep #$20	                REP #$20        ; set A long
+.393bad		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393bb0		5b		tcd		                TCD
+.393bb1		28		plp		                PLP
+.393bb2		68		pla		                PLA             ; end setdp macro
+.393bb3		c2 20		rep #$20	                REP #$20        ; set A long
+.393bb5		a9 60 00	lda #$0060	                LDA #$0060
+.393bb8		85 28		sta $28		                STA OPL2_REG_REGION
+.393bba		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393bbd		e2 20		sep #$20	                SEP #$20        ; set A short
+.393bbf		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393bc1		29 f0		and #$f0	                AND #$F0
+.393bc3		4a		lsr a		                LSR
+.393bc4		4a		lsr a		                LSR
+.393bc5		4a		lsr a		                LSR
+.393bc6		4a		lsr a		                LSR
+.393bc7		6b		rtl		                RTL
+.393bc8						OPL2_SET_DECAY
+.393bc8		48		pha		                PHA             ; begin setdp macro
+.393bc9		08		php		                PHP
+.393bca		c2 20		rep #$20	                REP #$20        ; set A long
+.393bcc		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393bcf		5b		tcd		                TCD
+.393bd0		28		plp		                PLP
+.393bd1		68		pla		                PLA             ; end setdp macro
+.393bd2		c2 20		rep #$20	                REP #$20        ; set A long
+.393bd4		a9 60 00	lda #$0060	                LDA #$0060;
+.393bd7		85 28		sta $28		                STA OPL2_REG_REGION
+.393bd9		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393bdc		e2 20		sep #$20	                SEP #$20        ; set A short
+.393bde		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
+.393be0		29 0f		and #$0f	                AND #$0F
+.393be2		85 32		sta $32		                STA OPL2_PARAMETER0
+.393be4		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393be6		29 f0		and #$f0	                AND #$F0
+.393be8		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393bea		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393bec		6b		rtl		                RTL
+.393bed						OPL2_GET_DECAY
+.393bed		48		pha		                PHA             ; begin setdp macro
+.393bee		08		php		                PHP
+.393bef		c2 20		rep #$20	                REP #$20        ; set A long
+.393bf1		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393bf4		5b		tcd		                TCD
+.393bf5		28		plp		                PLP
+.393bf6		68		pla		                PLA             ; end setdp macro
+.393bf7		c2 20		rep #$20	                REP #$20        ; set A long
+.393bf9		a9 60 00	lda #$0060	                LDA #$0060
+.393bfc		85 28		sta $28		                STA OPL2_REG_REGION
+.393bfe		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393c01		e2 20		sep #$20	                SEP #$20        ; set A short
+.393c03		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393c05		29 0f		and #$0f	                AND #$0F
+.393c07		6b		rtl		                RTL
+.393c08						OPL2_SET_SUSTAIN
+.393c08		48		pha		                PHA             ; begin setdp macro
+.393c09		08		php		                PHP
+.393c0a		c2 20		rep #$20	                REP #$20        ; set A long
+.393c0c		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393c0f		5b		tcd		                TCD
+.393c10		28		plp		                PLP
+.393c11		68		pla		                PLA             ; end setdp macro
+.393c12		c2 20		rep #$20	                REP #$20        ; set A long
+.393c14		a9 80 00	lda #$0080	                LDA #$0080;
+.393c17		85 28		sta $28		                STA OPL2_REG_REGION
+.393c19		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393c1c		e2 20		sep #$20	                SEP #$20        ; set A short
+.393c1e		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
+.393c20		29 0f		and #$0f	                AND #$0F
+.393c22		0a		asl a		                ASL
+.393c23		0a		asl a		                ASL
+.393c24		0a		asl a		                ASL
+.393c25		0a		asl a		                ASL
+.393c26		85 32		sta $32		                STA OPL2_PARAMETER0
+.393c28		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393c2a		29 0f		and #$0f	                AND #$0F
+.393c2c		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393c2e		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393c30		6b		rtl		                RTL
+.393c31						OPL2_GET_SUSTAIN
+.393c31		48		pha		                PHA             ; begin setdp macro
+.393c32		08		php		                PHP
+.393c33		c2 20		rep #$20	                REP #$20        ; set A long
+.393c35		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393c38		5b		tcd		                TCD
+.393c39		28		plp		                PLP
+.393c3a		68		pla		                PLA             ; end setdp macro
+.393c3b		c2 20		rep #$20	                REP #$20        ; set A long
+.393c3d		a9 80 00	lda #$0080	                LDA #$0080
+.393c40		85 28		sta $28		                STA OPL2_REG_REGION
+.393c42		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393c45		e2 20		sep #$20	                SEP #$20        ; set A short
+.393c47		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393c49		29 f0		and #$f0	                AND #$F0
+.393c4b		4a		lsr a		                LSR
+.393c4c		4a		lsr a		                LSR
+.393c4d		4a		lsr a		                LSR
+.393c4e		4a		lsr a		                LSR
+.393c4f		6b		rtl		                RTL
+.393c50						OPL2_SET_RELEASE
+.393c50		48		pha		                PHA             ; begin setdp macro
+.393c51		08		php		                PHP
+.393c52		c2 20		rep #$20	                REP #$20        ; set A long
+.393c54		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393c57		5b		tcd		                TCD
+.393c58		28		plp		                PLP
+.393c59		68		pla		                PLA             ; end setdp macro
+.393c5a		c2 20		rep #$20	                REP #$20        ; set A long
+.393c5c		a9 80 00	lda #$0080	                LDA #$0080;
+.393c5f		85 28		sta $28		                STA OPL2_REG_REGION
+.393c61		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393c64		e2 20		sep #$20	                SEP #$20        ; set A short
+.393c66		a5 32		lda $32		                LDA OPL2_PARAMETER0 ; Attack
+.393c68		29 0f		and #$0f	                AND #$0F
+.393c6a		85 32		sta $32		                STA OPL2_PARAMETER0
+.393c6c		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393c6e		29 f0		and #$f0	                AND #$F0
+.393c70		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393c72		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393c74		6b		rtl		                RTL
+.393c75						OPL2_GET_RELEASE
+.393c75		48		pha		                PHA             ; begin setdp macro
+.393c76		08		php		                PHP
+.393c77		c2 20		rep #$20	                REP #$20        ; set A long
+.393c79		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393c7c		5b		tcd		                TCD
+.393c7d		28		plp		                PLP
+.393c7e		68		pla		                PLA             ; end setdp macro
+.393c7f		c2 20		rep #$20	                REP #$20        ; set A long
+.393c81		a9 80 00	lda #$0080	                LDA #$0080
+.393c84		85 28		sta $28		                STA OPL2_REG_REGION
+.393c86		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393c89		e2 20		sep #$20	                SEP #$20        ; set A short
+.393c8b		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393c8d		29 0f		and #$0f	                AND #$0F
+.393c8f		6b		rtl		                RTL
+.393c90						OPL2_SET_FNUMBER
+.393c90		48		pha		                PHA             ; begin setdp macro
+.393c91		08		php		                PHP
+.393c92		c2 20		rep #$20	                REP #$20        ; set A long
+.393c94		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393c97		5b		tcd		                TCD
+.393c98		28		plp		                PLP
+.393c99		68		pla		                PLA             ; end setdp macro
+.393c9a		e2 20		sep #$20	                SEP #$20        ; set A short
+.393c9c		18		clc		                CLC
+.393c9d		a5 27		lda $27		                LDA OPL2_CHANNEL
+.393c9f		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
+.393ca1		69 a0		adc #$a0	                ADC #$A0
+.393ca3		85 2a		sta $2a		                STA OPL2_REG_OFFSET
+.393ca5		a9 00		lda #$00	                LDA #$00
+.393ca7		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
+.393ca9		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393cab		18		clc		                CLC
+.393cac		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
+.393caf		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
+.393cb1		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393cb3		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393cb6		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393cb8		e2 20		sep #$20	                SEP #$20        ; set A short
+.393cba		a5 32		lda $32		                LDA OPL2_PARAMETER0     ; Load the first 8 Bits Value of FNumber
+.393cbc		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]  ; Load
+.393cbe		18		clc		                CLC
+.393cbf		a5 2c		lda $2c		                LDA OPL2_IND_ADDY_LL
+.393cc1		69 10		adc #$10	                ADC #$10
+.393cc3		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393cc5		a5 33		lda $33		                LDA OPL2_PARAMETER1
+.393cc7		29 03		and #$03	                AND #$03
+.393cc9		85 33		sta $33		                STA OPL2_PARAMETER1
+.393ccb		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393ccd		29 fc		and #$fc	                AND #$FC
+.393ccf		05 33		ora $33		                ORA OPL2_PARAMETER1
+.393cd1		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393cd3		6b		rtl		                RTL
+.393cd4						OPL2_GET_FNUMBER
+.393cd4		48		pha		                PHA             ; begin setdp macro
+.393cd5		08		php		                PHP
+.393cd6		c2 20		rep #$20	                REP #$20        ; set A long
+.393cd8		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393cdb		5b		tcd		                TCD
+.393cdc		28		plp		                PLP
+.393cdd		68		pla		                PLA             ; end setdp macro
+.393cde		e2 20		sep #$20	                SEP #$20        ; set A short
+.393ce0		18		clc		                CLC
+.393ce1		a5 27		lda $27		                LDA OPL2_CHANNEL
+.393ce3		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
+.393ce5		69 a0		adc #$a0	                ADC #$A0
+.393ce7		85 2a		sta $2a		                STA OPL2_REG_OFFSET
+.393ce9		a9 00		lda #$00	                LDA #$00
+.393ceb		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
+.393ced		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393cef		18		clc		                CLC
+.393cf0		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
+.393cf3		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
+.393cf5		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393cf7		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393cfa		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393cfc		e2 20		sep #$20	                SEP #$20        ; set A short
+.393cfe		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393d00		85 32		sta $32		                STA OPL2_PARAMETER0
+.393d02		18		clc		                CLC
+.393d03		a5 2c		lda $2c		                LDA OPL2_IND_ADDY_LL
+.393d05		69 10		adc #$10	                ADC #$10
+.393d07		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393d09		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393d0b		29 03		and #$03	                AND #$03
+.393d0d		85 33		sta $33		                STA OPL2_PARAMETER1
+.393d0f		6b		rtl		                RTL
+.393d10						OPL2_Set_Frequency
+.393d10		6b		rtl		                RTL
+.393d11						OPL2_Get_Frequency
+.393d11		6b		rtl		                RTL
+.393d12						OPL2_SET_BLOCK
+.393d12		48		pha		                PHA             ; begin setdp macro
+.393d13		08		php		                PHP
+.393d14		c2 20		rep #$20	                REP #$20        ; set A long
+.393d16		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393d19		5b		tcd		                TCD
+.393d1a		28		plp		                PLP
+.393d1b		68		pla		                PLA             ; end setdp macro
+.393d1c		e2 20		sep #$20	                SEP #$20        ; set A short
+.393d1e		18		clc		                CLC
+.393d1f		a5 27		lda $27		                LDA OPL2_CHANNEL
+.393d21		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
+.393d23		69 b0		adc #$b0	                ADC #$B0
+.393d25		85 2a		sta $2a		                STA OPL2_REG_OFFSET
+.393d27		a9 00		lda #$00	                LDA #$00
+.393d29		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
+.393d2b		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393d2d		18		clc		                CLC
+.393d2e		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
+.393d31		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
+.393d33		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393d35		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393d38		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393d3a		e2 20		sep #$20	                SEP #$20        ; set A short
+.393d3c		a5 31		lda $31		                LDA OPL2_OCTAVE
+.393d3e		29 07		and #$07	                AND #$07
+.393d40		0a		asl a		                ASL
+.393d41		0a		asl a		                ASL
+.393d42		85 31		sta $31		                STA OPL2_OCTAVE
+.393d44		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393d46		29 e3		and #$e3	                AND #$E3
+.393d48		05 31		ora $31		                ORA OPL2_OCTAVE
+.393d4a		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393d4c		60		rts		                RTS
+.393d4d						OPL2_SET_KEYON
+.393d4d		48		pha		                PHA             ; begin setdp macro
+.393d4e		08		php		                PHP
+.393d4f		c2 20		rep #$20	                REP #$20        ; set A long
+.393d51		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393d54		5b		tcd		                TCD
+.393d55		28		plp		                PLP
+.393d56		68		pla		                PLA             ; end setdp macro
+.393d57		e2 20		sep #$20	                SEP #$20        ; set A short
+.393d59		18		clc		                CLC
+.393d5a		a5 27		lda $27		                LDA OPL2_CHANNEL
+.393d5c		29 0f		and #$0f	                AND #$0F  ; This is just precaution, it should be between 0 to 8
+.393d5e		69 b0		adc #$b0	                ADC #$B0
+.393d60		85 2a		sta $2a		                STA OPL2_REG_OFFSET
+.393d62		a9 00		lda #$00	                LDA #$00
+.393d64		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
+.393d66		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393d68		18		clc		                CLC
+.393d69		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
+.393d6c		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
+.393d6e		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393d70		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393d73		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393d75		e2 20		sep #$20	                SEP #$20        ; set A short
+.393d77		a5 32		lda $32		                LDA OPL2_PARAMETER0
+.393d79		29 01		and #$01	                AND #$01
+.393d7b		f0 02		beq $393d7f	                BEQ SET_KEYON_OFF
+.393d7d		a9 20		lda #$20	                LDA #$20
+.393d7f						    SET_KEYON_OFF
+.393d7f		85 32		sta $32		                STA OPL2_PARAMETER0
+.393d81		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393d83		29 df		and #$df	                AND #$DF
+.393d85		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393d87		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393d89		60		rts		                RTS
+.393d8a						OPL2_SET_FEEDBACK
+.393d8a		48		pha		                PHA             ; begin setdp macro
+.393d8b		08		php		                PHP
+.393d8c		c2 20		rep #$20	                REP #$20        ; set A long
+.393d8e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393d91		5b		tcd		                TCD
+.393d92		28		plp		                PLP
+.393d93		68		pla		                PLA             ; end setdp macro
+.393d94		e2 20		sep #$20	                SEP #$20        ; set A short
+.393d96		18		clc		              CLC
+.393d97		a5 27		lda $27		              LDA OPL2_CHANNEL
+.393d99		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
+.393d9b		69 c0		adc #$c0	              ADC #$C0
+.393d9d		85 2a		sta $2a		              STA OPL2_REG_OFFSET
+.393d9f		a9 00		lda #$00	              LDA #$00
+.393da1		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
+.393da3		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393da5		18		clc		              CLC
+.393da6		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.393da9		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
+.393dab		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393dad		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393db0		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393db2		e2 20		sep #$20	                SEP #$20        ; set A short
+.393db4		a5 32		lda $32		              LDA OPL2_PARAMETER0
+.393db6		29 07		and #$07	              AND #$07
+.393db8		0a		asl a		              ASL
+.393db9		85 32		sta $32		              STA OPL2_PARAMETER0
+.393dbb		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393dbd		29 01		and #$01	              AND #$01
+.393dbf		05 32		ora $32		              ORA OPL2_PARAMETER0
+.393dc1		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393dc3		6b		rtl		                RTL
+.393dc4						OPL2_SET_SYNTHMODE
+.393dc4		48		pha		                PHA             ; begin setdp macro
+.393dc5		08		php		                PHP
+.393dc6		c2 20		rep #$20	                REP #$20        ; set A long
+.393dc8		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393dcb		5b		tcd		                TCD
+.393dcc		28		plp		                PLP
+.393dcd		68		pla		                PLA             ; end setdp macro
+.393dce		08		php		              PHP ; Push the Carry
+.393dcf		e2 20		sep #$20	                SEP #$20        ; set A short
+.393dd1		18		clc		              CLC
+.393dd2		a5 27		lda $27		              LDA OPL2_CHANNEL
+.393dd4		29 0f		and #$0f	              AND #$0F  ; This is just precaution, it should be between 0 to 8
+.393dd6		69 c0		adc #$c0	              ADC #$C0
+.393dd8		85 2a		sta $2a		              STA OPL2_REG_OFFSET
+.393dda		a9 00		lda #$00	              LDA #$00
+.393ddc		85 2b		sta $2b		              STA OPL2_REG_OFFSET+1;
+.393dde		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393de0		18		clc		              CLC
+.393de1		a9 00 e6	lda #$e600	              LDA #<>OPL3_R_BASE
+.393de4		65 2a		adc $2a		              ADC OPL2_REG_OFFSET
+.393de6		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393de8		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393deb		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393ded		28		plp		              PLP ; Pull the Carry out
+.393dee		e2 20		sep #$20	                SEP #$20        ; set A short
+.393df0		b0 08		bcs $393dfa	              BCS OPL2_Set_Synthmode_Set;
+.393df2		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393df4		29 fe		and #$fe	              AND #$FE
+.393df6		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393df8		80 06		bra $393e00	              BRA OPL2_Set_Synthmode_Exit
+.393dfa						OPL2_Set_Synthmode_Set
+.393dfa		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393dfc		09 01		ora #$01	              ORA #$01
+.393dfe		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393e00						OPL2_Set_Synthmode_Exit
+.393e00		6b		rtl		                RTL
+.393e01						OPL2_SET_DEEPTREMOLO
+.393e01		48		pha		                PHA             ; begin setdp macro
+.393e02		08		php		                PHP
+.393e03		c2 20		rep #$20	                REP #$20        ; set A long
+.393e05		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393e08		5b		tcd		                TCD
+.393e09		28		plp		                PLP
+.393e0a		68		pla		                PLA             ; end setdp macro
+.393e0b		c2 20		rep #$20	                REP #$20        ; set A long
+.393e0d		a9 bd e6	lda #$e6bd	              LDA #<>OPL3_R_BASE + $00BD
+.393e10		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393e12		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393e15		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393e17		e2 20		sep #$20	                SEP #$20        ; set A short
+.393e19		b0 08		bcs $393e23	              BCS OPL2_Set_DeepTremolo_Set;
+.393e1b		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393e1d		29 7f		and #$7f	              AND #$7F
+.393e1f		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393e21		80 06		bra $393e29	              BRA OPL2_Set_DeepTremolo_Exit
+.393e23						OPL2_Set_DeepTremolo_Set
+.393e23		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393e25		09 80		ora #$80	              ORA #$80
+.393e27		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393e29						OPL2_Set_DeepTremolo_Exit
+.393e29		6b		rtl		                RTL
+.393e2a						OPL2_SET_DEEPVIBRATO
+.393e2a		48		pha		                PHA             ; begin setdp macro
+.393e2b		08		php		                PHP
+.393e2c		c2 20		rep #$20	                REP #$20        ; set A long
+.393e2e		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393e31		5b		tcd		                TCD
+.393e32		28		plp		                PLP
+.393e33		68		pla		                PLA             ; end setdp macro
+.393e34		c2 20		rep #$20	                REP #$20        ; set A long
+.393e36		a9 bd e6	lda #$e6bd	              LDA #<>OPL3_R_BASE + $00BD
+.393e39		85 2c		sta $2c		              STA OPL2_IND_ADDY_LL
+.393e3b		a9 af 00	lda #$00af	              LDA #`OPL3_R_BASE
+.393e3e		85 2e		sta $2e		              STA OPL2_IND_ADDY_HL
+.393e40		e2 20		sep #$20	                SEP #$20        ; set A short
+.393e42		b0 08		bcs $393e4c	              BCS OPL2_Set_DeepVibrato_Set;
+.393e44		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393e46		29 bf		and #$bf	              AND #$BF
+.393e48		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393e4a		80 06		bra $393e52	              BRA OPL2_Set_DeepVibrato_Exit
+.393e4c						OPL2_Set_DeepVibrato_Set
+.393e4c		a7 2c		lda [$2c]	              LDA [OPL2_IND_ADDY_LL]
+.393e4e		09 40		ora #$40	              ORA #$40
+.393e50		87 2c		sta [$2c]	              STA [OPL2_IND_ADDY_LL]
+.393e52						OPL2_Set_DeepVibrato_Exit
+.393e52		6b		rtl		                RTL
+.393e53						OPL2_SET_PERCUSSION
+.393e53		48		pha		                PHA             ; begin setdp macro
+.393e54		08		php		                PHP
+.393e55		c2 20		rep #$20	                REP #$20        ; set A long
+.393e57		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393e5a		5b		tcd		                TCD
+.393e5b		28		plp		                PLP
+.393e5c		68		pla		                PLA             ; end setdp macro
+.393e5d		c2 20		rep #$20	                REP #$20        ; set A long
+.393e5f		a9 bd e6	lda #$e6bd	                LDA #<>OPL3_R_BASE + $00BD
+.393e62		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393e64		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393e67		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393e69		e2 20		sep #$20	                SEP #$20        ; set A short
+.393e6b		b0 08		bcs $393e75	                BCS OPL2_Set_Percussion_Set;
+.393e6d		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393e6f		29 df		and #$df	                AND #$DF
+.393e71		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393e73		80 06		bra $393e7b	                BRA OPL2_Set_Percussion_Exit
+.393e75						OPL2_Set_Percussion_Set
+.393e75		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393e77		09 20		ora #$20	                ORA #$20
+.393e79		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393e7b						OPL2_Set_Percussion_Exit
+.393e7b		6b		rtl		                RTL
+.393e7c						OPL2_SET_DRUMS
+.393e7c		48		pha		                PHA             ; begin setdp macro
+.393e7d		08		php		                PHP
+.393e7e		c2 20		rep #$20	                REP #$20        ; set A long
+.393e80		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393e83		5b		tcd		                TCD
+.393e84		28		plp		                PLP
+.393e85		68		pla		                PLA             ; end setdp macro
+.393e86		c2 20		rep #$20	                REP #$20        ; set A long
+.393e88		a9 bd e6	lda #$e6bd	                LDA #<>OPL3_R_BASE + $00BD
+.393e8b		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393e8d		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393e90		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393e92		e2 20		sep #$20	                SEP #$20        ; set A short
+.393e94		a5 32		lda $32		                LDA OPL2_PARAMETER0
+.393e96		29 1f		and #$1f	                AND #$1F
+.393e98		85 32		sta $32		                STA OPL2_PARAMETER0
+.393e9a		49 ff		eor #$ff	                EOR #$FF
+.393e9c		85 33		sta $33		                STA OPL2_PARAMETER1
+.393e9e		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393ea0		25 33		and $33		                AND OPL2_PARAMETER1
+.393ea2		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393ea4		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393ea6		6b		rtl		                RTL
+.393ea7						OPL2_SET_WAVEFORM
+.393ea7		48		pha		                PHA             ; begin setdp macro
+.393ea8		08		php		                PHP
+.393ea9		c2 20		rep #$20	                REP #$20        ; set A long
+.393eab		a9 00 00	lda #$0000	                LDA #BANK0_BEGIN         ; set DP to page 0
+.393eae		5b		tcd		                TCD
+.393eaf		28		plp		                PLP
+.393eb0		68		pla		                PLA             ; end setdp macro
+.393eb1		c2 20		rep #$20	                REP #$20        ; set A long
+.393eb3		a9 e0 00	lda #$00e0	                LDA #$00E0;
+.393eb6		85 28		sta $28		                STA OPL2_REG_REGION
+.393eb8		20 cc 3e	jsr $393ecc	                JSR OPL2_GET_REG_OFFSET
+.393ebb		e2 20		sep #$20	                SEP #$20        ; set A short
+.393ebd		a5 32		lda $32		                LDA OPL2_PARAMETER0
+.393ebf		29 03		and #$03	                AND #$03
+.393ec1		85 32		sta $32		                STA OPL2_PARAMETER0
+.393ec3		a7 2c		lda [$2c]	                LDA [OPL2_IND_ADDY_LL]
+.393ec5		29 fc		and #$fc	                AND #$FC
+.393ec7		05 32		ora $32		                ORA OPL2_PARAMETER0
+.393ec9		87 2c		sta [$2c]	                STA [OPL2_IND_ADDY_LL]
+.393ecb		6b		rtl		                RTL
+.393ecc						OPL2_GET_REG_OFFSET
+.393ecc		e2 30		sep #$30	                SEP #$30        ; set A&X short
+.393ece		a5 27		lda $27		                LDA OPL2_CHANNEL
+.393ed0		29 0f		and #$0f	                AND #$0F
+.393ed2		aa		tax		                TAX
+.393ed3		a5 26		lda $26		                LDA OPL2_OPERATOR   ; 0 = operator 1, other = operator 2
+.393ed5		d0 06		bne $393edd	                BNE OPL2_Get_Register_Offset_l0
+.393ed7		bf 14 15 39	lda $391514,x	                LDA @lregisterOffsets_operator0, X
+.393edb		80 04		bra $393ee1	                BRA OPL2_Get_Register_Offset_exit
+.393edd						OPL2_Get_Register_Offset_l0
+.393edd		bf 1d 15 39	lda $39151d,x	                LDA @lregisterOffsets_operator1, X
+.393ee1						OPL2_Get_Register_Offset_exit
+.393ee1		85 2a		sta $2a		                STA OPL2_REG_OFFSET
+.393ee3		a9 00		lda #$00	                LDA #$00
+.393ee5		85 2b		sta $2b		                STA OPL2_REG_OFFSET+1;
+.393ee7		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393ee9		18		clc		                CLC
+.393eea		a9 00 e6	lda #$e600	                LDA #<>OPL3_R_BASE
+.393eed		65 2a		adc $2a		                ADC OPL2_REG_OFFSET
+.393eef		65 28		adc $28		                ADC OPL2_REG_REGION ; Ex: $20, or $40, $60, $80 (in 16bits)
+.393ef1		85 2c		sta $2c		                STA OPL2_IND_ADDY_LL
+.393ef3		a9 af 00	lda #$00af	                LDA #`OPL3_R_BASE
+.393ef6		85 2e		sta $2e		                STA OPL2_IND_ADDY_HL
+.393ef8		60		rts		                RTS
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Defines/sdcard_controller_def.asm
+
+=$afea00					SDC_VERSION_REG         = $AFEA00    ; Ought to read 12
+=$afea01					SDC_CONTROL_REG         = $AFEA01    ; Bit0 1 = Reset core logic, and registers. Self clearing
+=$afea02					SDC_TRANS_TYPE_REG      = $AFEA02  ; Bit[1:0]
+=$00						SDC_TRANS_DIRECT      = $00   ; 00 = Direct Access
+=$01						SDC_TRANS_INIT_SD     = $01   ; 01 = Init SD
+=$02						SDC_TRANS_READ_BLK    = $02   ; 10 = RW_READ_BLOCK (512 Bytes)
+=$03						SDC_TRANS_WRITE_BLK   = $03   ; 11 = RW_WRITE_SD_BLOCK
+=$afea03					SDC_TRANS_CONTROL_REG   = $AFEA03
+=$01						SDC_TRANS_START         = $01
+=$afea04					SDC_TRANS_STATUS_REG    = $AFEA04
+=$01						SDC_TRANS_BUSY          = $01     ;  1= Transaction Busy
+=$afea05					SDC_TRANS_ERROR_REG     = $AFEA05
+=$00						SDC_TRANS_INIT_NO_ERR   = $00   ; Init Error Report [1:0]
+=$01						SDC_TRANS_INIT_CMD0_ERR = $01
+=$02						SDC_TRANS_INIT_CMD1_ERR = $02
+=$00						SDC_TRANS_RD_NO_ERR     = $00   ; Read Error Report [3:2]
+=$04						SDC_TRANS_RD_CMD_ERR    = $04
+=$08						SDC_TRANS_RD_TOKEN_ERR  = $08
+=$00						SDC_TRANS_WR_NO_ERR     = $00   ; Write Report Error  [5:4]
+=$10						SDC_TRANS_WR_CMD_ERR    = $10   ;
+=$20						SDC_TRANS_WR_DATA_ERR   = $20
+=$30						SDC_TRANS_WR_BUSY_ERR   = $30
+=$afea06					SDC_DIRECT_ACCESS_REG   = $AFEA06 ; SPI Direct Read and Write - Set DATA before initiating direct Access Transaction
+=$afea07					SDC_SD_ADDR_7_0_REG     = $AFEA07 ; Set the ADDR before a block read or block write
+=$afea08					SDC_SD_ADDR_15_8_REG    = $AFEA08 ; Addr0 [8:0] Always should be 0, since each block is 512Bytes
+=$afea09					SDC_SD_ADDR_23_16_REG   = $AFEA09
+=$afea0a					SDC_SD_ADDR_31_24_REG   = $AFEA0A
+=$afea0b					SDC_SPI_CLK_DEL_REG     = $AFEA0B
+=$afea10					SDC_RX_FIFO_DATA_REG    = $AFEA10 ; Data from the Block Read
+=$afea12					SDC_RX_FIFO_DATA_CNT_HI = $AFEA12 ; How many Bytes in the FIFO HI
+=$afea13					SDC_RX_FIFO_DATA_CNT_LO = $AFEA13 ; How many Bytes in the FIFO LO
+=$afea14					SDC_RX_FIFO_CTRL_REG    = $AFEA14 ; Bit0  Force Empty - Set to 1 to clear FIFO, self clearing (the bit)
+=$afea20					SDC_TX_FIFO_DATA_REG    = $AFEA20 ; Write Data Block here
+=$afea24					SDC_TX_FIFO_CTRL_REG    = $AFEA24 ; Bit0  Force Empty - Set to 1 to clear FIFO, self clearing (the bit)
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\sdos.asm
+
+
+;******  Processing file: src\sdos_fat.asm
+
+
+;******  Processing file: src\sdos_bios.asm
+
+=$80						BIOS_TIMEOUT = $80              ; Flag to indicate if a time out has occurred (see ISETTIMEOUT)
+=0						BIOS_DEV_FDC = 0                ; Floppy 0
+=1						BIOS_DEV_FD1 = 1                ; Future support: Floppy 1 (not likely to be attached)
+=2						BIOS_DEV_SD = 2                 ; SD card, partition 0
+=3						BIOS_DEV_SD1 = 3                ; Future support: SD card, partition 1
+=4						BIOS_DEV_SD2 = 4                ; Future support: SD card, partition 2
+=5						BIOS_DEV_SD3 = 5                ; Future support: SD card, partition 3
+=6						BIOS_DEV_HD0 = 6                ; Future support: IDE Drive 0, partition 0
+=7						BIOS_DEV_HD1 = 7                ; Future support: IDE Drive 0, partition 1
+=8						BIOS_DEV_HD2 = 8                ; Future support: IDE Drive 0, partition 2
+=9						BIOS_DEV_HD3 = 9                ; Future support: IDE Drive 0, partition 3
+=$80						BIOS_ERR_BADDEV = $80           ; BIOS bad device # error
+=$81						BIOS_ERR_MOUNT = $81            ; BIOS failed to mount the device
+=$82						BIOS_ERR_READ = $82             ; BIOS failed to read from a device
+=$83						BIOS_ERR_WRITE = $83            ; BIOS failed to write to a device
+=$84						BIOS_ERR_TRACK = $84            ; BIOS failed to seek to the correct track
+=$85						BIOS_ERR_CMD = $85              ; A general block device command error
+=$86						BIOS_ERR_WRITEPROT = $86        ; The media was write-protected
+=$87						BIOS_ERR_NOMEDIA = $87          ; No media detected... unable to read/write in time
+=$88						BIOS_ERR_RESULT = $88           ; Couldn't get the result bytes for some reason
+=$89						BIOS_ERR_OOS = $89              ; FDC state is somehow out of sync with the driver.
+=$8a						BIOS_ERR_NOTATA = $8A           ; IDE drive is not ATA
+=$8b						BIOS_ERR_NOTINIT = $8B          ; Could not initilize the device
+=$8c						BIOS_ERR_TIMEOUT = $8C          ; Timeout error
+.393ef9						ITRACE
+.393ef9		08		php		                PHP
+.393efa		c2 30		rep #$30	                REP #$30        ; set A&X long
+.393efc		8b		phb		                PHB                 ; Print the text
+.393efd		a3 06		lda $06,s	                LDA #6,S            ; Get bits[15..0] of string pointer
+.393eff		aa		tax		                TAX                 ; ... into X
+.393f00		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f02		a3 08		lda $08,s	                LDA #8,S            ; Get bits[23..16] of string pointer
+.393f04		48		pha		                PHA
+.393f05		ab		plb		                PLB                 ; ... into B
+.393f06		22 68 07 39	jsl $390768	                JSL IPUTS           ; Print the string
+.393f0a		c2 20		rep #$20	                REP #$20        ; set A long
+.393f0c		a3 04		lda $04,s	                LDA #4,S            ; Move P and return address down over the string pointer
+.393f0e		83 08		sta $08,s	                STA #8,S
+.393f10		a3 02		lda $02,s	                LDA #2,S
+.393f12		83 06		sta $06,s	                STA #6,S
+.393f14		ab		plb		                PLB
+.393f15		68		pla		                PLA                 ; Clean up the stack
+.393f16		68		pla		                PLA
+.393f17		28		plp		                PLP
+.393f18		6b		rtl		                RTL
+.393f19						ISETTIMEOUT
+.393f19		8b		phb		                PHB
+.393f1a		0b		phd		                PHD
+.393f1b		08		php		                PHP
+.393f1c		48		pha		                PHA             ; begin setdbr macro
+.393f1d		08		php		                PHP
+.393f1e		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f20		a9 00		lda #$00	                LDA #0
+.393f22		48		pha		                PHA
+.393f23		ab		plb		                PLB
+.393f24		28		plp		                PLP
+.393f25		68		pla		                PLA             ; end setdbr macro
+.393f26		48		pha		                PHA             ; begin setdp macro
+.393f27		08		php		                PHP
+.393f28		c2 20		rep #$20	                REP #$20        ; set A long
+.393f2a		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.393f2d		5b		tcd		                TCD
+.393f2e		28		plp		                PLP
+.393f2f		68		pla		                PLA             ; end setdp macro
+.393f30		78		sei		                SEI                             ; We don't want to be interrupted
+.393f31		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f33		85 0d		sta $032d	                STA @b BIOS_TIMER               ; Set the number of ticks to wait
+.393f35		a5 0c		lda $032c	                LDA @b BIOS_FLAGS               ; Clear the BIOS_TIMEOUT flag
+.393f37		29 7f		and #$7f	                AND #~BIOS_TIMEOUT
+.393f39		85 0c		sta $032c	                STA @b BIOS_FLAGS
+.393f3b		28		plp		done            PLP
+.393f3c		2b		pld		                PLD
+.393f3d		ab		plb		                PLB
+.393f3e		6b		rtl		                RTL
+.393f3f						ICMDBLOCK
+.393f3f		0b		phd		                PHD
+.393f40		08		php		                PHP
+.393f41		48		pha		                PHA             ; begin setdp macro
+.393f42		08		php		                PHP
+.393f43		c2 20		rep #$20	                REP #$20        ; set A long
+.393f45		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.393f48		5b		tcd		                TCD
+.393f49		28		plp		                PLP
+.393f4a		68		pla		                PLA             ; end setdp macro
+.393f4b		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f4d		a5 01		lda $0321	                LDA BIOS_DEV                ; Get the device number
+.393f4f		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC           ; Check to see if we're sending to the floppy
+.393f51		d0 06		bne $393f59	                BNE ret_success             ; No: just return
+.393f53		22 f5 66 39	jsl $3966f5	                JSL FDC_CMDBLOCK            ; Yes: call upon the floppy code
+.393f57		90 0c		bcc $393f65	                BCC pass_failure
+.393f59						ret_success
+.393f59		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f5b		64 00		stz $0320	                STZ BIOS_STATUS
+.393f5d		28		plp		                PLP
+.393f5e		2b		pld		                PLD
+.393f5f		38		sec		                SEC
+.393f60		6b		rtl		                RTL
+.393f61						ret_failure
+.393f61		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f63		85 00		sta $0320	                STA BIOS_STATUS
+.393f65		28		plp		pass_failure    PLP
+.393f66		2b		pld		                PLD
+.393f67		18		clc		                CLC
+.393f68		6b		rtl		                RTL
+.393f69						IGETBLOCK
+.393f69		5a		phy		                PHY
+.393f6a		0b		phd		                PHD
+.393f6b		8b		phb		                PHB
+.393f6c		08		php		                PHP
+.393f6d		48		pha		                PHA             ; begin setdbr macro
+.393f6e		08		php		                PHP
+.393f6f		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f71		a9 00		lda #$00	                LDA #0
+.393f73		48		pha		                PHA
+.393f74		ab		plb		                PLB
+.393f75		28		plp		                PLP
+.393f76		68		pla		                PLA             ; end setdbr macro
+.393f77		48		pha		                PHA             ; begin setdp macro
+.393f78		08		php		                PHP
+.393f79		c2 20		rep #$20	                REP #$20        ; set A long
+.393f7b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.393f7e		5b		tcd		                TCD
+.393f7f		28		plp		                PLP
+.393f80		68		pla		                PLA             ; end setdp macro
+.393f81		e2 20		sep #$20	                SEP #$20        ; set A short
+.393f83		a0 00 00	ldy #$0000	                LDY #0
+.393f86		a9 5a		lda #$5a	                LDA #$5A                            ; Fill the buffer with a pattern we can recognize
+.393f88		97 06		sta [$0326],y	clr_loop        STA [BIOS_BUFF_PTR],Y               ; To make errors loading obvious
+.393f8a		c8		iny		                INY
+.393f8b		c0 00 02	cpy #$0200	                CPY #512
+.393f8e		d0 f8		bne $393f88	                BNE clr_loop
+.393f90		a5 01		lda $0321	                LDA BIOS_DEV                        ; Check the device number
+.393f92		c9 02		cmp #$02	                CMP #BIOS_DEV_SD                    ; Is it for the SDC?
+.393f94		f0 14		beq $393faa	                BEQ sd_getblock                     ; Yes: go to the SDC GETBLOCK routine
+.393f96		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC                   ; Is it for the floppy drive?
+.393f98		f0 18		beq $393fb2	                BEQ fd_getblock                     ; Yes: go to the FDC GETBLOCK routine
+.393f9a		c9 06		cmp #$06	                CMP #BIOS_DEV_HD0                   ; Is it for the IDE drive?
+.393f9c		f0 1c		beq $393fba	                BEQ hd_getblock
+.393f9e		a9 80		lda #$80	                LDA #BIOS_ERR_BADDEV                ; Otherwise: return a bad device error
+.393fa0						ret_failure
+.393fa0		e2 20		sep #$20	                SEP #$20        ; set A short
+.393fa2		85 00		sta $0320	                STA BIOS_STATUS                     ; Set BIOS STATUS
+.393fa4		28		plp		                PLP
+.393fa5		ab		plb		                PLB
+.393fa6		2b		pld		                PLD
+.393fa7		7a		ply		                PLY
+.393fa8		38		sec		                SEC                                 ; Return failure
+.393fa9		6b		rtl		                RTL
+.393faa		22 17 5c 39	jsl $395c17	sd_getblock     JSL SDC_GETBLOCK                    ; Call the SDC GETBLOCK routine
+.393fae		b0 12		bcs $393fc2	                BCS ret_success
+.393fb0		80 ee		bra $393fa0	                BRA ret_failure
+.393fb2		22 fa 64 39	jsl $3964fa	fd_getblock     JSL FDC_GETBLOCK                    ; Call the FDC GETBLOCK routine
+.393fb6		b0 0a		bcs $393fc2	                BCS ret_success
+.393fb8		80 e6		bra $393fa0	                BRA ret_failure
+.393fba		22 0e 6b 39	jsl $396b0e	hd_getblock     JSL IDE_GETBLOCK                    ; Call the IDE GETBLOCK routine
+.393fbe		b0 02		bcs $393fc2	                BCS ret_success
+.393fc0		80 de		bra $393fa0	                BRA ret_failure
+.393fc2						ret_success
+.393fc2		e2 20		sep #$20	                SEP #$20        ; set A short
+.393fc4		64 00		stz $0320	                STZ BIOS_STATUS                     ; Set BIOS STATUS to OK
+.393fc6		28		plp		                PLP
+.393fc7		ab		plb		                PLB
+.393fc8		2b		pld		                PLD
+.393fc9		7a		ply		                PLY
+.393fca		38		sec		                SEC                                 ; Return success
+.393fcb		6b		rtl		                RTL
+.393fcc						IPUTBLOCK
+.393fcc		0b		phd		                PHD
+.393fcd		8b		phb		                PHB
+.393fce		08		php		                PHP
+.393fcf		48		pha		                PHA             ; begin setdbr macro
+.393fd0		08		php		                PHP
+.393fd1		e2 20		sep #$20	                SEP #$20        ; set A short
+.393fd3		a9 00		lda #$00	                LDA #0
+.393fd5		48		pha		                PHA
+.393fd6		ab		plb		                PLB
+.393fd7		28		plp		                PLP
+.393fd8		68		pla		                PLA             ; end setdbr macro
+.393fd9		48		pha		                PHA             ; begin setdp macro
+.393fda		08		php		                PHP
+.393fdb		c2 20		rep #$20	                REP #$20        ; set A long
+.393fdd		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.393fe0		5b		tcd		                TCD
+.393fe1		28		plp		                PLP
+.393fe2		68		pla		                PLA             ; end setdp macro
+.393fe3		e2 20		sep #$20	                SEP #$20        ; set A short
+.393fe5		a5 01		lda $0321	                LDA BIOS_DEV                        ; Check the device number
+.393fe7		c9 02		cmp #$02	                CMP #BIOS_DEV_SD                    ; Is it for the SDC?
+.393fe9		f0 13		beq $393ffe	                BEQ sd_putblock                     ; Yes: go to the SDC PUTBLOCK routine
+.393feb		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC                   ; Is it for the FDC?
+.393fed		f0 17		beq $394006	                BEQ fd_putblock                     ; Yes: go to the FDC PUTBLOCK routine
+.393fef		c9 06		cmp #$06	                CMP #BIOS_DEV_HD0                   ; Is it for the IDE drive?
+.393ff1		f0 1b		beq $39400e	                BEQ hd_putblock
+.393ff3		a9 80		lda #$80	                LDA #BIOS_ERR_BADDEV                ; Otherwise: return a bad device error
+.393ff5						ret_failure
+.393ff5		e2 20		sep #$20	                SEP #$20        ; set A short
+.393ff7		85 00		sta $0320	                STA BIOS_STATUS                     ; Set BIOS STATUS
+.393ff9		28		plp		                PLP
+.393ffa		ab		plb		                PLB
+.393ffb		2b		pld		                PLD
+.393ffc		18		clc		                CLC                                 ; Return failure
+.393ffd		6b		rtl		                RTL
+.393ffe		22 b7 5c 39	jsl $395cb7	sd_putblock     JSL SDC_PUTBLOCK                    ; Call the SDC PUTBLOCK routine
+.394002		90 f1		bcc $393ff5	                BCC ret_failure
+.394004		80 10		bra $394016	                BRA ret_success
+.394006		22 5f 65 39	jsl $39655f	fd_putblock     JSL FDC_PUTBLOCK                    ; Call the FDC PUTBLOCK routine
+.39400a		90 e9		bcc $393ff5	                BCC ret_failure
+.39400c		80 08		bra $394016	                BRA ret_success
+.39400e		22 9f 6b 39	jsl $396b9f	hd_putblock     JSL IDE_PUTBLOCK                    ; Call the IDE PUTBLOCK routine
+.394012		90 e1		bcc $393ff5	                BCC ret_failure
+.394014		80 00		bra $394016	                BRA ret_success
+.394016						ret_success
+.394016		e2 20		sep #$20	                SEP #$20        ; set A short
+.394018		64 00		stz $0320	                STZ BIOS_STATUS                     ; Set BIOS STATUS to OK
+.39401a		28		plp		                PLP
+.39401b		ab		plb		                PLB
+.39401c		2b		pld		                PLD
+.39401d		38		sec		                SEC                                 ; Return success
+.39401e		6b		rtl		                RTL
+
+;******  Return to file: src\sdos_fat.asm
+
+
+;******  Processing file: src\sdos_dir.asm
+
+.39401f						DOS_DIROPEN
+.39401f		da		phx		                PHX
+.394020		5a		phy		                PHY
+.394021		0b		phd		                PHD
+.394022		8b		phb		                PHB
+.394023		08		php		                PHP
+.394024		48		pha		                PHA             ; begin setdbr macro
+.394025		08		php		                PHP
+.394026		e2 20		sep #$20	                SEP #$20        ; set A short
+.394028		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.39402a		48		pha		                PHA
+.39402b		ab		plb		                PLB
+.39402c		28		plp		                PLP
+.39402d		68		pla		                PLA             ; end setdbr macro
+.39402e		48		pha		                PHA             ; begin setdp macro
+.39402f		08		php		                PHP
+.394030		c2 20		rep #$20	                REP #$20        ; set A long
+.394032		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394035		5b		tcd		                TCD
+.394036		28		plp		                PLP
+.394037		68		pla		                PLA             ; end setdp macro
+.394038		ad 20 a0	lda $38a020	                LDA ROOT_DIR_FIRST_CLUSTER  ; Set the cluster (or sector for FAT12)
+.39403b		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID        ; to that of the root directory's start
+.39403e		ad 22 a0	lda $38a022	                LDA ROOT_DIR_FIRST_CLUSTER+2
+.394041		8d 34 a0	sta $38a034	                STA DOS_DIR_BLOCK_ID+2
+.394044		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Point to the directory cluster buffer for loading
+.394047		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.394049		85 18		sta $0338	                STA DOS_DIR_PTR
+.39404b		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.39404e		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.394050		85 1a		sta $033a	                STA DOS_DIR_PTR+2
+.394052		e2 20		sep #$20	                SEP #$20        ; set A short
+.394054		ad 01 a0	lda $38a001	                LDA FILE_SYSTEM             ; Check the file system
+.394057		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12        ; Is it FAT12?
+.394059		d0 24		bne $39407f	                BNE fetch_fat32             ; No: handle processing the diretory as FAT32
+.39405b						fetch_fat12
+.39405b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39405d		a9 00		lda #$00	                LDA #DOS_DIR_TYPE_FAT12ROOT ; Set the directory type to FAT12 root directory
+.39405f		8d 45 a0	sta $38a045	                STA DOS_DIR_TYPE
+.394062		c2 20		rep #$20	                REP #$20        ; set A long
+.394064		a5 18		lda $0338	                LDA DOS_DIR_PTR             ; Set the BIOS buffer pointer
+.394066		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394068		a5 1a		lda $033a	                LDA DOS_DIR_PTR+2
+.39406a		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.39406c		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the LBA of the sector
+.39406f		85 02		sta $0322	                STA BIOS_LBA
+.394071		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.394074		85 04		sta $0324	                STA BIOS_LBA+2
+.394076		22 44 10 00	jsl $001044	                JSL GETBLOCK                ; Get the sector from the FAT12 device
+.39407a		b0 1f		bcs $39409b	                BCS do_success              ; If sucessful, set the directory cursor
+.39407c		82 10 17	brl $39578f	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
+.39407f						fetch_fat32
+.39407f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394081		a9 01		lda #$01	                LDA #DOS_DIR_TYPE_FILE      ; Set the directory type to file type (all FAT32, any FAT12 subdirectory)
+.394083		8d 45 a0	sta $38a045	                STA DOS_DIR_TYPE
+.394086		c2 20		rep #$20	                REP #$20        ; set A long
+.394088		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID
+.39408b		85 10		sta $0330	                STA DOS_CLUS_ID
+.39408d		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.394090		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394092		22 02 46 39	jsl $394602	                JSL DOS_GETCLUSTER          ; Try to read the first cluster
+.394096		b0 03		bcs $39409b	                BCS do_success              ; If successful: set the directory cursor
+.394098		82 f4 16	brl $39578f	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
+.39409b		82 f8 16	brl $395796	do_success      BRL IF_SUCCESS
+.39409e						DOS_DIRFIRST
+.39409e		0b		phd		                PHD
+.39409f		08		php		                PHP
+.3940a0		48		pha		                PHA             ; begin setdp macro
+.3940a1		08		php		                PHP
+.3940a2		c2 20		rep #$20	                REP #$20        ; set A long
+.3940a4		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3940a7		5b		tcd		                TCD
+.3940a8		28		plp		                PLP
+.3940a9		68		pla		                PLA             ; end setdp macro
+.3940aa		c2 20		rep #$20	                REP #$20        ; set A long
+.3940ac		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER
+.3940af		85 18		sta $0338	                STA DOS_DIR_PTR
+.3940b1		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.3940b4		85 1a		sta $033a	                STA DOS_DIR_PTR+2
+.3940b6		28		plp		                PLP
+.3940b7		2b		pld		                PLD
+.3940b8		6b		rtl		                RTL
+.3940b9						DOS_DIRNEXT
+.3940b9		da		phx		                PHX
+.3940ba		5a		phy		                PHY
+.3940bb		0b		phd		                PHD
+.3940bc		8b		phb		                PHB
+.3940bd		08		php		                PHP
+.3940be		48		pha		                PHA             ; begin setdbr macro
+.3940bf		08		php		                PHP
+.3940c0		e2 20		sep #$20	                SEP #$20        ; set A short
+.3940c2		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3940c4		48		pha		                PHA
+.3940c5		ab		plb		                PLB
+.3940c6		28		plp		                PLP
+.3940c7		68		pla		                PLA             ; end setdbr macro
+.3940c8		48		pha		                PHA             ; begin setdp macro
+.3940c9		08		php		                PHP
+.3940ca		c2 20		rep #$20	                REP #$20        ; set A long
+.3940cc		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3940cf		5b		tcd		                TCD
+.3940d0		28		plp		                PLP
+.3940d1		68		pla		                PLA             ; end setdp macro
+.3940d2		c2 20		rep #$20	                REP #$20        ; set A long
+.3940d4		18		clc		                CLC                         ; Advance the directory entry pointer to the next entry
+.3940d5		a5 18		lda $0338	                LDA DOS_DIR_PTR
+.3940d7		69 20 00	adc #$0020	                ADC #DOS_DIR_ENTRY_SIZE
+.3940da		85 18		sta $0338	                STA DOS_DIR_PTR
+.3940dc		a5 1a		lda $033a	                LDA DOS_DIR_PTR+2
+.3940de		69 00 00	adc #$0000	                ADC #0
+.3940e1		85 1a		sta $033a	                STA DOS_DIR_PTR+2
+.3940e3		38		sec		                SEC                         ; Check to see if we've reached the end of the sector buffer
+.3940e4		a9 00 a3	lda #$a300	                LDA #<>DOS_DIR_CLUSTER_END
+.3940e7		e5 18		sbc $0338	                SBC DOS_DIR_PTR
+.3940e9		85 28		sta $0348	                STA DOS_TEMP
+.3940eb		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER_END
+.3940ee		e5 1a		sbc $033a	                SBC DOS_DIR_PTR+2
+.3940f0		85 2a		sta $034a	                STA DOS_TEMP+2
+.3940f2		30 0c		bmi $394100	                BMI get_next_block          ; Yes: try to fetch the next directory entry
+.3940f4		f0 03		beq $3940f9	                BEQ check_lower
+.3940f6		82 9d 16	brl $395796	                BRL IF_SUCCESS
+.3940f9		a5 28		lda $0348	check_lower     LDA DOS_TEMP
+.3940fb		f0 03		beq $394100	                BEQ get_next_block
+.3940fd		82 96 16	brl $395796	                BRL IF_SUCCESS
+.394100						get_next_block
+.394100		e2 20		sep #$20	                SEP #$20        ; set A short
+.394102		ad 45 a0	lda $38a045	                LDA DOS_DIR_TYPE            ; Check the type of the directory
+.394105		c9 01		cmp #$01	                CMP #DOS_DIR_TYPE_FILE
+.394107		f0 38		beq $394141	                BEQ next_cluster            ; FILE TYPE: it's cluster based (FAT32, or FAT12 non-root)
+.394109						next_sector
+.394109		c2 20		rep #$20	                REP #$20        ; set A long
+.39410b		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID
+.39410e		1a		inc a		                INC A
+.39410f		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID        ; Increment the sector number (FAT12 root directory is sector based)
+.394112		c9 0a 00	cmp #$000a	                CMP #10                     ; See if we're at the end (TODO: calculate this)
+.394115		d0 07		bne $39411e	                BNE read_sector
+.394117		e2 20		sep #$20	                SEP #$20        ; set A short
+.394119		a9 00		lda #$00	                LDA #0
+.39411b		82 6d 16	brl $39578b	                BRL IF_FAILURE
+.39411e						read_sector
+.39411e		c2 20		rep #$20	                REP #$20        ; set A long
+.394120		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the LBA to the sector #
+.394123		85 02		sta $0322	                STA BIOS_LBA
+.394125		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.394128		85 04		sta $0324	                STA BIOS_LBA+2
+.39412a		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Set the pointers to the buffer
+.39412d		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.39412f		85 18		sta $0338	                STA DOS_DIR_PTR
+.394131		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.394134		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394136		85 1a		sta $033a	                STA DOS_DIR_PTR+2
+.394138		22 44 10 00	jsl $001044	                JSL GETBLOCK                ; Attempt to read the sector from the FAT12 device
+.39413c		b0 39		bcs $394177	                BCS do_success              ; If successful: set the directory cursor
+.39413e		82 4e 16	brl $39578f	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
+.394141						next_cluster
+.394141		c2 20		rep #$20	                REP #$20        ; set A long
+.394143		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Get the current block (cluster) ID
+.394146		85 10		sta $0330	                STA DOS_CLUS_ID
+.394148		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.39414b		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.39414d		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER
+.394150		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.394152		85 18		sta $0338	                STA DOS_DIR_PTR
+.394154		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.394157		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.394159		85 1a		sta $033a	                STA DOS_DIR_PTR+2
+.39415b		22 0d 4a 39	jsl $394a0d	                JSL NEXTCLUSTER             ; Try to find the next cluster
+.39415f		b0 03		bcs $394164	                BCS set_next
+.394161		82 2b 16	brl $39578f	                BRL IF_PASSFAILURE          ; If error: pass it up the chain
+.394164		a5 10		lda $0330	set_next        LDA DOS_CLUS_ID             ; Save the cluster as the current directory cluster
+.394166		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID
+.394169		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.39416b		8d 34 a0	sta $38a034	                STA DOS_DIR_BLOCK_ID+2
+.39416e		22 02 46 39	jsl $394602	                JSL DOS_GETCLUSTER          ; Try to read the first cluster
+.394172		b0 03		bcs $394177	                BCS do_success              ; If successful: set the directory cursor
+.394174		82 18 16	brl $39578f	                BRL IF_PASSFAILURE          ; Otherwise: pass up the failure
+.394177		82 1c 16	brl $395796	do_success      BRL IF_SUCCESS
+.39417a						DOS_DIRFINDFREE
+.39417a		da		phx		                PHX
+.39417b		5a		phy		                PHY
+.39417c		0b		phd		                PHD
+.39417d		8b		phb		                PHB
+.39417e		08		php		                PHP
+.39417f		48		pha		                PHA             ; begin setdbr macro
+.394180		08		php		                PHP
+.394181		e2 20		sep #$20	                SEP #$20        ; set A short
+.394183		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394185		48		pha		                PHA
+.394186		ab		plb		                PLB
+.394187		28		plp		                PLP
+.394188		68		pla		                PLA             ; end setdbr macro
+.394189		48		pha		                PHA             ; begin setdp macro
+.39418a		08		php		                PHP
+.39418b		c2 20		rep #$20	                REP #$20        ; set A long
+.39418d		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394190		5b		tcd		                TCD
+.394191		28		plp		                PLP
+.394192		68		pla		                PLA             ; end setdp macro
+.394193		22 18 54 39	jsl $395418	                JSL IF_DIROPEN
+.394197		b0 06		bcs $39419f	                BCS start_walk
+.394199		a9 08 00	lda #$0008	                LDA #DOS_ERR_NODIR          ; Return that we could not read the directory
+.39419c		82 28 00	brl $3941c7	                BRL ret_failure
+.39419f		a0 00 00	ldy #$0000	start_walk      LDY #0                      ; We check the first character of the entry
+.3941a2						chk_entry
+.3941a2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3941a4		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y         ; Get the first byte of the directory entry
+.3941a6		f0 1c		beq $3941c4	                BEQ ret_success             ; If 0: we have a blank... return it
+.3941a8		c9 e5		cmp #$e5	                CMP #DOS_DIR_ENT_UNUSED     ; Is it an unused (deleted) entry?
+.3941aa		f0 18		beq $3941c4	                BEQ ret_success             ; Yes: return it
+.3941ac		22 52 54 39	jsl $395452	                JSL IF_DIRNEXT              ; Go to the next directory entry
+.3941b0		b0 ed		bcs $39419f	                BCS start_walk              ; If we got one, start walking it
+.3941b2		22 ca 41 39	jsl $3941ca	                JSL DOS_DIRAPPEND           ; If there isn't one, create a blank cluster
+.3941b6		90 0f		bcc $3941c7	                BCC ret_failure             ; If that didn't work, return the failure
+.3941b8		c2 20		rep #$20	                REP #$20        ; set A long
+.3941ba		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Return the first entry
+.3941bd		85 18		sta $0338	                STA DOS_DIR_PTR
+.3941bf		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.3941c2		85 1a		sta $033a	                STA DOS_DIR_PTR+2
+.3941c4		82 cf 15	brl $395796	ret_success     BRL IF_SUCCESS
+.3941c7		82 c1 15	brl $39578b	ret_failure     BRL IF_FAILURE
+.3941ca						DOS_DIRAPPEND
+.3941ca		da		phx		                PHX
+.3941cb		8b		phb		                PHB
+.3941cc		0b		phd		                PHD
+.3941cd		08		php		                PHP
+.3941ce		48		pha		                PHA             ; begin setdbr macro
+.3941cf		08		php		                PHP
+.3941d0		e2 20		sep #$20	                SEP #$20        ; set A short
+.3941d2		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3941d4		48		pha		                PHA
+.3941d5		ab		plb		                PLB
+.3941d6		28		plp		                PLP
+.3941d7		68		pla		                PLA             ; end setdbr macro
+.3941d8		48		pha		                PHA             ; begin setdp macro
+.3941d9		08		php		                PHP
+.3941da		c2 20		rep #$20	                REP #$20        ; set A long
+.3941dc		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3941df		5b		tcd		                TCD
+.3941e0		28		plp		                PLP
+.3941e1		68		pla		                PLA             ; end setdp macro
+.3941e2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3941e4		ad 45 a0	lda $38a045	                LDA DOS_DIR_TYPE
+.3941e7		c9 01		cmp #$01	                CMP #DOS_DIR_TYPE_FILE          ; Are we looking at a file type directory
+.3941e9		f0 09		beq $3941f4	                BEQ clr_sector                  ; Yes: clear out the directory data
+.3941eb						ret_failure
+.3941eb		e2 20		sep #$20	                SEP #$20        ; set A short
+.3941ed		a9 15		lda #$15	                LDA #DOS_ERR_DIRFULL            ; No: return a directory-full error
+.3941ef		85 0e		sta $032e	                STA DOS_STATUS
+.3941f1		82 3e 00	brl $394232	                BRL pass_failure
+.3941f4						clr_sector
+.3941f4		c2 20		rep #$20	                REP #$20        ; set A long
+.3941f6		a9 00 00	lda #$0000	                LDA #0
+.3941f9		a2 00 00	ldx #$0000	                LDX #0
+.3941fc		9d 00 a1	sta $38a100,x	clr_loop        STA DOS_DIR_CLUSTER,X           ; Clear the directory cluster
+.3941ff		e8		inx		                INX
+.394200		e8		inx		                INX
+.394201		e0 00 02	cpx #$0200	                CPX #512
+.394204		d0 f6		bne $3941fc	                BNE clr_loop
+.394206		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER          ; Point to the new, blank directory data
+.394209		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.39420b		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.39420e		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.394210		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID            ; We want to append it to the current directory
+.394213		85 10		sta $0330	                STA DOS_CLUS_ID
+.394215		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.394218		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.39421a		22 2e 4e 39	jsl $394e2e	                JSL DOS_APPENDCLUS              ; Attempt to append the blank data as a new cluster
+.39421e		90 12		bcc $394232	                BCC pass_failure                ; If there was an error, pass it up the chain
+.394220		ad 36 a0	lda $38a036	                LDA DOS_NEW_CLUSTER             ; Set the block ID of the new directory cluster
+.394223		8d 32 a0	sta $38a032	                STA DOS_DIR_BLOCK_ID
+.394226		ad 38 a0	lda $38a038	                LDA DOS_NEW_CLUSTER+2
+.394229		8d 34 a0	sta $38a034	                STA DOS_DIR_BLOCK_ID+2
+.39422c		28		plp		ret_success     PLP
+.39422d		2b		pld		                PLD
+.39422e		ab		plb		                PLB
+.39422f		fa		plx		                PLX
+.394230		38		sec		                SEC
+.394231		6b		rtl		                RTL
+.394232		28		plp		pass_failure    PLP
+.394233		2b		pld		                PLD
+.394234		ab		plb		                PLB
+.394235		fa		plx		                PLX
+.394236		18		clc		                CLC
+.394237		6b		rtl		                RTL
+.394238						DOS_DIRWRITE
+.394238		da		phx		                PHX
+.394239		5a		phy		                PHY
+.39423a		0b		phd		                PHD
+.39423b		8b		phb		                PHB
+.39423c		08		php		                PHP
+.39423d		48		pha		                PHA             ; begin setdbr macro
+.39423e		08		php		                PHP
+.39423f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394241		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394243		48		pha		                PHA
+.394244		ab		plb		                PLB
+.394245		28		plp		                PLP
+.394246		68		pla		                PLA             ; end setdbr macro
+.394247		48		pha		                PHA             ; begin setdp macro
+.394248		08		php		                PHP
+.394249		c2 20		rep #$20	                REP #$20        ; set A long
+.39424b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39424e		5b		tcd		                TCD
+.39424f		28		plp		                PLP
+.394250		68		pla		                PLA             ; end setdp macro
+.394251		e2 20		sep #$20	                SEP #$20        ; set A short
+.394253		ad 45 a0	lda $38a045	                LDA DOS_DIR_TYPE            ; Check the type of the directory
+.394256		c9 01		cmp #$01	                CMP #DOS_DIR_TYPE_FILE      ; Is it a file type directory (FAT32 or FAT12 non-root?)
+.394258		f0 1f		beq $394279	                BEQ write_cluster           ; Yes: write it back using a cluster ID
+.39425a						write_sector
+.39425a		c2 20		rep #$20	                REP #$20        ; set A long
+.39425c		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the BIOS_LBA to the LBA of the sector
+.39425f		85 02		sta $0322	                STA BIOS_LBA
+.394261		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.394264		85 04		sta $0324	                STA BIOS_LBA+2
+.394266		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Set the pointer to the directory buffer
+.394269		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.39426b		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.39426e		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394270		22 24 10 00	jsl $001024	                JSL PUTBLOCK                ; Try to write the sector to disk
+.394274		b0 1f		bcs $394295	                BCS ret_success
+.394276		82 12 15	brl $39578b	ret_failure     BRL IF_FAILURE
+.394279						write_cluster
+.394279		c2 20		rep #$20	                REP #$20        ; set A long
+.39427b		ad 32 a0	lda $38a032	                LDA DOS_DIR_BLOCK_ID        ; Set the DOS_CLUS_ID to the ID of the cluster
+.39427e		85 10		sta $0330	                STA DOS_CLUS_ID
+.394280		ad 34 a0	lda $38a034	                LDA DOS_DIR_BLOCK_ID+2
+.394283		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394285		a9 00 a1	lda #$a100	                LDA #<>DOS_DIR_CLUSTER      ; Set the pointer to the directory buffer
+.394288		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.39428a		a9 38 00	lda #$0038	                LDA #`DOS_DIR_CLUSTER
+.39428d		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.39428f		22 3f 46 39	jsl $39463f	                JSL DOS_PUTCLUSTER          ; Try to write the cluster to disk
+.394293		90 e1		bcc $394276	                BCC ret_failure
+.394295		82 fe 14	brl $395796	ret_success     BRL IF_SUCCESS
+
+;******  Return to file: src\sdos_fat.asm
+
+.0000						DEVICE_DESC
+>0000						DEVNAME         .dword ?            ; A pointer to the ASCIIZ name of the device
+>0004						DEVNUMBER       .byte ?           ; The BIOS_DEV number for the device
+>0005						NEXT            .dword ?            ; A pointer to the next device descriptor
+.0000						DIRENTRY
+>0000						SHORTNAME               .fill 11        ; $00 - The short name of the file (8 name, 3 extension)
+>000b						ATTRIBUTE               .byte ?         ; $0B - The attribute bits
+>000c						IGNORED1                .word ?         ; $0C - Unused (by us) bytes
+>000e						CREATE_TIME             .word ?         ; $0E - Creation time
+>0010						CREATE_DATE             .word ?         ; $10 - Creation date
+>0012						ACCESS_DATE             .word ?         ; $12 - Last access date
+>0014						CLUSTER_H               .word ?         ; $14 - High word of the first cluster #
+>0016						MODIFIED_TIME           .word ?         ; $16 - Last modified time
+>0018						MODIFIED_DATE           .word ?         ; $18 - Last modified date
+>001a						CLUSTER_L               .word ?         ; $1A - Low word of the first cluster #
+>001c						SIZE                    .dword ?        ; $1C - The size of the file (in bytes)
+=$01						DOS_ATTR_RO = $01                       ; File is read-only
+=$02						DOS_ATTR_HIDDEN = $02                   ; File is hidden
+=$04						DOS_ATTR_SYSTEM = $04                   ; File is a system file
+=$08						DOS_ATTR_VOLUME = $08                   ; Entry is the volume label
+=$10						DOS_ATTR_DIR = $10                      ; Entry is a directory
+=$20						DOS_ATTR_ARCH = $20                     ; Entry has changed since last backup
+=$0f						DOS_ATTR_LONGNAME = $0F                 ; Entry is the long file name
+.0000						FILEDESC
+>0000						STATUS              .byte ?             ; The status flags of the file descriptor (open, closed, error, EOF, etc.)
+>0001						DEV                 .byte ?             ; The ID of the device holding the file
+>0002						PATH                .dword ?            ; Pointer to a NULL terminated path string
+>0006						CLUSTER             .dword ?            ; The current cluster of the file.
+>000a						FIRST_CLUSTER       .dword ?            ; The ID of the first cluster in the file
+>000e						BUFFER              .dword ?            ; Pointer to a cluster-sized buffer
+>0012						SIZE                .dword ?            ; The size of the file
+>0016						CREATE_DATE         .word ?             ; The creation date of the file
+>0018						CREATE_TIME         .word ?             ; The creation time of the file
+>001a						MODIFIED_DATE       .word ?             ; The modification date of the file
+>001c						MODIFIED_TIME       .word ?             ; The modification time of the file
+>001e						RESERVED            .word ?             ; Two reserved bytes to bring the descriptor up to 32 bytes
+=$01						FD_STAT_READ = $01                      ; The file is readable
+=$02						FD_STAT_WRITE = $02                     ; The file is writable
+=$10						FD_STAT_ALLOC = $10                     ; The file descriptor has been allocated
+=$38						FD_STAT_OPEN = $38                      ; The file is open
+=$40						FD_STAT_ERROR = $40                     ; The file is in an error condition
+=$80						FD_STAT_EOF = $80                       ; The file cursor is at the end of the file
+=$0fffffff					FAT_LAST_CLUSTER = $0FFFFFFF            ; Code to mark the last cluster of a file
+=1						VOLUMEMAX = 1                           ; The maximum number of mounted volumes we support
+=32						DOS_DIR_ENTRY_SIZE = 32                 ; The size of a directory entry
+=512						DOS_SECTOR_SIZE = 512                   ; The size of a sector
+=$e5						DOS_DIR_ENT_UNUSED = $E5                ; Marker for an unused directory entry
+=$00						PART_TYPE_FAT12 = $00                   ; "Partition" type: FAT12, used for floppy disks
+=$0c						PART_TYPE_FAT32_LBA = $0C               ; Patition type: FAT32 with LBA addressing
+=$29						BPB_EXTENDED_RECORD = $29               ; If SIGNATUREB of the BPB has this byte, the volume label is valid
+=0						DOS_DIR_TYPE_FAT12ROOT = 0              ; Directory is a FAT12 root directory
+=1						DOS_DIR_TYPE_FILE = 1                   ; Directory is a file type directory
+=8						DOS_FD_MAX = 8                          ; The maximum number of open file descriptors
+=1						DOS_ERR_READ = 1                        ; We could not read a sector, check BIOS_STATUS for details
+=2						DOS_ERR_NOTMBR = 2                      ; We could not find the MBR
+=3						DOS_ERR_NOFAT32 = 3                     ; We could not find a FAT32 parition using LBA
+=4						DOS_ERR_NOINIT = 4                      ; We could not INIT the block device
+=5						DOS_ERR_VOLID = 5                       ; Volume ID sector could not be loaded
+=6						DOS_ERR_FAT = 6                         ; Can't scan the FAT for some reason
+=7						DOS_ERR_BADPATH = 7                     ; The path was badly formatted
+=8						DOS_ERR_NODIR = 8                       ; Could not read the directory
+=9						DOS_ERR_NOTFOUND = 9                    ; File/directory requested was not found
+=10						DOS_ERR_NOCLUSTER = 10                  ; There are no more clusters
+=11						DOS_ERR_FILEEXISTS = 11                 ; There is already a file of that name
+=12						DOS_ERR_NOTOPEN = 12                    ; File has not been open
+=13						DOS_ERR_NOTREAD = 13                    ; File is not open for reading
+=14						DOS_ERR_NOTWRITE = 14                   ; File is not open for writing
+=15						DOS_ERR_OPEN = 15                       ; File is already open
+=16						DOS_ERR_PGXSIG = 16                     ; File does not have the PGX signature
+=17						DOS_ERR_NOEXEC = 17                     ; File does is not an executable format
+=18						DOS_ERR_MEDIAFULL = 18                  ; There are no more free clusters on the drive
+=19						DOS_ERR_WRITEPROT = 19                  ; The medium is write-protected
+=20						DOS_ERR_FATUPDATE = 20                  ; Can't update the FAT
+=21						DOS_ERR_DIRFULL = 21                    ; The directory is full
+=22						DOS_ERR_NOFD = 22                       ; No file descriptors are available for allocation
+=446						PART0_OFF = 446                         ; Offset to the first partition in the MBR
+=4						PART_TYPE_OFF = 4                       ; Offset to the partition's type
+=8						PART_LBA_OFF = 8                        ; Offset to the LBA of the first sector of the partition
+=13						PART_SECT_COUNT_OFF = 13                ; Offset to the sector count of the partition
+=510						MBR_SIGNATURE = 510                     ; The offset to the MBR signature bytes
+=11						BPB_BYTEPERSEC_OFF = 11                 ; Offset in the BPB sector to the Bytes Per Sector
+=13						BPB_SECPERCLUS_OFF = 13                 ; Offset in the BPB sector to the Sectors Per Cluster
+=14						BPB_RSRVCLUS_OFF = 14                   ; Offset in the BPB sector to the Number of Reserved Clusters
+=16						BPB_NUMFAT_OFF = 16                     ; Offset in the BPB sector to the Number of FATs
+=17						BPB_ROOT_MAX_ENTRY_OFF = 17             ; Offset in the BPB sector to the Maximum # of entries in the root directory (FAT12)
+=19						BPB_TOTAL_SECTORS = 19                  ; Offset in the BPB sector to the number of sectors on the partition or disk (FAT12)
+=$24						BPB_SECPERFAT_OFF = $24                 ; Offset in the BPB sector to the Sectors Per FAT
+=38						BPB_SIGNATUREB = 38                     ; Offset in the BPB sector to the second signature byte
+=39						BPB_VOLUMEID = 39                       ; Offset in the BPB sector to the volume ID
+=$2c						BPB_ROOTCLUS_OFF = $2C                  ; Offset in the BPB sector to the Root Cluster Number
+=510						BPB_SIGNATURE = 510                     ; The offset to the MBR signature bytes
+
+;******  Processing file: src\Includes/sdos_fat_vars_user_inc.asm
+
+=$38a000					    DOS_HIGH_VARIABLES      = $38A000
+=$38a000					    DEVICE                  = $38A000       ; 1 byte - The number of the block device
+=$38a001					    FILE_SYSTEM             = $38A001       ; 1 byte - The type of filesystem (FAT12, FAT32, etc.)
+=$38a002					    PARTITION               = $38A002       ; 1 byte - The number of the partitions on the device
+=$38a003					    SECTORS_PER_CLUSTER     = $38A003       ; 1 byte - The number of sectors in a cluster
+=$38a004					    FIRSTSECTOR             = $38A004       ; 4 bytes - The LBA of the first sector on the volume
+=$38a008					    SECTORCOUNT             = $38A008       ; 4 bytes - The number of sectors in the volume
+=$38a00c					    NUM_RSRV_SEC            = $38A00C       ; 2 bytes - The number of hidden or reserved sectors
+=$38a00e					    CLUSTER_SIZE            = $38A00E       ; 2 bytes - The size of a cluster in bytes
+=$38a010					    SEC_PER_FAT             = $38A010       ; 4 bytes - The number of sectors per FAT
+=$38a014					    FAT_BEGIN_LBA           = $38A014       ; 4 bytes - The LBA of the first sector of FAT #1
+=$38a018					    FAT2_BEGIN_LBA          = $38A018       ; 4 bytes - The LBA of the first sector of FAT #2
+=$38a01c					    CLUSTER_BEGIN_LBA       = $38A01C       ; 4 bytes - The LBA of the first cluster in the storage area
+=$38a020					    ROOT_DIR_FIRST_CLUSTER  = $38A020       ; 4 bytes - The number of the first cluster in the root directory
+=$38a024					    ROOT_DIR_MAX_ENTRY      = $38A024       ; 2 bytes - The maximum number of entries in the root directory (0 = no limit)
+=$38a026					    VOLUME_ID               = $38A026       ; 4 bytes - The ID of the volume
+=$38a02a					    DOS_CURR_CLUS           = $38A02A       ; 4 bytes - The current cluster (for delete)
+=$38a02e					    DOS_NEXT_CLUS           = $38A02E       ; 4 bytes - The next cluster in a file (for delete)
+=$38a032					    DOS_DIR_BLOCK_ID        = $38A032       ; 4 bytes - The ID of the current directory block
+=$38a036					    DOS_NEW_CLUSTER         = $38A036       ; 4 bytes - Space to store a newly written cluster ID
+=$38a03a					    DOS_SHORT_NAME          = $38A03A       ; 11 bytes - The short name for a desired file
+=$38a045					    DOS_DIR_TYPE            = $38A045       ; 1 byte - a code indicating the type of the current directory (0 = cluster based, $80 = sector based)
+=$38a046					    DOS_CURR_DIR_ID         = $38A046       ; 4 byte - the ID of the first sector or cluster of the current directory
+=$38a04a					    DOS_DEV_NAMES           = $38A04A       ; 4 byte - pointer to the linked list of device names
+=$38a04e					    FDC_MOTOR_TIMER         = $38A04E       ; 2 bytes - count-down timer to automatically turn off the FDC spindle motor
+=$38a050					    DOS_MOUNT_DEV           = $38A050       ; 1 byte - the device code of the currently mounted device
+=$38a100					    DOS_DIR_CLUSTER         = $38A100       ; 512 bytes - A buffer for directory entries
+=$38a300					    DOS_DIR_CLUSTER_END     = $38A300       ; The byte just past the end of the directory cluster buffer
+=$38a300					    DOS_SECTOR              = $38A300       ; 512 bytes - A buffer for block device read/write
+=$38a500					    DOS_SECTOR_END          = $38A500       ; The byte just past the end of the cluster buffer
+=$38a500					    DOS_FAT_SECTORS         = $38A500       ; 1024 bytes - two sectors worth of the FAT
+=$38a900					    DOS_FAT_SECTORS_END     = $38A900       ; The byte just past the end of the FAT buffers
+=$38a900					    DOS_BOOT_SECTOR         = $38A900       ; A sector for holding the boot sector
+=$38ab00					    DOS_BOOT_SECTOR_END     = $38AB00
+=$38ab00					    DOS_SPARE_SECTOR        = $38AB00       ; A spare 512 byte buffer for loading sectors
+=$38ad00					    DOS_SPARE_SECTOR_END    = $38AD00
+=$38ad00					    DOS_SPARE_FD            = $38AD00       ; A spare file descriptor buffer
+=3714336					DOS_SPARE_FD_END        = DOS_SPARE_FD + SIZE(FILEDESC)
+=3714336					DOS_FILE_DESCS          = DOS_SPARE_FD_END
+=3714592					DOS_FILE_DESCS_END      = DOS_FILE_DESCS + SIZE(FILEDESC) * DOS_FD_MAX
+=$38b000					    DOS_FILE_BUFFS          = $38B000
+=3719168					    DOS_FILE_BUFFS_END      = DOS_FILE_BUFFS + DOS_SECTOR_SIZE * DOS_FD_MAX
+
+;******  Return to file: src\sdos_fat.asm
+
+.394298						DOS_INIT
+.394298		8b		phb		                PHB
+.394299		0b		phd		                PHD
+.39429a		08		php		                PHP
+.39429b		48		pha		                PHA             ; begin setdbr macro
+.39429c		08		php		                PHP
+.39429d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39429f		a9 00		lda #$00	                LDA #0
+.3942a1		48		pha		                PHA
+.3942a2		ab		plb		                PLB
+.3942a3		28		plp		                PLP
+.3942a4		68		pla		                PLA             ; end setdbr macro
+.3942a5		48		pha		                PHA             ; begin setdp macro
+.3942a6		08		php		                PHP
+.3942a7		c2 20		rep #$20	                REP #$20        ; set A long
+.3942a9		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3942ac		5b		tcd		                TCD
+.3942ad		28		plp		                PLP
+.3942ae		68		pla		                PLA             ; end setdp macro
+.3942af		e2 20		sep #$20	                SEP #$20        ; set A short
+.3942b1		c2 10		rep #$10	                REP #$10        ; set X long
+.3942b3		a2 00 00	ldx #$0000	                LDX #0                  ; Zero out all the bank 0 variables
+.3942b6		a9 00		lda #$00	                LDA #0
+.3942b8		9d 20 03	sta $0320,x	b0_clr_loop     STA @w SDOS_VARIABLES,X
+.3942bb		e8		inx		                INX
+.3942bc		e0 15 02	cpx #$0215	                CPX #<>(FDC_CMD_RETRY - SDOS_VARIABLES + 1)
+.3942bf		d0 f7		bne $3942b8	                BNE b0_clr_loop
+.3942c1		48		pha		                PHA             ; begin setdbr macro
+.3942c2		08		php		                PHP
+.3942c3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3942c5		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3942c7		48		pha		                PHA
+.3942c8		ab		plb		                PLB
+.3942c9		28		plp		                PLP
+.3942ca		68		pla		                PLA             ; end setdbr macro
+.3942cb		48		pha		                PHA             ; begin setdp macro
+.3942cc		08		php		                PHP
+.3942cd		c2 20		rep #$20	                REP #$20        ; set A long
+.3942cf		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3942d2		5b		tcd		                TCD
+.3942d3		28		plp		                PLP
+.3942d4		68		pla		                PLA             ; end setdp macro
+.3942d5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3942d7		c2 10		rep #$10	                REP #$10        ; set X long
+.3942d9		a2 00 00	ldx #$0000	                LDX #0                  ; Zero out all the bank $38 variables
+.3942dc		a9 00		lda #$00	                LDA #0
+.3942de		9d 00 a0	sta $38a000,x	b38_clr_loop    STA @w DOS_HIGH_VARIABLES,X
+.3942e1		e8		inx		                INX
+.3942e2		e0 01 20	cpx #$2001	                CPX #<>(DOS_FILE_BUFFS_END - DOS_HIGH_VARIABLES + 1)
+.3942e5		d0 f7		bne $3942de	                BNE b38_clr_loop
+.3942e7		c2 20		rep #$20	                REP #$20        ; set A long
+.3942e9		a9 97 46	lda #$4697	                LDA #<>DOS_HD_DESC      ; Initialize the device names list
+.3942ec		8f 4a a0 38	sta $38a04a	                STA @l DOS_DEV_NAMES
+.3942f0		a9 39 00	lda #$0039	                LDA #`DOS_HD_DESC
+.3942f3		8f 4c a0 38	sta $38a04c	                STA @l DOS_DEV_NAMES+2
+.3942f7		e2 20		sep #$20	                SEP #$20        ; set A short
+.3942f9		a9 02		lda #$02	                LDA #BIOS_DEV_SD        ; Default to the SD card
+.3942fb		85 01		sta $0321	                STA BIOS_DEV
+.3942fd		a9 ff		lda #$ff	                LDA #$FF                ; Set the mounted device to a sentinel value
+.3942ff		8f 50 a0 38	sta $38a050	                STA @l DOS_MOUNT_DEV
+.394303		a9 00		lda #$00	                LDA #0
+.394305		a2 00 00	ldx #$0000	                LDX #0
+.394308		9d 20 ad	sta $38ad20,x	fd_zero_loop    STA @w DOS_FILE_DESCS,X
+.39430b		e8		inx		                INX
+.39430c		e0 00 01	cpx #$0100	                CPX #(DOS_FILE_DESCS_END - DOS_FILE_DESCS)
+.39430f		d0 f7		bne $394308	                BNE fd_zero_loop
+.394311		a9 00		lda #$00	                LDA #0
+.394313		a2 00 00	ldx #$0000	                LDX #0
+.394316		9d 00 b0	sta $38b000,x	sect_zero_loop  STA @w DOS_FILE_BUFFS,X
+.394319		e8		inx		                INX
+.39431a		e0 00 10	cpx #$1000	                CPX #(DOS_FILE_BUFFS_END - DOS_FILE_BUFFS)
+.39431d		d0 f7		bne $394316	                BNE sect_zero_loop
+.39431f		c2 20		rep #$20	                REP #$20        ; set A long
+.394321		a9 20 ad	lda #$ad20	                LDA #<>DOS_FILE_DESCS   ; Initialize a pointer to the file descriptors
+.394324		85 20		sta $0340	                STA @b DOS_FD_PTR
+.394326		a9 38 00	lda #$0038	                LDA #`DOS_FILE_DESCS
+.394329		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.39432b		a9 00 b0	lda #$b000	                LDA #<>DOS_FILE_BUFFS   ; Initialize a pointer to the sector buffers
+.39432e		85 28		sta $0348	                STA @b DOS_TEMP
+.394330		a9 38 00	lda #$0038	                LDA #`DOS_FILE_BUFFS
+.394333		85 2a		sta $034a	                STA @b DOS_TEMP+2
+.394335		a2 08 00	ldx #$0008	                LDX #DOS_FD_MAX         ; Set how many file descriptors to update
+.394338		a0 0e 00	ldy #$000e	fd_buff_loop    LDY #FILEDESC.BUFFER    ; Set the file descriptor's buffer pointer
+.39433b		a5 28		lda $0348	                LDA @b DOS_TEMP
+.39433d		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39433f		c8		iny		                INY
+.394340		c8		iny		                INY
+.394341		a5 2a		lda $034a	                LDA @b DOS_TEMP+2
+.394343		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.394345		18		clc		                CLC                     ; Advance the file descriptor pointer to the next file descriptor
+.394346		a5 20		lda $0340	                LDA @b DOS_FD_PTR
+.394348		69 20 00	adc #$0020	                ADC #SIZE(FILEDESC)
+.39434b		85 20		sta $0340	                STA @b DOS_FD_PTR
+.39434d		a5 22		lda $0342	                LDA @b DOS_FD_PTR+2
+.39434f		69 00 00	adc #$0000	                ADC #0
+.394352		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.394354		18		clc		                CLC                     ; Advance the sector buffer pointer to the next buffer
+.394355		a5 28		lda $0348	                LDA @b DOS_TEMP
+.394357		69 00 02	adc #$0200	                ADC #DOS_SECTOR_SIZE
+.39435a		85 28		sta $0348	                STA @b DOS_TEMP
+.39435c		a5 2a		lda $034a	                LDA @b DOS_TEMP+2
+.39435e		69 00 00	adc #$0000	                ADC #0
+.394361		85 2a		sta $034a	                STA @b DOS_TEMP+2
+.394363		ca		dex		                DEX                     ; Count down the descriptors...
+.394364		d0 d2		bne $394338	                BNE fd_buff_loop        ; If not zero, keep setting the buffer pointers
+.394366		28		plp		                PLP
+.394367		2b		pld		                PLD
+.394368		ab		plb		                PLB
+.394369		6b		rtl		                RTL
+.39436a						DOS_MOUNT
+.39436a		8b		phb		                PHB
+.39436b		0b		phd		                PHD
+.39436c		08		php		                PHP
+.39436d		48		pha		                PHA             ; begin setdbr macro
+.39436e		08		php		                PHP
+.39436f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394371		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394373		48		pha		                PHA
+.394374		ab		plb		                PLB
+.394375		28		plp		                PLP
+.394376		68		pla		                PLA             ; end setdbr macro
+.394377		48		pha		                PHA             ; begin setdp macro
+.394378		08		php		                PHP
+.394379		c2 20		rep #$20	                REP #$20        ; set A long
+.39437b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39437e		5b		tcd		                TCD
+.39437f		28		plp		                PLP
+.394380		68		pla		                PLA             ; end setdp macro
+.394381		e2 20		sep #$20	                SEP #$20        ; set A short
+.394383		a5 01		lda $0321	                LDA BIOS_DEV            ; Get the device to moount
+.394385		8f 50 a0 38	sta $38a050	try_mount       STA @l DOS_MOUNT_DEV    ; Save the device we're going to try to mount
+.394389		c9 02		cmp #$02	                CMP #BIOS_DEV_SD        ; Is it the SDC?
+.39438b		f0 1f		beq $3943ac	                BEQ do_sdc_mount        ; Yes: attempt to mount it
+.39438d		c9 06		cmp #$06	                CMP #BIOS_DEV_HD0       ; Is it HD0?
+.39438f		f0 26		beq $3943b7	                BEQ do_ide_mount        ; Yes: attempt to mount the IDE drive
+.394391		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC       ; Is it the FDC?
+.394393		f0 0b		beq $3943a0	                BEQ do_fdc_mount        ; Yes: attempt to mount it
+.394395		a9 04		lda #$04	                LDA #DOS_ERR_NOINIT     ; Otherwise: return a bad device error
+.394397		85 0e		sta $032e	                STA DOS_STATUS
+.394399		a9 80		lda #$80	                LDA #BIOS_ERR_BADDEV
+.39439b		85 00		sta $0320	                STA BIOS_STATUS
+.39439d		82 7c 01	brl $39451c	                BRL ret_failure
+.3943a0		22 cb 65 39	jsl $3965cb	do_fdc_mount    JSL FDC_MOUNT           ; Attempt to mount the floppy disk
+.3943a4		b0 03		bcs $3943a9	                BCS fdc_success
+.3943a6		82 73 01	brl $39451c	                BRL ret_failure
+.3943a9		82 67 01	brl $394513	fdc_success     BRL ret_success
+.3943ac		22 d5 5b 39	jsl $395bd5	do_sdc_mount    JSL SDC_INIT            ; Yes: Initialize access to the SDC
+.3943b0		b0 10		bcs $3943c2	                BCS get_mbr             ; Continue if success
+.3943b2		a9 04		lda #$04	                LDA #DOS_ERR_NOINIT     ; Otherwise: return an error
+.3943b4		82 65 01	brl $39451c	                BRL ret_failure
+.3943b7		22 13 6a 39	jsl $396a13	do_ide_mount    JSL IDE_INIT            ; Yes: Initialize access to the IDE drive
+.3943bb		b0 05		bcs $3943c2	                BCS get_mbr             ; Continue if success
+.3943bd		a9 04		lda #$04	                LDA #DOS_ERR_NOINIT     ; Otherwise: return an error
+.3943bf		82 5a 01	brl $39451c	                BRL ret_failure
+.3943c2						get_mbr
+.3943c2		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3943c4		64 02		stz $0322	                STZ BIOS_LBA            ; Get the MBR
+.3943c6		64 04		stz $0324	                STZ BIOS_LBA+2
+.3943c8		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR       ; Into DOS_SECTOR
+.3943cb		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.3943cd		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
+.3943d0		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.3943d2		22 44 10 00	jsl $001044	                JSL GETBLOCK            ; Try to read the MBR
+.3943d6		b0 07		bcs $3943df	                BCS chk_signature       ; If success, check the signature bytes
+.3943d8		e2 20		sep #$20	                SEP #$20        ; set A short
+.3943da		a9 01		lda #$01	                LDA #DOS_ERR_READ       ; Otherwise: report we couldn't read the first sector
+.3943dc		82 3d 01	brl $39451c	                BRL ret_failure
+.3943df						chk_signature
+.3943df		e2 20		sep #$20	                SEP #$20        ; set A short
+.3943e1		ad fe a4	lda $38a4fe	                LDA DOS_SECTOR+MBR_SIGNATURE
+.3943e4		c9 55		cmp #$55	                CMP #$55                ; Is first byte of signature $55?
+.3943e6		d0 07		bne $3943ef	                BNE not_mbr             ; No: signal we could find the MBR
+.3943e8		ad ff a4	lda $38a4ff	                LDA DOS_SECTOR+MBR_SIGNATURE+1
+.3943eb		c9 aa		cmp #$aa	                CMP #$AA                ; Is second byte of signature $AA?
+.3943ed		f0 05		beq $3943f4	                BEQ chk_part_type       ; Yes: we have an MBR
+.3943ef		a9 02		lda #$02	not_mbr         LDA #DOS_ERR_NOTMBR     ; Return that we didn't find the MBR
+.3943f1		82 28 01	brl $39451c	                BRL ret_failure
+.3943f4		ad c2 a4	lda $38a4c2	chk_part_type   LDA DOS_SECTOR+PART0_OFF+PART_TYPE_OFF
+.3943f7		c9 0c		cmp #$0c	                CMP #PART_TYPE_FAT32_LBA
+.3943f9		f0 05		beq $394400	                BEQ get_LBA             ; Is FAT32 with LBA?
+.3943fb		a9 03		lda #$03	                LDA #DOS_ERR_NOFAT32    ; No: return No FAT32 found error
+.3943fd		82 1c 01	brl $39451c	                BRL ret_failure
+.394400		8d 01 a0	sta $38a001	get_LBA         STA FILE_SYSTEM         ; Save the file system of the partition
+.394403		c2 20		rep #$20	                REP #$20        ; set A long
+.394405		ad c6 a4	lda $38a4c6	                LDA DOS_SECTOR+PART0_OFF+PART_LBA_OFF
+.394408		8d 04 a0	sta $38a004	                STA FIRSTSECTOR
+.39440b		ad c8 a4	lda $38a4c8	                LDA DOS_SECTOR+PART0_OFF+PART_LBA_OFF+2
+.39440e		8d 06 a0	sta $38a006	                STA FIRSTSECTOR+2
+.394411		ad cb a4	lda $38a4cb	                LDA DOS_SECTOR+PART0_OFF+PART_SECT_COUNT_OFF
+.394414		8d 08 a0	sta $38a008	                STA SECTORCOUNT
+.394417		ad cd a4	lda $38a4cd	                LDA DOS_SECTOR+PART0_OFF+PART_SECT_COUNT_OFF+2
+.39441a		8d 0a a0	sta $38a00a	                STA SECTORCOUNT+2
+.39441d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39441f		a5 01		lda $0321	                LDA BIOS_DEV            ; Save the device number
+.394421		8d 00 a0	sta $38a000	                STA DEVICE
+.394424		a9 00		lda #$00	                LDA #0
+.394426		8d 02 a0	sta $38a002	                STA PARTITION           ; For the moment, we only support the first partition
+.394429		c2 20		rep #$20	                REP #$20        ; set A long
+.39442b		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR
+.39442e		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394430		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
+.394433		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394435		ad 04 a0	lda $38a004	                LDA FIRSTSECTOR
+.394438		85 02		sta $0322	                STA BIOS_LBA
+.39443a		ad 06 a0	lda $38a006	                LDA FIRSTSECTOR+2
+.39443d		85 04		sta $0324	                STA BIOS_LBA+2
+.39443f		22 44 10 00	jsl $001044	                JSL GETBLOCK            ; Attempt to load the volume ID
+.394443		b0 1c		bcs $394461	                BCS get_first_sec       ; Got it? Start parsing it
+.394445		e2 20		sep #$20	                SEP #$20        ; set A short
+.394447		a9 05		lda #$05	                LDA #DOS_ERR_VOLID      ; Otherwise: return an error
+.394449		82 d0 00	brl $39451c	                BRL ret_failure
+.39444c						chk_bpb_sig
+.39444c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39444e		ad fe a4	lda $38a4fe	                LDA DOS_SECTOR+BPB_SIGNATURE
+.394451		c9 55		cmp #$55	                CMP #$55                ; Is first byte of signature $55?
+.394453		d0 07		bne $39445c	                BNE not_bpb             ; No: signal we could find the volume ID
+.394455		ad ff a4	lda $38a4ff	                LDA DOS_SECTOR+BPB_SIGNATURE+1
+.394458		c9 aa		cmp #$aa	                CMP #$AA                ; Is second byte of signature $AA?
+.39445a		f0 05		beq $394461	                BEQ get_first_sec       ; Yes: we have an volume ID
+.39445c		a9 05		lda #$05	not_bpb         LDA #DOS_ERR_VOLID      ; Return that we didn't find the Volume ID (BPB)
+.39445e		82 bb 00	brl $39451c	                BRL ret_failure
+.394461						get_first_sec
+.394461		c2 20		rep #$20	                REP #$20        ; set A long
+.394463		ad 2c a3	lda $38a32c	                LDA DOS_SECTOR+BPB_ROOTCLUS_OFF
+.394466		8d 20 a0	sta $38a020	                STA ROOT_DIR_FIRST_CLUSTER
+.394469		ad 2e a3	lda $38a32e	                LDA DOS_SECTOR+BPB_ROOTCLUS_OFF+2
+.39446c		8d 22 a0	sta $38a022	                STA ROOT_DIR_FIRST_CLUSTER+2
+.39446f		ad 0e a3	lda $38a30e	                LDA DOS_SECTOR+BPB_RSRVCLUS_OFF
+.394472		8d 0c a0	sta $38a00c	                STA NUM_RSRV_SEC
+.394475		18		clc		                CLC                     ; fat_begin_lba := FirstSector + Number_of_Reserved_Sectors
+.394476		ad 04 a0	lda $38a004	                LDA FIRSTSECTOR
+.394479		6d 0c a0	adc $38a00c	                ADC NUM_RSRV_SEC
+.39447c		8d 14 a0	sta $38a014	                STA FAT_BEGIN_LBA
+.39447f		ad 06 a0	lda $38a006	                LDA FIRSTSECTOR+2
+.394482		69 00 00	adc #$0000	                ADC #0
+.394485		8d 16 a0	sta $38a016	                STA FAT_BEGIN_LBA+2
+.394488		e2 20		sep #$20	                SEP #$20        ; set A short
+.39448a		a2 00 00	ldx #$0000	                LDX #0
+.39448d		bf 24 a3 38	lda $38a324,x	cpy_secperfat   LDA @l DOS_SECTOR+BPB_SECPERFAT_OFF,X
+.394491		9f 10 a0 38	sta $38a010,x	                STA @l SEC_PER_FAT,X
+.394495		e8		inx		                INX
+.394496		e0 04 00	cpx #$0004	                CPX #4
+.394499		d0 f2		bne $39448d	                BNE cpy_secperfat
+.39449b		ad 10 a0	lda $38a010	                LDA SEC_PER_FAT
+.39449e		0a		asl a		                ASL A
+.39449f		8d 1c a0	sta $38a01c	                STA CLUSTER_BEGIN_LBA
+.3944a2		ad 11 a0	lda $38a011	                LDA SEC_PER_FAT+1
+.3944a5		2a		rol a		                ROL A
+.3944a6		8d 1d a0	sta $38a01d	                STA CLUSTER_BEGIN_LBA+1
+.3944a9		ad 12 a0	lda $38a012	                LDA SEC_PER_FAT+2
+.3944ac		2a		rol a		                ROL A
+.3944ad		8d 1e a0	sta $38a01e	                STA CLUSTER_BEGIN_LBA+2
+.3944b0		ad 13 a0	lda $38a013	                LDA SEC_PER_FAT+3
+.3944b3		2a		rol a		                ROL A
+.3944b4		8d 1f a0	sta $38a01f	                STA CLUSTER_BEGIN_LBA+3
+.3944b7		18		clc		                CLC
+.3944b8		ad 1c a0	lda $38a01c	                LDA CLUSTER_BEGIN_LBA
+.3944bb		6d 14 a0	adc $38a014	                ADC FAT_BEGIN_LBA
+.3944be		8d 1c a0	sta $38a01c	                STA CLUSTER_BEGIN_LBA
+.3944c1		ad 1d a0	lda $38a01d	                LDA CLUSTER_BEGIN_LBA+1
+.3944c4		6d 15 a0	adc $38a015	                ADC FAT_BEGIN_LBA+1
+.3944c7		8d 1d a0	sta $38a01d	                STA CLUSTER_BEGIN_LBA+1
+.3944ca		ad 1e a0	lda $38a01e	                LDA CLUSTER_BEGIN_LBA+2
+.3944cd		6d 16 a0	adc $38a016	                ADC FAT_BEGIN_LBA+2
+.3944d0		8d 1e a0	sta $38a01e	                STA CLUSTER_BEGIN_LBA+2
+.3944d3		ad 1f a0	lda $38a01f	                LDA CLUSTER_BEGIN_LBA+3
+.3944d6		6d 17 a0	adc $38a017	                ADC FAT_BEGIN_LBA+3
+.3944d9		8d 1f a0	sta $38a01f	                STA CLUSTER_BEGIN_LBA+3
+.3944dc		e2 20		sep #$20	                SEP #$20        ; set A short
+.3944de		ad 0d a3	lda $38a30d	                LDA DOS_SECTOR+BPB_SECPERCLUS_OFF
+.3944e1		8d 03 a0	sta $38a003	                STA SECTORS_PER_CLUSTER
+.3944e4		18		clc		                CLC
+.3944e5		ad 14 a0	lda $38a014	                LDA FAT_BEGIN_LBA                       ; Compute the address of the first sector of
+.3944e8		6d 10 a0	adc $38a010	                ADC SEC_PER_FAT                         ; the second copy of the FAT
+.3944eb		8d 18 a0	sta $38a018	                STA FAT2_BEGIN_LBA
+.3944ee		ad 15 a0	lda $38a015	                LDA FAT_BEGIN_LBA+1
+.3944f1		6d 11 a0	adc $38a011	                ADC SEC_PER_FAT+1
+.3944f4		8d 19 a0	sta $38a019	                STA FAT2_BEGIN_LBA+1
+.3944f7		ad 16 a0	lda $38a016	                LDA FAT_BEGIN_LBA+2
+.3944fa		6d 12 a0	adc $38a012	                ADC SEC_PER_FAT+2
+.3944fd		8d 1a a0	sta $38a01a	                STA FAT2_BEGIN_LBA+2
+.394500		ad 17 a0	lda $38a017	                LDA FAT_BEGIN_LBA+3
+.394503		6d 13 a0	adc $38a013	                ADC SEC_PER_FAT+3
+.394506		8d 1b a0	sta $38a01b	                STA FAT2_BEGIN_LBA+3
+.394509		a9 00		lda #$00	                LDA #<DOS_SECTOR_SIZE                   ; Default to one sector's worth of bytes
+.39450b		8d 0e a0	sta $38a00e	                STA CLUSTER_SIZE
+.39450e		a9 02		lda #$02	                LDA #>DOS_SECTOR_SIZE
+.394510		8d 0f a0	sta $38a00f	                STA CLUSTER_SIZE+1
+.394513						ret_success
+.394513		e2 20		sep #$20	                SEP #$20        ; set A short
+.394515		64 0e		stz $032e	                STZ DOS_STATUS          ; Set status code to 0
+.394517		28		plp		                PLP
+.394518		2b		pld		                PLD
+.394519		ab		plb		                PLB
+.39451a		38		sec		                SEC
+.39451b		6b		rtl		                RTL
+.39451c						ret_failure
+.39451c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39451e		85 0e		sta $032e	                STA DOS_STATUS          ; Save the status code
+.394520		28		plp		                PLP
+.394521		2b		pld		                PLD
+.394522		ab		plb		                PLB
+.394523		18		clc		                CLC
+.394524		6b		rtl		                RTL
+.394525						DOS_TESTBOOT
+.394525		8b		phb		                PHB
+.394526		0b		phd		                PHD
+.394527		da		phx		                PHX
+.394528		08		php		                PHP
+.394529		48		pha		                PHA             ; begin setdbr macro
+.39452a		08		php		                PHP
+.39452b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39452d		a9 00		lda #$00	                LDA #0
+.39452f		48		pha		                PHA
+.394530		ab		plb		                PLB
+.394531		28		plp		                PLP
+.394532		68		pla		                PLA             ; end setdbr macro
+.394533		48		pha		                PHA             ; begin setdp macro
+.394534		08		php		                PHP
+.394535		c2 20		rep #$20	                REP #$20        ; set A long
+.394537		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39453a		5b		tcd		                TCD
+.39453b		28		plp		                PLP
+.39453c		68		pla		                PLA             ; end setdp macro
+.39453d		c2 10		rep #$10	                REP #$10        ; set X long
+.39453f						chk_dev
+.39453f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394541		a5 01		lda $0321	                LDA @b BIOS_DEV             ; Look at the device #
+.394543		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC           ; Is it the floppy drive?
+.394545		f0 24		beq $39456b	                BEQ chk_vbr_brl             ; Yes: check if BRL is in the right place in the VBR
+.394547		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394549		a9 00 00	lda #$0000	                LDA #0                      ; Point to the MBR
+.39454c		85 02		sta $0322	                STA @b BIOS_LBA
+.39454e		85 04		sta $0324	                STA @b BIOS_LBA+2
+.394550		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR           ; And the buffer
+.394553		85 06		sta $0326	                STA @b BIOS_BUFF_PTR
+.394555		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
+.394558		85 08		sta $0328	                STA @b BIOS_BUFF_PTR+2
+.39455a		22 44 10 00	jsl $001044	                JSL GETBLOCK                ; Try to load the MBR
+.39455e		b0 03		bcs $394563	                BCS chk_mbr_brl
+.394560		82 47 00	brl $3945aa	                BRL done                    ; If failed... just return
+.394563						chk_mbr_brl
+.394563		e2 20		sep #$20	                SEP #$20        ; set A short
+.394565		af 00 a3 38	lda $38a300	                LDA @l DOS_SECTOR           ; Check the first byte of the MBR
+.394569		80 04		bra $39456f	                BRA chk_brl
+.39456b		af 3e a3 38	lda $38a33e	chk_vbr_brl     LDA @l DOS_SECTOR+FDC_BOOT_START
+.39456f		c9 80		cmp #$80	chk_brl         CMP #$80                    ; Is the first byte a BRL/BRA instruction?
+.394571		f0 06		beq $394579	                BEQ chk_magic               ; Yes: check for the magic text
+.394573		c9 82		cmp #$82	                CMP #$82
+.394575		f0 02		beq $394579	                BEQ chk_magic
+.394577		80 31		bra $3945aa	                BRA done                    ; No: just return
+.394579		a2 00 00	ldx #$0000	chk_magic       LDX #0
+.39457c		bf 03 a3 38	lda $38a303,x	magic_loop      LDA @l DOS_SECTOR+3,X       ; Check the "vendor" byte
+.394580		df af 45 39	cmp $3945af,x	                CMP DOS_BOOT_MAGIC,X        ; Compare it against our boot magic code
+.394584		d0 24		bne $3945aa	                BNE done                    ; If it's not equal, just return
+.394586		e8		inx		                INX                         ; Otherwise, check the next one
+.394587		e0 08 00	cpx #$0008	                CPX #8
+.39458a		d0 f0		bne $39457c	                BNE magic_loop              ; Until we've checked all 8 bytes
+.39458c		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39458e		a9 00 02	lda #$0200	                LDA #DOS_SECTOR_SIZE
+.394591		a2 00 a5	ldx #$a500	                LDX #<>(DOS_SECTOR+DOS_SECTOR_SIZE)
+.394594		a0 00 ab	ldy #$ab00	                LDY #<>(DOS_BOOT_SECTOR+DOS_SECTOR_SIZE)
+.394597		44 38 38	mvp $38,$38	                MVP #`DOS_SECTOR, #`DOS_BOOT_SECTOR
+.39459a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39459c		a5 01		lda $0321	                LDA @b BIOS_DEV             ; Check the device
+.39459e		c9 00		cmp #$00	                CMP #BIOS_DEV_FDC           ; Is it the FDC?
+.3945a0		f0 04		beq $3945a6	                BEQ jmp_fdc_start           ; Yes: jump to the start of the VBR code
+.3945a2		5c 00 a9 38	jmp $38a900	                JML DOS_BOOT_SECTOR         ; No: it's an MBR, start at the first byte
+.3945a6		5c 3e a9 38	jmp $38a93e	jmp_fdc_start   JML DOS_BOOT_SECTOR+FDC_BOOT_START
+.3945aa		28		plp		done            PLP
+.3945ab		2b		pld		                PLD
+.3945ac		ab		plb		                PLB
+.3945ad		fa		plx		                PLX
+.3945ae		6b		rtl		                RTL
+>3945af		43 32 35 36 44 4f 53 20		DOS_BOOT_MAGIC  .text "C256DOS "
+.3945b7						DOS_CALC_LBA
+.3945b7		8b		phb		                PHB
+.3945b8		0b		phd		                PHD
+.3945b9		08		php		                PHP
+.3945ba		48		pha		                PHA             ; begin setdbr macro
+.3945bb		08		php		                PHP
+.3945bc		e2 20		sep #$20	                SEP #$20        ; set A short
+.3945be		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3945c0		48		pha		                PHA
+.3945c1		ab		plb		                PLB
+.3945c2		28		plp		                PLP
+.3945c3		68		pla		                PLA             ; end setdbr macro
+.3945c4		48		pha		                PHA             ; begin setdp macro
+.3945c5		08		php		                PHP
+.3945c6		c2 20		rep #$20	                REP #$20        ; set A long
+.3945c8		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3945cb		5b		tcd		                TCD
+.3945cc		28		plp		                PLP
+.3945cd		68		pla		                PLA             ; end setdp macro
+.3945ce		c2 20		rep #$20	                REP #$20        ; set A long
+.3945d0		38		sec		                SEC
+.3945d1		a5 10		lda $0330	                LDA DOS_CLUS_ID                     ; cluster - 2
+.3945d3		e9 02 00	sbc #$0002	                SBC #2
+.3945d6		85 28		sta $0348	                STA DOS_TEMP
+.3945d8		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3945da		e9 00 00	sbc #$0000	                SBC #0
+.3945dd		85 2a		sta $034a	                STA DOS_TEMP+2
+.3945df		e2 10		sep #$10	                SEP #$10        ; set X short
+.3945e1		ae 03 a0	ldx $38a003	                LDX SECTORS_PER_CLUSTER
+.3945e4		e0 01		cpx #$01	mult_loop       CPX #1
+.3945e6		f0 07		beq $3945ef	                BEQ add_offset
+.3945e8		06 28		asl $0348	                ASL DOS_TEMP
+.3945ea		26 28		rol $0348	                ROL DOS_TEMP
+.3945ec		ca		dex		                DEX
+.3945ed		80 f5		bra $3945e4	                BRA mult_loop
+.3945ef		18		clc		add_offset      CLC
+.3945f0		a5 28		lda $0348	                LDA DOS_TEMP                        ; cluster_being_lba + (cluster - 2) * SECTORS_PER_CLUSTER
+.3945f2		6d 1c a0	adc $38a01c	                ADC CLUSTER_BEGIN_LBA
+.3945f5		85 02		sta $0322	                STA BIOS_LBA
+.3945f7		a5 2a		lda $034a	                LDA DOS_TEMP+2
+.3945f9		6d 1e a0	adc $38a01e	                ADC CLUSTER_BEGIN_LBA+2
+.3945fc		85 04		sta $0324	                STA BIOS_LBA+2
+.3945fe		28		plp		                PLP
+.3945ff		2b		pld		                PLD
+.394600		ab		plb		                PLB
+.394601		6b		rtl		                RTL
+.394602						DOS_GETCLUSTER
+.394602		8b		phb		                PHB
+.394603		0b		phd		                PHD
+.394604		08		php		                PHP
+.394605		48		pha		                PHA             ; begin setdbr macro
+.394606		08		php		                PHP
+.394607		e2 20		sep #$20	                SEP #$20        ; set A short
+.394609		a9 00		lda #$00	                LDA #0
+.39460b		48		pha		                PHA
+.39460c		ab		plb		                PLB
+.39460d		28		plp		                PLP
+.39460e		68		pla		                PLA             ; end setdbr macro
+.39460f		48		pha		                PHA             ; begin setdp macro
+.394610		08		php		                PHP
+.394611		c2 20		rep #$20	                REP #$20        ; set A long
+.394613		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394616		5b		tcd		                TCD
+.394617		28		plp		                PLP
+.394618		68		pla		                PLA             ; end setdp macro
+.394619		c2 20		rep #$20	                REP #$20        ; set A long
+.39461b		a5 1c		lda $033c	                LDA DOS_BUFF_PTR                    ; Set the BIOS BUFFER
+.39461d		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.39461f		a5 1e		lda $033e	                LDA DOS_BUFF_PTR+2
+.394621		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394623		22 b7 45 39	jsl $3945b7	                JSL DOS_CALC_LBA                    ; Convert the cluster # to the first sector's LBA
+.394627		22 44 10 00	jsl $001044	                JSL GETBLOCK                        ; Get the first block of the cluster
+.39462b		90 09		bcc $394636	                BCC ret_failure
+.39462d						ret_success
+.39462d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39462f		64 0e		stz $032e	                STZ DOS_STATUS
+.394631		28		plp		                PLP
+.394632		2b		pld		                PLD
+.394633		ab		plb		                PLB
+.394634		38		sec		                SEC
+.394635		6b		rtl		                RTL
+.394636						ret_failure
+.394636		e2 20		sep #$20	                SEP #$20        ; set A short
+.394638		85 0e		sta $032e	                STA DOS_STATUS
+.39463a		28		plp		                PLP
+.39463b		2b		pld		                PLD
+.39463c		ab		plb		                PLB
+.39463d		18		clc		                CLC
+.39463e		6b		rtl		                RTL
+.39463f						DOS_PUTCLUSTER
+.39463f		8b		phb		                PHB
+.394640		0b		phd		                PHD
+.394641		08		php		                PHP
+.394642		48		pha		                PHA             ; begin setdbr macro
+.394643		08		php		                PHP
+.394644		e2 20		sep #$20	                SEP #$20        ; set A short
+.394646		a9 00		lda #$00	                LDA #0
+.394648		48		pha		                PHA
+.394649		ab		plb		                PLB
+.39464a		28		plp		                PLP
+.39464b		68		pla		                PLA             ; end setdbr macro
+.39464c		48		pha		                PHA             ; begin setdp macro
+.39464d		08		php		                PHP
+.39464e		c2 20		rep #$20	                REP #$20        ; set A long
+.394650		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394653		5b		tcd		                TCD
+.394654		28		plp		                PLP
+.394655		68		pla		                PLA             ; end setdp macro
+.394656		c2 20		rep #$20	                REP #$20        ; set A long
+.394658		a5 1c		lda $033c	                LDA DOS_BUFF_PTR                    ; Set the BIOS BUFFER
+.39465a		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.39465c		a5 1e		lda $033e	                LDA DOS_BUFF_PTR+2
+.39465e		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394660		22 b7 45 39	jsl $3945b7	                JSL DOS_CALC_LBA                    ; Convert the cluster # to the first sector's LBA
+.394664		22 24 10 00	jsl $001024	                JSL PUTBLOCK                        ; PUT the first block of the cluster
+.394668		90 09		bcc $394673	                BCC ret_failure
+.39466a						ret_success
+.39466a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39466c		64 0e		stz $032e	                STZ DOS_STATUS
+.39466e		28		plp		                PLP
+.39466f		2b		pld		                PLD
+.394670		ab		plb		                PLB
+.394671		38		sec		                SEC
+.394672		6b		rtl		                RTL
+.394673						ret_failure
+.394673		e2 20		sep #$20	                SEP #$20        ; set A short
+.394675		85 0e		sta $032e	                STA DOS_STATUS
+.394677		28		plp		                PLP
+.394678		2b		pld		                PLD
+.394679		ab		plb		                PLB
+.39467a		18		clc		                CLC
+.39467b		6b		rtl		                RTL
+>39467c		40 46 00			DOS_FDC_NAME    .null "@F"
+.39467f						DOS_FDC_DESC
+>39467f		7c 46 39 00			DEVNAME         .dword DOS_FDC_NAME            ; A pointer to the ASCIIZ name of the device
+>394683		00				DEVNUMBER       .byte BIOS_DEV_FDC           ; The BIOS_DEV number for the device
+>394684		00 00 00 00			NEXT            .dword 0            ; A pointer to the next device descriptor
+>394688		40 53 00			DOS_SDC_NAME    .null "@S"
+.39468b						DOS_SDC_DESC
+>39468b		88 46 39 00			DEVNAME         .dword DOS_SDC_NAME            ; A pointer to the ASCIIZ name of the device
+>39468f		02				DEVNUMBER       .byte BIOS_DEV_SD           ; The BIOS_DEV number for the device
+>394690		7f 46 39 00			NEXT            .dword DOS_FDC_DESC            ; A pointer to the next device descriptor
+>394694		40 48 00			DOS_HDC_NAME    .null "@H"
+.394697						DOS_HD_DESC
+>394697		94 46 39 00			DEVNAME         .dword DOS_HDC_NAME            ; A pointer to the ASCIIZ name of the device
+>39469b		06				DEVNUMBER       .byte BIOS_DEV_HD0           ; The BIOS_DEV number for the device
+>39469c		8b 46 39 00			NEXT            .dword DOS_SDC_DESC            ; A pointer to the next device descriptor
+.3946a0						DOS_PARSE_DEV
+.3946a0		8b		phb		                PHB
+.3946a1		0b		phd		                PHD
+.3946a2		08		php		                PHP
+.3946a3		48		pha		                PHA             ; begin setdbr macro
+.3946a4		08		php		                PHP
+.3946a5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3946a7		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3946a9		48		pha		                PHA
+.3946aa		ab		plb		                PLB
+.3946ab		28		plp		                PLP
+.3946ac		68		pla		                PLA             ; end setdbr macro
+.3946ad		48		pha		                PHA             ; begin setdp macro
+.3946ae		08		php		                PHP
+.3946af		c2 20		rep #$20	                REP #$20        ; set A long
+.3946b1		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3946b4		5b		tcd		                TCD
+.3946b5		28		plp		                PLP
+.3946b6		68		pla		                PLA             ; end setdp macro
+.3946b7		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3946b9		af 4a a0 38	lda $38a04a	                LDA @l DOS_DEV_NAMES        ; Point to the first device name to check
+.3946bd		85 28		sta $0348	                STA DOS_TEMP
+.3946bf		af 4c a0 38	lda $38a04c	                LDA @l DOS_DEV_NAMES+2
+.3946c3		85 2a		sta $034a	                STA DOS_TEMP+2
+.3946c5		a9 00 04	lda #$0400	                LDA #<>DOS_PATH_BUFF        ; Make DOS_STR2_PTR point to the path to check
+.3946c8		85 48		sta $0368	                STA DOS_STR2_PTR
+.3946ca		a9 00 00	lda #$0000	                LDA #`DOS_PATH_BUFF
+.3946cd		85 4a		sta $036a	                STA DOS_STR2_PTR+2
+.3946cf		a0 00 00	ldy #$0000	dev_loop        LDY #DEVICE_DESC.DEVNAME    ; Get the name of the current device into DOS_STR1_PTR
+.3946d2		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
+.3946d4		85 44		sta $0364	                STA DOS_STR1_PTR
+.3946d6		c8		iny		                INY
+.3946d7		c8		iny		                INY
+.3946d8		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
+.3946da		85 46		sta $0366	                STA DOS_STR1_PTR+2
+.3946dc		e2 20		sep #$20	                SEP #$20        ; set A short
+.3946de		a0 00 00	ldy #$0000	                LDY #0
+.3946e1		b7 44		lda [$0364],y	cmp_loop        LDA [DOS_STR1_PTR],Y        ; Get the Yth character of the device name
+.3946e3		f0 24		beq $394709	                BEQ found                   ; If it's NULL, we found a match
+.3946e5		d7 48		cmp [$0368],y	                CMP [DOS_STR2_PTR],Y        ; Compare it to the Yth character of the path
+.3946e7		d0 03		bne $3946ec	                BNE next_device             ; If no match, try to load the next device
+.3946e9		c8		iny		                INY                         ; Go to the next character
+.3946ea		80 f5		bra $3946e1	                BRA cmp_loop
+.3946ec						next_device
+.3946ec		c2 20		rep #$20	                REP #$20        ; set A long
+.3946ee		a0 05 00	ldy #$0005	                LDY #DEVICE_DESC.NEXT       ; DOS_TEMP := DOS_TEMP->NEXT
+.3946f1		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
+.3946f3		48		pha		                PHA
+.3946f4		c8		iny		                INY
+.3946f5		c8		iny		                INY
+.3946f6		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
+.3946f8		85 2a		sta $034a	                STA DOS_TEMP+2
+.3946fa		68		pla		                PLA
+.3946fb		85 28		sta $0348	                STA DOS_TEMP
+.3946fd		a5 28		lda $0348	                LDA DOS_TEMP                ; Is DOS_TEMP = NULL?
+.3946ff		d0 ce		bne $3946cf	                BNE dev_loop                ; No: check this device
+.394701		a5 2a		lda $034a	                LDA DOS_TEMP+2
+.394703		d0 ca		bne $3946cf	                BNE dev_loop
+.394705		28		plp		done            PLP                         ; Otherwise, return having not found a match
+.394706		2b		pld		                PLD
+.394707		ab		plb		                PLB
+.394708		6b		rtl		                RTL
+.394709		22 1a 47 39	jsl $39471a	found           JSL DOS_ADJUSTPATH          ; Remove the device name from the buffer
+.39470d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39470f		a0 04 00	ldy #$0004	                LDY #DEVICE_DESC.DEVNUMBER  ; Set the BIOS device number from the found device
+.394712		b7 28		lda [$0348],y	                LDA [DOS_TEMP],Y
+.394714		8f 21 03 00	sta $000321	                STA @l BIOS_DEV
+.394718		80 eb		bra $394705	                BRA done
+.39471a						DOS_ADJUSTPATH
+.39471a		da		phx		                PHX
+.39471b		5a		phy		                PHY
+.39471c		8b		phb		                PHB
+.39471d		0b		phd		                PHD
+.39471e		08		php		                PHP
+.39471f		48		pha		                PHA             ; begin setdbr macro
+.394720		08		php		                PHP
+.394721		e2 20		sep #$20	                SEP #$20        ; set A short
+.394723		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394725		48		pha		                PHA
+.394726		ab		plb		                PLB
+.394727		28		plp		                PLP
+.394728		68		pla		                PLA             ; end setdbr macro
+.394729		48		pha		                PHA             ; begin setdp macro
+.39472a		08		php		                PHP
+.39472b		c2 20		rep #$20	                REP #$20        ; set A long
+.39472d		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394730		5b		tcd		                TCD
+.394731		28		plp		                PLP
+.394732		68		pla		                PLA             ; end setdp macro
+.394733		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394735		84 4b		sty $036b	                STY DOS_SCRATCH                 ; Save the index to later compute the size
+.394737		98		tya		                TYA                             ; Compute the address of the first source byte
+.394738		18		clc		                CLC
+.394739		69 00 04	adc #$0400	                ADC #<>DOS_PATH_BUFF
+.39473c		aa		tax		                TAX
+.39473d		a9 00 04	lda #$0400	                LDA #<>DOS_PATH_BUFF            ; Compute the destination address for the source byte
+.394740		a8		tay		                TAY
+.394741		38		sec		                SEC                             ; Compute the number of bytes to copy
+.394742		a9 00 01	lda #$0100	                LDA #256
+.394745		e5 4b		sbc $036b	                SBC DOS_SCRATCH
+.394747		54 00 00	mvn $00,$00	                MVN #`DOS_PATH_BUFF, #`DOS_PATH_BUFF
+.39474a		28		plp		                PLP
+.39474b		2b		pld		                PLD
+.39474c		ab		plb		                PLB
+.39474d		7a		ply		                PLY
+.39474e		fa		plx		                PLX
+.39474f		6b		rtl		                RTL
+.394750						DOS_PARSE_PATH
+.394750		8b		phb		                PHB
+.394751		0b		phd		                PHD
+.394752		08		php		                PHP
+.394753		48		pha		                PHA             ; begin setdbr macro
+.394754		08		php		                PHP
+.394755		e2 20		sep #$20	                SEP #$20        ; set A short
+.394757		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394759		48		pha		                PHA
+.39475a		ab		plb		                PLB
+.39475b		28		plp		                PLP
+.39475c		68		pla		                PLA             ; end setdbr macro
+.39475d		48		pha		                PHA             ; begin setdp macro
+.39475e		08		php		                PHP
+.39475f		c2 20		rep #$20	                REP #$20        ; set A long
+.394761		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394764		5b		tcd		                TCD
+.394765		28		plp		                PLP
+.394766		68		pla		                PLA             ; end setdp macro
+.394767		c2 10		rep #$10	                REP #$10        ; set X long
+.394769		e2 20		sep #$20	                SEP #$20        ; set A short
+.39476b		a2 00 00	ldx #$0000	                LDX #0
+.39476e		b5 e0		lda $0400,x	upcase_loop     LDA DOS_PATH_BUFF,X     ; Get the character
+.394770		f0 1b		beq $39478d	                BEQ parse_dev           ; If it's NULL, the path is upper case, attempt to parse the device
+.394772		c9 20		cmp #$20	                CMP #' '                ; Is a control character?
+.394774		b0 05		bcs $39477b	                BGE check_case          ; No: check the case
+.394776		a9 07		lda #$07	                LDA #DOS_ERR_BADPATH    ; Yes: return a bad path error
+.394778		82 64 00	brl $3947df	                BRL ret_failure
+.39477b		c9 61		cmp #$61	check_case      CMP #'a'                ; Is the character lower case?
+.39477d		90 08		bcc $394787	                BLT next_char
+.39477f		c9 7b		cmp #$7b	                CMP #'z'+1
+.394781		b0 04		bcs $394787	                BGE next_char
+.394783		29 5f		and #$5f	                AND #%01011111          ; Yes: Convert to uppercase
+.394785		95 e0		sta $0400,x	                STA DOS_PATH_BUFF,X
+.394787		e8		inx		next_char       INX                     ; Move to the next character
+.394788		e0 00 01	cpx #$0100	                CPX #$100
+.39478b		d0 e1		bne $39476e	                BNE upcase_loop
+.39478d		22 a0 46 39	jsl $3946a0	parse_dev       JSL DOS_PARSE_DEV       ; Parse and extract a device specifier ":xxx:"
+.394791		a5 e0		lda $0400	                LDA DOS_PATH_BUFF       ; Check the first character of the path
+.394793		c9 3a		cmp #$3a	                CMP #':'
+.394795		d0 07		bne $39479e	                BNE clr_name            ; If not colon, treat it as a file name
+.394797		a0 01 00	ldy #$0001	                LDY #1                  ; Otherwise...
+.39479a		22 1a 47 39	jsl $39471a	                JSL DOS_ADJUSTPATH      ; For now, just remove the leading ":"
+.39479e		a0 00 00	ldy #$0000	clr_name        LDY #0                  ; Set the short name to blanks
+.3947a1		a9 20		lda #$20	                LDA #' '
+.3947a3		99 3a a0	sta $38a03a,y	clr_loop        STA DOS_SHORT_NAME,Y
+.3947a6		c8		iny		                INY
+.3947a7		c0 0b 00	cpy #$000b	                CPY #11
+.3947aa		d0 f7		bne $3947a3	                BNE clr_loop
+.3947ac		a2 00 00	ldx #$0000	                LDX #0
+.3947af		a0 00 00	ldy #$0000	                LDY #0
+.3947b2		b5 e0		lda $0400,x	cpy_name_loop   LDA DOS_PATH_BUFF,X     ; Get the character of the name
+.3947b4		f0 20		beq $3947d6	                BEQ ret_success         ; If NULL: we've finished parsing the path
+.3947b6		c9 2e		cmp #$2e	                CMP #'.'                ; If it's a dot, we've finished the name part
+.3947b8		f0 0a		beq $3947c4	                BEQ cpy_ext             ; And move to the extension
+.3947ba		99 3a a0	sta $38a03a,y	                STA DOS_SHORT_NAME,Y    ; Otherwise, store it to the name portion
+.3947bd		e8		inx		                INX
+.3947be		c8		iny		                INY                     ; Move to the next character
+.3947bf		c0 08 00	cpy #$0008	                CPY #8                  ; Have we processed 8?
+.3947c2		d0 ee		bne $3947b2	                BNE cpy_name_loop       ; No: process this one
+.3947c4		e8		inx		cpy_ext         INX                     ; Skip the dot
+.3947c5		a0 08 00	ldy #$0008	                LDY #8
+.3947c8		b5 e0		lda $0400,x	cpy_ext_loop    LDA DOS_PATH_BUFF,X     ; Get the character of the extension
+.3947ca		f0 0a		beq $3947d6	                BEQ ret_success         ; If it's NULL, we've finished
+.3947cc		99 3a a0	sta $38a03a,y	                STA DOS_SHORT_NAME,Y    ; Otherwise, copy it to the short name
+.3947cf		e8		inx		                INX
+.3947d0		c8		iny		                INY                     ; Move to the next character
+.3947d1		c0 0b 00	cpy #$000b	                CPY #11                 ; Have we processed the three ext characters?
+.3947d4		d0 f2		bne $3947c8	                BNE cpy_ext_loop        ; No: process this one
+.3947d6						ret_success
+.3947d6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3947d8		64 0e		stz $032e	                STZ DOS_STATUS
+.3947da		28		plp		                PLP
+.3947db		2b		pld		                PLD
+.3947dc		ab		plb		                PLB
+.3947dd		38		sec		                SEC
+.3947de		6b		rtl		                RTL
+.3947df						ret_failure
+.3947df		e2 20		sep #$20	                SEP #$20        ; set A short
+.3947e1		85 0e		sta $032e	                STA DOS_STATUS
+.3947e3		28		plp		                PLP
+.3947e4		2b		pld		                PLD
+.3947e5		ab		plb		                PLB
+.3947e6		18		clc		                CLC
+.3947e7		6b		rtl		                RTL
+.3947e8						DOS_FINDFILE
+.3947e8		8b		phb		                PHB
+.3947e9		0b		phd		                PHD
+.3947ea		08		php		                PHP
+.3947eb		48		pha		                PHA             ; begin setdbr macro
+.3947ec		08		php		                PHP
+.3947ed		e2 20		sep #$20	                SEP #$20        ; set A short
+.3947ef		a9 00		lda #$00	                LDA #0
+.3947f1		48		pha		                PHA
+.3947f2		ab		plb		                PLB
+.3947f3		28		plp		                PLP
+.3947f4		68		pla		                PLA             ; end setdbr macro
+.3947f5		48		pha		                PHA             ; begin setdp macro
+.3947f6		08		php		                PHP
+.3947f7		c2 20		rep #$20	                REP #$20        ; set A long
+.3947f9		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3947fc		5b		tcd		                TCD
+.3947fd		28		plp		                PLP
+.3947fe		68		pla		                PLA             ; end setdp macro
+.3947ff		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394801		22 50 47 39	jsl $394750	                JSL DOS_PARSE_PATH              ; Break out the path into its components
+.394805		b0 05		bcs $39480c	                BCS mount                       ; If success: try to open the directory
+.394807		28		plp		pass_failure    PLP                             ; If failure, just pass the failure back up
+.394808		2b		pld		                PLD
+.394809		ab		plb		                PLB
+.39480a		18		clc		                CLC
+.39480b		6b		rtl		                RTL
+.39480c		22 6a 43 39	jsl $39436a	mount           JSL DOS_MOUNT
+.394810						get_directory
+.394810		c2 20		rep #$20	                REP #$20        ; set A long
+.394812		22 1f 40 39	jsl $39401f	                JSL DOS_DIROPEN                 ; Get the directory
+.394816		b0 07		bcs $39481f	                BCS scan_entries                ; If success: start scanning the directory entries
+.394818		e2 20		sep #$20	                SEP #$20        ; set A short
+.39481a		a9 08		lda #$08	                LDA #DOS_ERR_NODIR              ; Otherwise: return a no directory error
+.39481c		82 47 00	brl $394866	                BRL ret_failure
+.39481f		22 9e 40 39	jsl $39409e	scan_entries    JSL DOS_DIRFIRST                ; Move the DIR pointer to the beginning of the sector
+.394823						scan_loop
+.394823		e2 20		sep #$20	                SEP #$20        ; set A short
+.394825		a0 00 00	ldy #$0000	                LDY #0
+.394828		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y             ; Check the directory entry
+.39482a		d0 05		bne $394831	                BNE chk_unused                  ; If there's an entry, check to see if it's unused
+.39482c		a9 09		lda #$09	                LDA #DOS_ERR_NOTFOUND           ; If end-of-directory, we couldn't find a match
+.39482e		82 35 00	brl $394866	                BRL ret_failure
+.394831		c9 e5		cmp #$e5	chk_unused      CMP #DOS_DIR_ENT_UNUSED         ; If it's unused...
+.394833		f0 26		beq $39485b	                BEQ next_entry                  ; Go to the next entry
+.394835		a0 0b 00	ldy #$000b	                LDY #DIRENTRY.ATTRIBUTE         ; Check the entry's attributes
+.394838		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.39483a		89 08		bit #$08	                BIT #DOS_ATTR_VOLUME            ; Is it a volume name?
+.39483c		d0 1d		bne $39485b	                BNE next_entry                  ; Yes: skip it!
+.39483e		29 0f		and #$0f	                AND #DOS_ATTR_LONGNAME
+.394840		c9 0f		cmp #$0f	                CMP #DOS_ATTR_LONGNAME          ; Is it a long name field?
+.394842		f0 17		beq $39485b	                BEQ next_entry                  ; Yes: skip it!
+.394844		a2 00 00	ldx #$0000	                LDX #0
+.394847		a0 00 00	ldy #$0000	                LDY #DIRENTRY.SHORTNAME
+.39484a		b7 18		lda [$0338],y	scan_cmp_loop   LDA [DOS_DIR_PTR],Y             ; Get the X'th character of the entry
+.39484c		df 3a a0 38	cmp $38a03a,x	                CMP DOS_SHORT_NAME,X            ; And compare to the X'th character of the name we want
+.394850		d0 09		bne $39485b	                BNE next_entry                  ; If not equal: try the next entry
+.394852		c8		iny		                INY                             ; Advance to the next character
+.394853		e8		inx		                INX
+.394854		e0 0b 00	cpx #$000b	                CPX #11                         ; Did we reach the end of the names?
+.394857		f0 16		beq $39486f	                BEQ match                       ; Yes: we have a match!
+.394859		80 ef		bra $39484a	                BRA scan_cmp_loop               ; No: keep checking
+.39485b		22 b9 40 39	jsl $3940b9	next_entry      JSL DOS_DIRNEXT                 ; Try to get the next directory entry
+.39485f		90 05		bcc $394866	                BCC ret_failure                 ; If we're at the end of the directory, return a failure.
+.394861		82 bf ff	brl $394823	                BRL scan_loop                   ; If found: keep scanning
+.394864		a9 08		lda #$08	bad_dir         LDA #DOS_ERR_NODIR              ; Otherwise: fail with a NODIR error (maybe something else is better)
+.394866						ret_failure
+.394866		e2 20		sep #$20	                SEP #$20        ; set A short
+.394868		85 0e		sta $032e	                STA DOS_STATUS
+.39486a		28		plp		                PLP
+.39486b		2b		pld		                PLD
+.39486c		ab		plb		                PLB
+.39486d		18		clc		                CLC
+.39486e		6b		rtl		                RTL
+.39486f						match
+.39486f		c2 20		rep #$20	                REP #$20        ; set A long
+.394871		a0 1a 00	ldy #$001a	                LDY #DIRENTRY.CLUSTER_L         ; Copy the cluster number from the directory entry
+.394874		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.394876		85 10		sta $0330	                STA DOS_CLUS_ID                 ; To DOS_CLUS_ID
+.394878		a0 14 00	ldy #$0014	                LDY #DIRENTRY.CLUSTER_H
+.39487b		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.39487d		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.39487f						ret_success
+.39487f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394881		64 0e		stz $032e	                STZ DOS_STATUS
+.394883		28		plp		                PLP
+.394884		2b		pld		                PLD
+.394885		ab		plb		                PLB
+.394886		38		sec		                SEC
+.394887		6b		rtl		                RTL
+.394888						DOS_READFILE
+.394888		8b		phb		                PHB
+.394889		0b		phd		                PHD
+.39488a		08		php		                PHP
+.39488b		48		pha		                PHA             ; begin setdbr macro
+.39488c		08		php		                PHP
+.39488d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39488f		a9 00		lda #$00	                LDA #0
+.394891		48		pha		                PHA
+.394892		ab		plb		                PLB
+.394893		28		plp		                PLP
+.394894		68		pla		                PLA             ; end setdbr macro
+.394895		48		pha		                PHA             ; begin setdp macro
+.394896		08		php		                PHP
+.394897		c2 20		rep #$20	                REP #$20        ; set A long
+.394899		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39489c		5b		tcd		                TCD
+.39489d		28		plp		                PLP
+.39489e		68		pla		                PLA             ; end setdp macro
+.39489f		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3948a1		a5 1e		lda $033e	                LDA DOS_BUFF_PTR+2
+.3948a3		48		pha		                PHA
+.3948a4		a5 1c		lda $033c	                LDA DOS_BUFF_PTR
+.3948a6		48		pha		                PHA
+.3948a7		22 e8 47 39	jsl $3947e8	                JSL DOS_FINDFILE                    ; Attempt to find the file's directory entry
+.3948ab		68		pla		                PLA
+.3948ac		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.3948ae		68		pla		                PLA
+.3948af		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.3948b1		90 0f		bcc $3948c2	                BCC pass_failure                    ; If found: try to load the cluster
+.3948b3		22 02 46 39	jsl $394602	load_cluster    JSL DOS_GETCLUSTER                  ; Get the first block of the cluster
+.3948b7		90 09		bcc $3948c2	                BCC pass_failure                    ; If there's an error... pass it up the chain
+.3948b9						ret_success
+.3948b9		e2 20		sep #$20	                SEP #$20        ; set A short
+.3948bb		64 0e		stz $032e	                STZ DOS_STATUS
+.3948bd		28		plp		                PLP
+.3948be		2b		pld		                PLD
+.3948bf		ab		plb		                PLB
+.3948c0		38		sec		                SEC
+.3948c1		6b		rtl		                RTL
+.3948c2		28		plp		pass_failure    PLP                                 ; Otherwise: pass any error up the chain
+.3948c3		2b		pld		                PLD
+.3948c4		ab		plb		                PLB
+.3948c5		18		clc		                CLC
+.3948c6		6b		rtl		                RTL
+.3948c7						ENTRYFORCLUS12
+.3948c7		8b		phb		                PHB
+.3948c8		0b		phd		                PHD
+.3948c9		08		php		                PHP
+.3948ca		48		pha		                PHA             ; begin setdbr macro
+.3948cb		08		php		                PHP
+.3948cc		e2 20		sep #$20	                SEP #$20        ; set A short
+.3948ce		a9 00		lda #$00	                LDA #0
+.3948d0		48		pha		                PHA
+.3948d1		ab		plb		                PLB
+.3948d2		28		plp		                PLP
+.3948d3		68		pla		                PLA             ; end setdbr macro
+.3948d4		48		pha		                PHA             ; begin setdp macro
+.3948d5		08		php		                PHP
+.3948d6		c2 20		rep #$20	                REP #$20        ; set A long
+.3948d8		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3948db		5b		tcd		                TCD
+.3948dc		28		plp		                PLP
+.3948dd		68		pla		                PLA             ; end setdp macro
+.3948de		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3948e0		a5 10		lda $0330	                LDA DOS_CLUS_ID                 ; DOS_TEMP := DOS_CLUS_ID * 3
+.3948e2		0a		asl a		                ASL A
+.3948e3		85 28		sta $0348	                STA DOS_TEMP
+.3948e5		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3948e7		2a		rol a		                ROL A
+.3948e8		85 2a		sta $034a	                STA DOS_TEMP+2
+.3948ea		18		clc		                CLC
+.3948eb		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3948ed		65 28		adc $0348	                ADC DOS_TEMP
+.3948ef		85 28		sta $0348	                STA DOS_TEMP
+.3948f1		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3948f3		65 2a		adc $034a	                ADC DOS_TEMP+2
+.3948f5		85 2a		sta $034a	                STA DOS_TEMP+2
+.3948f7		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := (DOS_CLUS_ID * 3) / 2
+.3948f9		66 28		ror $0348	                ROR DOS_TEMP                    ; DOS_TEMP is now the offset to the cluster's entry in the FAT
+.3948fb		a5 28		lda $0348	                LDA DOS_TEMP                    ; X should be the offset within the FAT buffer
+.3948fd		29 ff 03	and #$03ff	                AND #$003FF
+.394900		aa		tax		                TAX
+.394901		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.394903		66 28		ror $0348	                ROR DOS_TEMP
+.394905		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.394907		66 28		ror $0348	                ROR DOS_TEMP
+.394909		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.39490b		66 28		ror $0348	                ROR DOS_TEMP
+.39490d		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.39490f		66 28		ror $0348	                ROR DOS_TEMP
+.394911		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.394913		66 28		ror $0348	                ROR DOS_TEMP
+.394915		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.394917		66 28		ror $0348	                ROR DOS_TEMP
+.394919		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.39491b		66 28		ror $0348	                ROR DOS_TEMP
+.39491d		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.39491f		66 28		ror $0348	                ROR DOS_TEMP
+.394921		46 2a		lsr $034a	                LSR DOS_TEMP+2                  ; DOS_TEMP := DOS_TEMP / 512
+.394923		66 28		ror $0348	                ROR DOS_TEMP
+.394925		18		clc		                CLC                             ; DOS_FAT_LBA should be the LBA of the first FAT sector we need
+.394926		af 14 a0 38	lda $38a014	                LDA FAT_BEGIN_LBA
+.39492a		65 28		adc $0348	                ADC DOS_TEMP
+.39492c		85 24		sta $0344	                STA DOS_FAT_LBA
+.39492e		af 16 a0 38	lda $38a016	                LDA FAT_BEGIN_LBA+2
+.394932		65 2a		adc $034a	                ADC DOS_TEMP+2
+.394934		85 26		sta $0346	                STA DOS_FAT_LBA+2
+.394936		28		plp		                PLP
+.394937		2b		pld		                PLD
+.394938		ab		plb		                PLB
+.394939		6b		rtl		                RTL
+.39493a						FATFORCLUSTER12
+.39493a		8b		phb		                PHB
+.39493b		0b		phd		                PHD
+.39493c		08		php		                PHP
+.39493d		48		pha		                PHA             ; begin setdbr macro
+.39493e		08		php		                PHP
+.39493f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394941		a9 00		lda #$00	                LDA #0
+.394943		48		pha		                PHA
+.394944		ab		plb		                PLB
+.394945		28		plp		                PLP
+.394946		68		pla		                PLA             ; end setdbr macro
+.394947		48		pha		                PHA             ; begin setdp macro
+.394948		08		php		                PHP
+.394949		c2 20		rep #$20	                REP #$20        ; set A long
+.39494b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39494e		5b		tcd		                TCD
+.39494f		28		plp		                PLP
+.394950		68		pla		                PLA             ; end setdp macro
+.394951		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394953		a2 00 00	ldx #$0000	                LDX #0
+.394956		a9 5a 5a	lda #$5a5a	                LDA #$5A5A
+.394959		8f 00 a5 38	sta $38a500	clr_loop        STA DOS_FAT_SECTORS
+.39495d		e8		inx		                INX
+.39495e		e8		inx		                INX
+.39495f		e0 00 04	cpx #$0400	                CPX #1024
+.394962		d0 f5		bne $394959	                BNE clr_loop
+.394964		22 c7 48 39	jsl $3948c7	                JSL ENTRYFORCLUS12              ; Calculate the LBA
+.394968		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; Point to the desired sector in the FAT
+.39496a		85 02		sta $0322	                STA BIOS_LBA
+.39496c		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
+.39496e		85 04		sta $0324	                STA BIOS_LBA+2
+.394970		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS          ; Point to the first 512 bytes of the FAT buffer
+.394973		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394975		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
+.394978		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.39497a		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Attempt to load the first FAT sector
+.39497e		90 17		bcc $394997	                BCC error
+.394980		e6 02		inc $0322	                INC BIOS_LBA                    ; Move to the next sector
+.394982		a9 00 a7	lda #$a700	                LDA #<>DOS_FAT_SECTORS+512      ; And point to the second 512 bytes of teh FAT buffer
+.394985		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394987		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
+.39498a		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.39498c		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Attempt to load the first FAT sector
+.394990		90 05		bcc $394997	                BCC error
+.394992		28		plp		                PLP
+.394993		2b		pld		                PLD
+.394994		ab		plb		                PLB
+.394995		38		sec		                SEC
+.394996		6b		rtl		                RTL
+.394997						error
+.394997		e2 20		sep #$20	                SEP #$20        ; set A short
+.394999		a9 06		lda #$06	                LDA #DOS_ERR_FAT
+.39499b		85 0e		sta $032e	                STA DOS_STATUS
+.39499d		28		plp		                PLP
+.39499e		2b		pld		                PLD
+.39499f		ab		plb		                PLB
+.3949a0		18		clc		                CLC
+.3949a1		6b		rtl		                RTL
+.3949a2						FATFORCLUSTER32
+.3949a2		8b		phb		                PHB
+.3949a3		0b		phd		                PHD
+.3949a4		48		pha		                PHA             ; begin setdbr macro
+.3949a5		08		php		                PHP
+.3949a6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3949a8		a9 00		lda #$00	                LDA #0
+.3949aa		48		pha		                PHA
+.3949ab		ab		plb		                PLB
+.3949ac		28		plp		                PLP
+.3949ad		68		pla		                PLA             ; end setdbr macro
+.3949ae		48		pha		                PHA             ; begin setdp macro
+.3949af		08		php		                PHP
+.3949b0		c2 20		rep #$20	                REP #$20        ; set A long
+.3949b2		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3949b5		5b		tcd		                TCD
+.3949b6		28		plp		                PLP
+.3949b7		68		pla		                PLA             ; end setdp macro
+.3949b8		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3949ba		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3949bc		85 24		sta $0344	                STA DOS_FAT_LBA
+.3949be		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3949c0		85 26		sta $0346	                STA DOS_FAT_LBA+2
+.3949c2		a2 07 00	ldx #$0007	                LDX #7
+.3949c5		46 26		lsr $0346	div_loop        LSR DOS_FAT_LBA+2
+.3949c7		66 24		ror $0344	                ROR DOS_FAT_LBA
+.3949c9		ca		dex		                DEX
+.3949ca		d0 f9		bne $3949c5	                BNE div_loop
+.3949cc		18		clc		                CLC
+.3949cd		a5 24		lda $0344	                LDA DOS_FAT_LBA
+.3949cf		6f 14 a0 38	adc $38a014	                ADC FAT_BEGIN_LBA
+.3949d3		85 24		sta $0344	                STA DOS_FAT_LBA
+.3949d5		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
+.3949d7		6f 16 a0 38	adc $38a016	                ADC FAT_BEGIN_LBA+2
+.3949db		85 26		sta $0346	                STA DOS_FAT_LBA+2
+.3949dd		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; We want to load the FAT sector
+.3949df		85 02		sta $0322	                STA BIOS_LBA
+.3949e1		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
+.3949e3		85 04		sta $0324	                STA BIOS_LBA+2
+.3949e5		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS          ; We want to load the FAT sector in DOS_FAT_SECTORS
+.3949e8		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.3949ea		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
+.3949ed		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.3949ef		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Load the FAT entry
+.3949f3		b0 06		bcs $3949fb	                BCS find_entry
+.3949f5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3949f7		a9 06		lda #$06	                LDA #DOS_ERR_FAT
+.3949f9		80 0e		bra $394a09	                BRA ret_failure
+.3949fb						find_entry
+.3949fb		c2 20		rep #$20	                REP #$20        ; set A long
+.3949fd		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3949ff		0a		asl a		                ASL A
+.394a00		0a		asl a		                ASL A                           ; * 4
+.394a01		29 ff 01	and #$01ff	                AND #$1FF                       ; DOS_CLUS_ID MOD 512
+.394a04		aa		tax		                TAX                             ; X should be the offset within the sector
+.394a05		2b		pld		ret_success     PLD
+.394a06		ab		plb		                PLB
+.394a07		38		sec		                SEC                             ; return success
+.394a08		6b		rtl		                RTL
+.394a09		2b		pld		ret_failure     PLD
+.394a0a		ab		plb		                PLB
+.394a0b		18		clc		                CLC                             ; Return failure
+.394a0c		6b		rtl		                RTL
+.394a0d						NEXTCLUSTER
+.394a0d		08		php		                PHP
+.394a0e		e2 20		sep #$20	                SEP #$20        ; set A short
+.394a10		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
+.394a14		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
+.394a16		d0 08		bne $394a20	                BNE fat32                       ; No: assume it's FAT32
+.394a18		22 2e 4a 39	jsl $394a2e	fat12           JSL NEXTCLUSTER12               ; Lookup the next cluster from FAT12
+.394a1c		90 0d		bcc $394a2b	                BCC pass_failure                ; If there was an error, pass it up the chain
+.394a1e		80 06		bra $394a26	                BRA ret_success
+.394a20		22 96 4a 39	jsl $394a96	fat32           JSL NEXTCLUSTER32               ; Lookup the next cluster from FAT32
+.394a24		90 05		bcc $394a2b	                BCC pass_failure                ; If there was an error, pass it up the chain
+.394a26		64 0e		stz $032e	ret_success     STZ DOS_STATUS
+.394a28		28		plp		                PLP
+.394a29		38		sec		                SEC
+.394a2a		6b		rtl		                RTL
+.394a2b		28		plp		pass_failure    PLP
+.394a2c		18		clc		                CLC
+.394a2d		6b		rtl		                RTL
+.394a2e						NEXTCLUSTER12
+.394a2e		8b		phb		                    PHB
+.394a2f		0b		phd		                    PHD
+.394a30		08		php		                    PHP
+.394a31		48		pha		                PHA             ; begin setdbr macro
+.394a32		08		php		                PHP
+.394a33		e2 20		sep #$20	                SEP #$20        ; set A short
+.394a35		a9 00		lda #$00	                LDA #0
+.394a37		48		pha		                PHA
+.394a38		ab		plb		                PLB
+.394a39		28		plp		                PLP
+.394a3a		68		pla		                PLA             ; end setdbr macro
+.394a3b		48		pha		                PHA             ; begin setdp macro
+.394a3c		08		php		                PHP
+.394a3d		c2 20		rep #$20	                REP #$20        ; set A long
+.394a3f		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394a42		5b		tcd		                TCD
+.394a43		28		plp		                PLP
+.394a44		68		pla		                PLA             ; end setdp macro
+.394a45		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394a47		22 3a 49 39	jsl $39493a	                    JSL FATFORCLUSTER12             ; Attempt to load the FAT entries
+.394a4b		b0 03		bcs $394a50	                    BCS chk_clus_id
+.394a4d		82 41 00	brl $394a91	                    BRL pass_failure
+.394a50		a5 10		lda $0330	chk_clus_id         LDA DOS_CLUS_ID                 ; Check the cluster ID...
+.394a52		89 01 00	bit #$0001	                    BIT #1                          ; Is it odd?
+.394a55		d0 0d		bne $394a64	                    BNE is_odd                      ; Yes: calculate the next cluster for odd
+.394a57						is_even
+.394a57		c2 20		rep #$20	                REP #$20        ; set A long
+.394a59		bf 00 a5 38	lda $38a500,x	                    LDA DOS_FAT_SECTORS,X           ; DOS_CLUS_ID := DOS_FAT_SECTORS[X] & $0FFF
+.394a5d		29 ff 0f	and #$0fff	                    AND #$0FFF
+.394a60		85 28		sta $0348	                    STA DOS_TEMP
+.394a62		80 0c		bra $394a70	                    BRA check_id
+.394a64						is_odd
+.394a64		c2 20		rep #$20	                REP #$20        ; set A long
+.394a66		bf 00 a5 38	lda $38a500,x	                    LDA DOS_FAT_SECTORS,X           ; DOS_CLUS_ID := DOS_FAT_SECTORS[X] >> 4
+.394a6a		4a		lsr a		                    LSR A
+.394a6b		4a		lsr a		                    LSR A
+.394a6c		4a		lsr a		                    LSR A
+.394a6d		4a		lsr a		                    LSR A
+.394a6e		85 28		sta $0348	                    STA DOS_TEMP
+.394a70						check_id
+.394a70		c2 20		rep #$20	                REP #$20        ; set A long
+.394a72		a5 28		lda $0348	                    LDA DOS_TEMP                    ; Check the new cluster ID we got
+.394a74		29 f0 0f	and #$0ff0	                    AND #$0FF0                      ; Is it in the range $0FF0 -- $0FFF?
+.394a77		c9 f0 0f	cmp #$0ff0	                    CMP #$0FF0
+.394a7a		f0 0f		beq $394a8b	                    BEQ no_more                     ; Yes: return that we've reached the end of the chain
+.394a7c		a5 28		lda $0348	                    LDA DOS_TEMP                    ; Restore the "current" cluster ID
+.394a7e		85 10		sta $0330	                    STA DOS_CLUS_ID
+.394a80		64 12		stz $0332	                    STZ DOS_CLUS_ID+2
+.394a82						ret_success
+.394a82		e2 20		sep #$20	                SEP #$20        ; set A short
+.394a84		64 0e		stz $032e	                    STZ DOS_STATUS
+.394a86		28		plp		                    PLP
+.394a87		2b		pld		                    PLD
+.394a88		ab		plb		                    PLB
+.394a89		38		sec		                    SEC
+.394a8a		6b		rtl		                    RTL
+.394a8b						no_more
+.394a8b		e2 20		sep #$20	                SEP #$20        ; set A short
+.394a8d		a9 0a		lda #$0a	                    LDA #DOS_ERR_NOCLUSTER
+.394a8f		85 0e		sta $032e	                    STA DOS_STATUS
+.394a91		28		plp		pass_failure        PLP
+.394a92		2b		pld		                    PLD
+.394a93		ab		plb		                    PLB
+.394a94		18		clc		                    CLC
+.394a95		6b		rtl		                    RTL
+.394a96						NEXTCLUSTER32
+.394a96		8b		phb		                PHB
+.394a97		0b		phd		                PHD
+.394a98		08		php		                PHP
+.394a99		48		pha		                PHA             ; begin setdbr macro
+.394a9a		08		php		                PHP
+.394a9b		e2 20		sep #$20	                SEP #$20        ; set A short
+.394a9d		a9 00		lda #$00	                LDA #0
+.394a9f		48		pha		                PHA
+.394aa0		ab		plb		                PLB
+.394aa1		28		plp		                PLP
+.394aa2		68		pla		                PLA             ; end setdbr macro
+.394aa3		48		pha		                PHA             ; begin setdp macro
+.394aa4		08		php		                PHP
+.394aa5		c2 20		rep #$20	                REP #$20        ; set A long
+.394aa7		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394aaa		5b		tcd		                TCD
+.394aab		28		plp		                PLP
+.394aac		68		pla		                PLA             ; end setdp macro
+.394aad		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394aaf		22 a2 49 39	jsl $3949a2	                JSL FATFORCLUSTER32             ; Get the FAT entry for this cluster
+.394ab3		90 53		bcc $394b08	                BCC ret_failure                 ; If it did not work, return the error
+.394ab5		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ab7		bf 00 a5 38	lda $38a500,x	                LDA @l DOS_FAT_SECTORS,X        ; Get the entry and copy it to DOS_TEMP
+.394abb		85 28		sta $0348	                STA DOS_TEMP
+.394abd		bf 01 a5 38	lda $38a501,x	                LDA @l DOS_FAT_SECTORS+1,X
+.394ac1		85 29		sta $0349	                STA DOS_TEMP+1
+.394ac3		bf 02 a5 38	lda $38a502,x	                LDA @l DOS_FAT_SECTORS+2,X
+.394ac7		85 2a		sta $034a	                STA DOS_TEMP+2
+.394ac9		bf 03 a5 38	lda $38a503,x	                LDA @l DOS_FAT_SECTORS+3,X
+.394acd		85 2b		sta $034b	                STA DOS_TEMP+3
+.394acf		a5 28		lda $0348	xxxx            LDA DOS_TEMP                    ; Is DOS_TEMP = $FFFFFFFF?
+.394ad1		c9 ff		cmp #$ff	                CMP #$FF
+.394ad3		d0 18		bne $394aed	                BNE found_next
+.394ad5		a5 29		lda $0349	                LDA DOS_TEMP+1
+.394ad7		c9 ff		cmp #$ff	                CMP #$FF
+.394ad9		d0 12		bne $394aed	                BNE found_next
+.394adb		a5 2a		lda $034a	                LDA DOS_TEMP+2
+.394add		c9 ff		cmp #$ff	                CMP #$FF
+.394adf		d0 0c		bne $394aed	                BNE found_next
+.394ae1		a5 2b		lda $034b	                LDA DOS_TEMP+3
+.394ae3		c9 0f		cmp #$0f	                CMP #$0F
+.394ae5		d0 06		bne $394aed	                BNE found_next                  ; No: return this cluster as the next
+.394ae7		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ae9		a9 0a		lda #$0a	                LDA #DOS_ERR_NOCLUSTER          ; Yes: return that there are no more clusters
+.394aeb		80 1b		bra $394b08	                BRA ret_failure
+.394aed						found_next
+.394aed		e2 20		sep #$20	                SEP #$20        ; set A short
+.394aef		a5 28		lda $0348	                LDA DOS_TEMP                    ; No: return DOS_TEMP as the new DOS_CLUS_ID
+.394af1		85 10		sta $0330	                STA DOS_CLUS_ID
+.394af3		a5 29		lda $0349	                LDA DOS_TEMP+1
+.394af5		85 11		sta $0331	                STA DOS_CLUS_ID+1
+.394af7		a5 2a		lda $034a	                LDA DOS_TEMP+2
+.394af9		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394afb		a5 2b		lda $034b	                LDA DOS_TEMP+3
+.394afd		85 13		sta $0333	                STA DOS_CLUS_ID+3
+.394aff						ret_success
+.394aff		e2 20		sep #$20	                SEP #$20        ; set A short
+.394b01		64 0e		stz $032e	                STZ DOS_STATUS                  ; Record success
+.394b03		28		plp		                PLP
+.394b04		2b		pld		                PLD
+.394b05		ab		plb		                PLB
+.394b06		38		sec		                SEC
+.394b07		6b		rtl		                RTL
+.394b08						ret_failure
+.394b08		e2 20		sep #$20	                SEP #$20        ; set A short
+.394b0a		85 0e		sta $032e	                STA DOS_STATUS                  ; Record the error condition
+.394b0c		28		plp		                PLP
+.394b0d		2b		pld		                PLD
+.394b0e		ab		plb		                PLB
+.394b0f		18		clc		                CLC
+.394b10		6b		rtl		                RTL
+.394b11						DOS_READNEXT
+.394b11		08		php		                PHP
+.394b12		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394b14		22 0d 4a 39	jsl $394a0d	                JSL NEXTCLUSTER                 ; Attempt to find the next cluster in the FAT
+.394b18		90 09		bcc $394b23	                BCC pass_failure                ; If nothing found: pass the failure up the chain
+.394b1a		22 02 46 39	jsl $394602	                JSL DOS_GETCLUSTER              ; Otherwise: attempt to read the cluster
+.394b1e		90 03		bcc $394b23	                BCC pass_failure                ; If nothing read: pass the failure up the chain
+.394b20		28		plp		ret_success     PLP
+.394b21		38		sec		                SEC
+.394b22		6b		rtl		                RTL
+.394b23		28		plp		pass_failure    PLP
+.394b24		18		clc		                CLC
+.394b25		6b		rtl		                RTL
+.394b26						DOS_FREECLUS
+.394b26		08		php		                PHP
+.394b27		48		pha		                PHA             ; begin setdp macro
+.394b28		08		php		                PHP
+.394b29		c2 20		rep #$20	                REP #$20        ; set A long
+.394b2b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394b2e		5b		tcd		                TCD
+.394b2f		28		plp		                PLP
+.394b30		68		pla		                PLA             ; end setdp macro
+.394b31		e2 20		sep #$20	                SEP #$20        ; set A short
+.394b33		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
+.394b37		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
+.394b39		d0 08		bne $394b43	                BNE fat32                       ; No: assume it's FAT32
+.394b3b		22 b7 4b 39	jsl $394bb7	fat12           JSL DOS_FREECLUS12              ; Find the next free cluster from FAT12
+.394b3f		90 0d		bcc $394b4e	                BCC pass_failure                ; If there was an error, pass it up the chain
+.394b41		80 06		bra $394b49	                BRA ret_success
+.394b43		22 8f 4c 39	jsl $394c8f	fat32           JSL DOS_FREECLUS32              ; Find the next free cluster from FAT32
+.394b47		90 05		bcc $394b4e	                BCC pass_failure                ; If there was an error, pass it up the chain
+.394b49		64 0e		stz $032e	ret_success     STZ DOS_STATUS
+.394b4b		28		plp		                PLP
+.394b4c		38		sec		                SEC
+.394b4d		6b		rtl		                RTL
+.394b4e		28		plp		pass_failure    PLP
+.394b4f		18		clc		                CLC
+.394b50		6b		rtl		                RTL
+.394b51						FDC_READ2FAT12
+.394b51		8b		phb		                    PHB
+.394b52		0b		phd		                    PHD
+.394b53		08		php		                    PHP
+.394b54		48		pha		                PHA             ; begin setdbr macro
+.394b55		08		php		                PHP
+.394b56		e2 20		sep #$20	                SEP #$20        ; set A short
+.394b58		a9 00		lda #$00	                LDA #0
+.394b5a		48		pha		                PHA
+.394b5b		ab		plb		                PLB
+.394b5c		28		plp		                PLP
+.394b5d		68		pla		                PLA             ; end setdbr macro
+.394b5e		48		pha		                PHA             ; begin setdp macro
+.394b5f		08		php		                PHP
+.394b60		c2 20		rep #$20	                REP #$20        ; set A long
+.394b62		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394b65		5b		tcd		                TCD
+.394b66		28		plp		                PLP
+.394b67		68		pla		                PLA             ; end setdp macro
+.394b68		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394b6a		a9 00 a5	lda #$a500	                    LDA #<>DOS_FAT_SECTORS          ; Set the location to store the sector
+.394b6d		85 06		sta $0326	                    STA BIOS_BUFF_PTR
+.394b6f		a9 38 00	lda #$0038	                    LDA #`DOS_FAT_SECTORS
+.394b72		85 08		sta $0328	                    STA BIOS_BUFF_PTR+2
+.394b74		a5 24		lda $0344	                    LDA DOS_FAT_LBA
+.394b76		85 02		sta $0322	                    STA BIOS_LBA
+.394b78		a5 26		lda $0346	                    LDA DOS_FAT_LBA+2
+.394b7a		85 04		sta $0324	                    STA BIOS_LBA+2
+.394b7c		22 44 10 00	jsl $001044	                    JSL GETBLOCK                    ; Read the first sector
+.394b80		b0 07		bcs $394b89	                    BCS inc_sect2                   ; If success: start getting the second sector
+.394b82		e2 20		sep #$20	                SEP #$20        ; set A short
+.394b84		a9 06		lda #$06	                    LDA #DOS_ERR_FAT
+.394b86		82 1c 00	brl $394ba5	                    BRL ret_failure
+.394b89						inc_sect2
+.394b89		c2 20		rep #$20	                REP #$20        ; set A long
+.394b8b		e6 02		inc $0322	                    INC BIOS_LBA                    ; Move to the next sector
+.394b8d		d0 02		bne $394b91	                    BNE inc_buff_ptr
+.394b8f		e6 04		inc $0324	                    INC BIOS_LBA+2
+.394b91		a9 00 a7	lda #$a700	inc_buff_ptr        LDA #<>(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
+.394b94		85 06		sta $0326	                    STA BIOS_BUFF_PTR
+.394b96		a9 38 00	lda #$0038	                    LDA #`(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
+.394b99		85 08		sta $0328	                    STA BIOS_BUFF_PTR+2
+.394b9b		22 44 10 00	jsl $001044	                    JSL GETBLOCK                    ; Read the second sector
+.394b9f		b0 0d		bcs $394bae	                    BCS ret_success                 ; If success, return success
+.394ba1		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ba3		a9 06		lda #$06	                    LDA #DOS_ERR_FAT
+.394ba5						ret_failure
+.394ba5		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ba7		85 00		sta $0320	                    STA BIOS_STATUS
+.394ba9		28		plp		                    PLP
+.394baa		2b		pld		                    PLD
+.394bab		ab		plb		                    PLB
+.394bac		18		clc		                    CLC
+.394bad		6b		rtl		                    RTL
+.394bae						ret_success
+.394bae		e2 20		sep #$20	                SEP #$20        ; set A short
+.394bb0		64 00		stz $0320	                    STZ BIOS_STATUS
+.394bb2		28		plp		                    PLP
+.394bb3		2b		pld		                    PLD
+.394bb4		ab		plb		                    PLB
+.394bb5		38		sec		                    SEC
+.394bb6		6b		rtl		                    RTL
+.394bb7						DOS_FREECLUS12
+.394bb7		da		phx		                PHX
+.394bb8		8b		phb		                PHB
+.394bb9		0b		phd		                PHD
+.394bba		08		php		                PHP
+.394bbb		48		pha		                PHA             ; begin setdbr macro
+.394bbc		08		php		                PHP
+.394bbd		e2 20		sep #$20	                SEP #$20        ; set A short
+.394bbf		a9 00		lda #$00	                LDA #0
+.394bc1		48		pha		                PHA
+.394bc2		ab		plb		                PLB
+.394bc3		28		plp		                PLP
+.394bc4		68		pla		                PLA             ; end setdbr macro
+.394bc5		48		pha		                PHA             ; begin setdp macro
+.394bc6		08		php		                PHP
+.394bc7		c2 20		rep #$20	                REP #$20        ; set A long
+.394bc9		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394bcc		5b		tcd		                TCD
+.394bcd		28		plp		                PLP
+.394bce		68		pla		                PLA             ; end setdp macro
+.394bcf		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394bd1		a9 02 00	lda #$0002	                LDA #2                          ; Cluster ID is 2 to start with
+.394bd4		85 10		sta $0330	                STA DOS_CLUS_ID
+.394bd6		a9 00 00	lda #$0000	                LDA #0
+.394bd9		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394bdb		22 c7 48 39	jsl $3948c7	                JSL ENTRYFORCLUS12              ; Calculate the LBA and buffer offset for the cluster
+.394bdf		22 51 4b 39	jsl $394b51	                JSL FDC_READ2FAT12              ; Read the first two sectors of the FAT
+.394be3		b0 07		bcs $394bec	                BCS start_of_fat                ; If success, move X to the start of the FAT
+.394be5		e2 20		sep #$20	                SEP #$20        ; set A short
+.394be7		a9 06		lda #$06	                LDA #DOS_ERR_FAT
+.394be9		82 99 00	brl $394c85	                BRL ret_failure
+.394bec						start_of_fat
+.394bec		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394bee		a5 10		lda $0330	chk_cluster     LDA DOS_CLUS_ID                 ; Check to see if cluster number is even or odd
+.394bf0		89 01 00	bit #$0001	                BIT #1
+.394bf3		d0 09		bne $394bfe	                BNE is_odd
+.394bf5		bf 00 a5 38	lda $38a500,x	is_even         LDA DOS_FAT_SECTORS,X           ; Get the cluster status for an even numbered cluster
+.394bf9		29 ff 0f	and #$0fff	                AND #$0FFF
+.394bfc		80 08		bra $394c06	                BRA chk_available
+.394bfe		bf 00 a5 38	lda $38a500,x	is_odd          LDA DOS_FAT_SECTORS,X           ; Get the cluster status for an odd numbered cluster
+.394c02		4a		lsr a		                LSR A
+.394c03		4a		lsr a		                LSR A
+.394c04		4a		lsr a		                LSR A
+.394c05		4a		lsr a		                LSR A
+.394c06						chk_available
+.394c06		85 28		sta $0348	                STA DOS_TEMP
+.394c08		c9 00 00	cmp #$0000	                CMP #0                          ; Is it available?
+.394c0b		f0 03		beq $394c10	                BEQ chk_found
+.394c0d		82 39 00	brl $394c49	                BRL next_cluster                ; No: advance to the next cluster
+.394c10		8a		txa		chk_found       TXA
+.394c11		85 2a		sta $034a	                STA DOS_TEMP+2
+.394c13		a5 10		lda $0330	                LDA DOS_CLUS_ID                 ; Check to see if cluster number is even or odd
+.394c15		89 01 00	bit #$0001	                BIT #1
+.394c18		d0 0d		bne $394c27	                BNE is_odd2
+.394c1a						is_even2
+.394c1a		bf 00 a5 38	lda $38a500,x	                LDA DOS_FAT_SECTORS,X           ; Reserve the cluster in the FAT, even offset case
+.394c1e		09 ff 0f	ora #$0fff	                ORA #$0FFF
+.394c21		9f 00 a5 38	sta $38a500,x	                STA DOS_FAT_SECTORS,X
+.394c25		80 0b		bra $394c32	                BRA write_fat
+.394c27						is_odd2
+.394c27		bf 00 a5 38	lda $38a500,x	                LDA DOS_FAT_SECTORS,X           ; Reserve the cluster in the FAT, odd offset case
+.394c2b		09 f0 ff	ora #$fff0	                ORA #$FFF0
+.394c2e		9f 00 a5 38	sta $38a500,x	                STA DOS_FAT_SECTORS,X
+.394c32		22 59 4d 39	jsl $394d59	write_fat       JSL WRITEFAT12                  ; Write the two FAT sectors back to disk
+.394c36		b0 07		bcs $394c3f	                BCS ret_success                 ; If success: return success
+.394c38		e2 20		sep #$20	                SEP #$20        ; set A short
+.394c3a		a9 14		lda #$14	                LDA #DOS_ERR_FATUPDATE          ; Flag an error trying to write the FAT back
+.394c3c		82 46 00	brl $394c85	                BRL ret_failure
+.394c3f						ret_success
+.394c3f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394c41		64 0e		stz $032e	                STZ DOS_STATUS
+.394c43		28		plp		                PLP
+.394c44		2b		pld		                PLD
+.394c45		ab		plb		                PLB
+.394c46		fa		plx		                PLX
+.394c47		38		sec		                SEC
+.394c48		6b		rtl		                RTL
+.394c49						next_cluster
+.394c49		e6 10		inc $0330	                INC DOS_CLUS_ID                 ; And advance the cluster ID
+.394c4b		d0 02		bne $394c4f	                BNE calc_entry
+.394c4d		e6 12		inc $0332	                INC DOS_CLUS_ID+2
+.394c4f		22 c7 48 39	jsl $3948c7	calc_entry      JSL ENTRYFORCLUS12              ; Calculate the LBA and offset into the buffer for the cluster
+.394c53		e0 00 00	cpx #$0000	                CPX #0                          ; Did we wrap around?
+.394c56		f0 03		beq $394c5b	                BEQ chk_end_of_fat
+.394c58		82 93 ff	brl $394bee	                BRL chk_cluster                 ; No: go back and check it too
+.394c5b						chk_end_of_fat
+.394c5b		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; Are we at the end of the FAT?
+.394c5d		cf 18 a0 38	cmp $38a018	                CMP FAT2_BEGIN_LBA              ; NOTE: we use the start sector of the second FAT as our sentinel
+.394c61		d0 0f		bne $394c72	                BNE next_2
+.394c63		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
+.394c65		cf 1a a0 38	cmp $38a01a	                CMP FAT2_BEGIN_LBA+2
+.394c69		d0 07		bne $394c72	                BNE next_2                      ; No: get the next to sectors
+.394c6b		e2 20		sep #$20	                SEP #$20        ; set A short
+.394c6d		a9 12		lda #$12	                LDA #DOS_ERR_MEDIAFULL          ; Yes: return media full
+.394c6f		82 13 00	brl $394c85	                BRL ret_failure
+.394c72						next_2
+.394c72		22 51 4b 39	jsl $394b51	                JSL FDC_READ2FAT12              ; Read the next two sectors of the FAT
+.394c76		90 06		bcc $394c7e	                BCC fat_fail                    ; If failed: return error
+.394c78		a2 00 00	ldx #$0000	                LDX #0                          ; If success: Start scanning at the beginning of the sectors
+.394c7b		82 70 ff	brl $394bee	                BRL chk_cluster                 ; And start checking from there
+.394c7e						fat_fail
+.394c7e		e2 20		sep #$20	                SEP #$20        ; set A short
+.394c80		a9 06		lda #$06	                LDA #DOS_ERR_FAT
+.394c82		82 00 00	brl $394c85	                BRL ret_failure
+.394c85						ret_failure
+.394c85		e2 20		sep #$20	                SEP #$20        ; set A short
+.394c87		85 0e		sta $032e	                STA DOS_STATUS
+.394c89		28		plp		                PLP
+.394c8a		2b		pld		                PLD
+.394c8b		ab		plb		                PLB
+.394c8c		fa		plx		                PLX
+.394c8d		18		clc		                CLC
+.394c8e		6b		rtl		                RTL
+.394c8f						DOS_FREECLUS32
+.394c8f		8b		phb		                PHB
+.394c90		0b		phd		                PHD
+.394c91		08		php		                PHP
+.394c92		48		pha		                PHA             ; begin setdbr macro
+.394c93		08		php		                PHP
+.394c94		e2 20		sep #$20	                SEP #$20        ; set A short
+.394c96		a9 00		lda #$00	                LDA #0
+.394c98		48		pha		                PHA
+.394c99		ab		plb		                PLB
+.394c9a		28		plp		                PLP
+.394c9b		68		pla		                PLA             ; end setdbr macro
+.394c9c		48		pha		                PHA             ; begin setdp macro
+.394c9d		08		php		                PHP
+.394c9e		c2 20		rep #$20	                REP #$20        ; set A long
+.394ca0		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394ca3		5b		tcd		                TCD
+.394ca4		28		plp		                PLP
+.394ca5		68		pla		                PLA             ; end setdp macro
+.394ca6		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394ca8		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR               ; Set the location to store the sector
+.394cab		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394cad		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
+.394cb0		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394cb2		af 14 a0 38	lda $38a014	                LDA FAT_BEGIN_LBA               ; Set the LBA to that of the first FAT sector
+.394cb6		85 02		sta $0322	                STA BIOS_LBA
+.394cb8		af 16 a0 38	lda $38a016	                LDA FAT_BEGIN_LBA+2
+.394cbc		85 04		sta $0324	                STA BIOS_LBA+2
+.394cbe		22 44 10 00	jsl $001044	                JSL GETBLOCK                    ; Load the sector into memory
+.394cc2		b0 07		bcs $394ccb	                BCS initial_entry               ; If OK: set the initial entry to check
+.394cc4		e2 20		sep #$20	                SEP #$20        ; set A short
+.394cc6		a9 06		lda #$06	                LDA #DOS_ERR_FAT                ; Return a NOFAT error
+.394cc8		82 6b 00	brl $394d36	                BRL ret_failure
+.394ccb						initial_entry
+.394ccb		c2 20		rep #$20	                REP #$20        ; set A long
+.394ccd		a9 02 00	lda #$0002	                LDA #2                          ; Set DOS_CLUS_ID to 2
+.394cd0		85 10		sta $0330	                STA DOS_CLUS_ID
+.394cd2		a9 00 00	lda #$0000	                LDA #0
+.394cd5		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394cd7		a2 08 00	ldx #$0008	                LDX #8                          ; Set the offset to DOS_CLUS_ID * 4
+.394cda		bf 00 a3 38	lda $38a300,x	chk_entry       LDA DOS_SECTOR,X                ; Is the cluster entry == $00000000?
+.394cde		d0 06		bne $394ce6	                BNE next_entry                  ; No: move to the next entry
+.394ce0		bf 02 a3 38	lda $38a302,x	                LDA DOS_SECTOR+2,X
+.394ce4		f0 36		beq $394d1c	                BEQ found_free                  ; Yes: go to allocate and return it
+.394ce6		e6 10		inc $0330	next_entry      INC DOS_CLUS_ID                 ; Move to the next cluster
+.394ce8		d0 02		bne $394cec	                BNE inc_ptr
+.394cea		e6 12		inc $0332	                INC DOS_CLUS_ID+2
+.394cec		e8		inx		inc_ptr         INX                             ; Update the index to the entry
+.394ced		e8		inx		                INX
+.394cee		e8		inx		                INX
+.394cef		e8		inx		                INX
+.394cf0		e0 00 02	cpx #$0200	                CPX #DOS_SECTOR_SIZE            ; Are we outside the sector?
+.394cf3		90 e5		bcc $394cda	                BLT chk_entry                   ; No: check this entry
+.394cf5		e6 02		inc $0322	                INC BIOS_LBA                    ; Point to the next sector in the FAT
+.394cf7		d0 18		bne $394d11	                BNE get_block
+.394cf9		e6 04		inc $0324	                INC BIOS_LBA+2
+.394cfb		a5 04		lda $0324	                LDA BIOS_LBA+2
+.394cfd		cf 1a a0 38	cmp $38a01a	                CMP FAT2_BEGIN_LBA+2
+.394d01		90 0e		bcc $394d11	                BLT get_block
+.394d03		a5 02		lda $0322	                LDA BIOS_LBA
+.394d05		cf 18 a0 38	cmp $38a018	                CMP FAT2_BEGIN_LBA
+.394d09		90 06		bcc $394d11	                BLT get_block
+.394d0b		e2 20		sep #$20	                SEP #$20        ; set A short
+.394d0d		a9 12		lda #$12	                LDA #DOS_ERR_MEDIAFULL          ; No: throw a media full error
+.394d0f		80 25		bra $394d36	                BRA ret_failure
+.394d11		22 44 10 00	jsl $001044	get_block       JSL GETBLOCK                    ; Attempt to read the block
+.394d15		90 1b		bcc $394d32	                BCC ret_fat_error               ; If error: throw a FAT error
+.394d17		a2 00 00	ldx #$0000	set_ptr         LDX #0                          ; Set index pointer to the first entry
+.394d1a		80 be		bra $394cda	                BRA chk_entry                   ; Check this entry
+.394d1c						found_free
+.394d1c		c2 20		rep #$20	                REP #$20        ; set A long
+.394d1e		a9 ff ff	lda #$ffff	                LDA #<>FAT_LAST_CLUSTER         ; Set the entry to $0FFFFFFF to make it the last entry in its chain
+.394d21		9f 00 a3 38	sta $38a300,x	                STA DOS_SECTOR,X
+.394d25		a9 ff 0f	lda #$0fff	                LDA #(FAT_LAST_CLUSTER >> 16)
+.394d28		9f 02 a3 38	sta $38a302,x	                STA DOS_SECTOR+2,X
+.394d2c		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the sector back to the block device
+.394d30		b0 0d		bcs $394d3f	                BCS ret_success                 ; If OK: return success
+.394d32						ret_fat_error
+.394d32		e2 20		sep #$20	                SEP #$20        ; set A short
+.394d34		a9 06		lda #$06	                LDA #DOS_ERR_FAT                ; Otherwise: return NOFAT error
+.394d36						ret_failure
+.394d36		e2 20		sep #$20	                SEP #$20        ; set A short
+.394d38		85 0e		sta $032e	                STA DOS_STATUS
+.394d3a		28		plp		                PLP
+.394d3b		2b		pld		                PLD
+.394d3c		ab		plb		                PLB
+.394d3d		18		clc		                CLC
+.394d3e		6b		rtl		                RTL
+.394d3f						ret_success
+.394d3f		e2 20		sep #$20	                SEP #$20        ; set A short
+.394d41		64 0e		stz $032e	                STZ DOS_STATUS
+.394d43		28		plp		                PLP
+.394d44		2b		pld		                PLD
+.394d45		ab		plb		                PLB
+.394d46		38		sec		                SEC
+.394d47		6b		rtl		                RTL
+.394d48						DELCLUSTER
+.394d48		e2 20		sep #$20	                SEP #$20        ; set A short
+.394d4a		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
+.394d4e		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
+.394d50		d0 04		bne $394d56	                BNE fat32                       ; No: assume it's FAT32
+.394d52		5c a0 4d 39	jmp $394da0	fat12           JML DELCLUSTER12
+.394d56		4c ee 4d	jmp $394dee	fat32           JMP DELCLUSTER32
+.394d59						WRITEFAT12
+.394d59		8b		phb		                PHB
+.394d5a		0b		phd		                PHD
+.394d5b		48		pha		                PHA             ; begin setdbr macro
+.394d5c		08		php		                PHP
+.394d5d		e2 20		sep #$20	                SEP #$20        ; set A short
+.394d5f		a9 00		lda #$00	                LDA #0
+.394d61		48		pha		                PHA
+.394d62		ab		plb		                PLB
+.394d63		28		plp		                PLP
+.394d64		68		pla		                PLA             ; end setdbr macro
+.394d65		48		pha		                PHA             ; begin setdp macro
+.394d66		08		php		                PHP
+.394d67		c2 20		rep #$20	                REP #$20        ; set A long
+.394d69		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394d6c		5b		tcd		                TCD
+.394d6d		28		plp		                PLP
+.394d6e		68		pla		                PLA             ; end setdp macro
+.394d6f		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394d71		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS          ; Point to the first FAT sector in memory
+.394d74		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394d76		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
+.394d79		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394d7b		a5 24		lda $0344	                LDA DOS_FAT_LBA                 ; Set the LBA to that of the first sector's
+.394d7d		85 02		sta $0322	                STA BIOS_LBA
+.394d7f		a5 26		lda $0346	                LDA DOS_FAT_LBA+2
+.394d81		85 04		sta $0324	                STA BIOS_LBA+2
+.394d83		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the first sector back to the block device
+.394d87		90 14		bcc $394d9d	                BCC done
+.394d89		a9 00 a7	lda #$a700	                LDA #<>(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
+.394d8c		85 06		sta $0326	                STA BIOS_BUFF_PTR
+.394d8e		a9 38 00	lda #$0038	                LDA #`(DOS_FAT_SECTORS+DOS_SECTOR_SIZE)
+.394d91		85 08		sta $0328	                STA BIOS_BUFF_PTR+2
+.394d93		e6 02		inc $0322	                INC BIOS_LBA                    ; Point to the next sector in the FAT
+.394d95		d0 02		bne $394d99	                BNE put_second
+.394d97		e6 04		inc $0324	                INC BIOS_LBA+2
+.394d99		22 24 10 00	jsl $001024	put_second      JSL PUTBLOCK                    ; Write the second sector back to the block device
+.394d9d		2b		pld		done            PLD
+.394d9e		ab		plb		                PLB
+.394d9f		6b		rtl		                RTL
+.394da0						DELCLUSTER12
+.394da0		8b		phb		                PHB
+.394da1		0b		phd		                PHD
+.394da2		08		php		                PHP
+.394da3		48		pha		                PHA             ; begin setdbr macro
+.394da4		08		php		                PHP
+.394da5		e2 20		sep #$20	                SEP #$20        ; set A short
+.394da7		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394da9		48		pha		                PHA
+.394daa		ab		plb		                PLB
+.394dab		28		plp		                PLP
+.394dac		68		pla		                PLA             ; end setdbr macro
+.394dad		48		pha		                PHA             ; begin setdp macro
+.394dae		08		php		                PHP
+.394daf		c2 20		rep #$20	                REP #$20        ; set A long
+.394db1		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394db4		5b		tcd		                TCD
+.394db5		28		plp		                PLP
+.394db6		68		pla		                PLA             ; end setdp macro
+.394db7		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394db9		22 3a 49 39	jsl $39493a	                JSL FATFORCLUSTER12
+.394dbd		8a		txa		                TXA                             ; Check to see if the index is odd or even
+.394dbe		89 01 00	bit #$0001	                BIT #1
+.394dc1		d0 08		bne $394dcb	                BNE is_odd
+.394dc3		bd 00 a5	lda $38a500,x	is_even         LDA DOS_FAT_SECTORS,X           ; Get the two bytes from the FAT
+.394dc6		29 00 f0	and #$f000	                AND #$F000                      ; Mask out the lower 12 bits
+.394dc9		80 06		bra $394dd1	                BRA save_update
+.394dcb		bd 00 a5	lda $38a500,x	is_odd          LDA DOS_FAT_SECTORS,X           ; Get the two bytes from the FAT
+.394dce		29 0f 00	and #$000f	                AND #$000F                      ; Mask out the upper 12 bits
+.394dd1		9d 00 a5	sta $38a500,x	save_update     STA DOS_FAT_SECTORS,X           ; And write it back
+.394dd4		22 59 4d 39	jsl $394d59	                JSL WRITEFAT12                  ; Write the two FAT12 sectors back to the drive
+.394dd8		b0 0b		bcs $394de5	                BCS ret_success
+.394dda						ret_failure
+.394dda		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ddc		a9 06		lda #$06	                LDA #DOS_ERR_FAT
+.394dde		85 0e		sta $032e	                STA DOS_STATUS
+.394de0		28		plp		                PLP
+.394de1		2b		pld		                PLD
+.394de2		ab		plb		                PLB
+.394de3		18		clc		                CLC
+.394de4		6b		rtl		                RTL
+.394de5						ret_success
+.394de5		e2 20		sep #$20	                SEP #$20        ; set A short
+.394de7		64 0e		stz $032e	                STZ DOS_STATUS
+.394de9		28		plp		                PLP
+.394dea		2b		pld		                PLD
+.394deb		ab		plb		                PLB
+.394dec		38		sec		                SEC
+.394ded		6b		rtl		                RTL
+.394dee						DELCLUSTER32
+.394dee		8b		phb		                PHB
+.394def		0b		phd		                PHD
+.394df0		08		php		                PHP
+.394df1		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394df3		48		pha		                PHA             ; begin setdbr macro
+.394df4		08		php		                PHP
+.394df5		e2 20		sep #$20	                SEP #$20        ; set A short
+.394df7		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394df9		48		pha		                PHA
+.394dfa		ab		plb		                PLB
+.394dfb		28		plp		                PLP
+.394dfc		68		pla		                PLA             ; end setdbr macro
+.394dfd		48		pha		                PHA             ; begin setdp macro
+.394dfe		08		php		                PHP
+.394dff		c2 20		rep #$20	                REP #$20        ; set A long
+.394e01		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394e04		5b		tcd		                TCD
+.394e05		28		plp		                PLP
+.394e06		68		pla		                PLA             ; end setdp macro
+.394e07		22 a2 49 39	jsl $3949a2	                JSL FATFORCLUSTER32
+.394e0b		a9 00 00	lda #$0000	                LDA #0
+.394e0e		9d 00 a5	sta $38a500,x	                STA DOS_FAT_SECTORS,X           ; Set the cluster entry to 0
+.394e11		9d 02 a5	sta $38a502,x	                STA DOS_FAT_SECTORS+2,X
+.394e14		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the sector back to the block device
+.394e18		b0 0b		bcs $394e25	                BCS ret_success
+.394e1a						ret_failure
+.394e1a		e2 20		sep #$20	                SEP #$20        ; set A short
+.394e1c		a9 06		lda #$06	                LDA #DOS_ERR_FAT
+.394e1e		85 0e		sta $032e	                STA DOS_STATUS
+.394e20		28		plp		                PLP
+.394e21		2b		pld		                PLD
+.394e22		ab		plb		                PLB
+.394e23		18		clc		                CLC
+.394e24		6b		rtl		                RTL
+.394e25						ret_success
+.394e25		e2 20		sep #$20	                SEP #$20        ; set A short
+.394e27		64 0e		stz $032e	                STZ DOS_STATUS
+.394e29		28		plp		                PLP
+.394e2a		2b		pld		                PLD
+.394e2b		ab		plb		                PLB
+.394e2c		38		sec		                SEC
+.394e2d		6b		rtl		                RTL
+.394e2e						DOS_APPENDCLUS
+.394e2e		8b		phb		                PHB
+.394e2f		0b		phd		                PHD
+.394e30		08		php		                PHP
+.394e31		48		pha		                PHA             ; begin setdbr macro
+.394e32		08		php		                PHP
+.394e33		e2 20		sep #$20	                SEP #$20        ; set A short
+.394e35		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394e37		48		pha		                PHA
+.394e38		ab		plb		                PLB
+.394e39		28		plp		                PLP
+.394e3a		68		pla		                PLA             ; end setdbr macro
+.394e3b		48		pha		                PHA             ; begin setdp macro
+.394e3c		08		php		                PHP
+.394e3d		c2 20		rep #$20	                REP #$20        ; set A long
+.394e3f		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394e42		5b		tcd		                TCD
+.394e43		28		plp		                PLP
+.394e44		68		pla		                PLA             ; end setdp macro
+.394e45		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394e47		a5 12		lda $0332	                LDA DOS_CLUS_ID+2               ; Save the cluster number for later
+.394e49		48		pha		                PHA
+.394e4a		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.394e4c		48		pha		                PHA
+.394e4d		22 26 4b 39	jsl $394b26	                JSL DOS_FREECLUS                ; Find a free cluster on the block device
+.394e51		b0 09		bcs $394e5c	                BCS save_cluster                ; If we got a cluster, write the data to it
+.394e53		68		pla		fail_cleanup    PLA                             ; Restore the cluster of the file
+.394e54		85 10		sta $0330	                STA DOS_CLUS_ID
+.394e56		68		pla		                PLA
+.394e57		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394e59		82 7d 00	brl $394ed9	                BRL pass_failure                ; Pass the failure back up the chain
+.394e5c		a5 10		lda $0330	save_cluster    LDA DOS_CLUS_ID
+.394e5e		8d 36 a0	sta $38a036	                STA DOS_NEW_CLUSTER
+.394e61		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.394e63		8d 38 a0	sta $38a038	                STA DOS_NEW_CLUSTER+2
+.394e66		22 3f 46 39	jsl $39463f	                JSL DOS_PUTCLUSTER              ; Write the data to the free cluster
+.394e6a		90 e7		bcc $394e53	                BCC fail_cleanup                ; If failure: clean up stack and pass the failure up
+.394e6c		68		pla		                PLA                             ; Restore the cluster of the file
+.394e6d		85 10		sta $0330	                STA DOS_CLUS_ID
+.394e6f		68		pla		                PLA
+.394e70		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.394e72		22 0d 4a 39	jsl $394a0d	walk_loop       JSL NEXTCLUSTER                 ; Try to get the next cluster in the chain
+.394e76		b0 fa		bcs $394e72	                BCS walk_loop                   ; If found a cluster, keep walking the chain
+.394e78		e2 20		sep #$20	                SEP #$20        ; set A short
+.394e7a		af 01 a0 38	lda $38a001	                LDA @l FILE_SYSTEM              ; Get the file system code
+.394e7e		c9 00		cmp #$00	                CMP #PART_TYPE_FAT12            ; Is it FAT12?
+.394e80		d0 3d		bne $394ebf	                BNE fat32                       ; No: assume it's FAT32
+.394e82						fat12
+.394e82		c2 20		rep #$20	                REP #$20        ; set A long
+.394e84		22 c7 48 39	jsl $3948c7	                JSL ENTRYFORCLUS12              ; Make sure we have the right offset for the cluster
+.394e88		a5 10		lda $0330	                LDA DOS_CLUS_ID                 ; Check to see if the last cluster ID is even or odd
+.394e8a		89 01 00	bit #$0001	                BIT #1
+.394e8d		d0 11		bne $394ea0	                BNE is_odd
+.394e8f		ad 36 a0	lda $38a036	is_even         LDA DOS_NEW_CLUSTER             ; Handle the even case (change the lower 12 bits)
+.394e92		29 ff 0f	and #$0fff	                AND #$0FFF
+.394e95		8d 36 a0	sta $38a036	                STA DOS_NEW_CLUSTER
+.394e98		bd 00 a5	lda $38a500,x	                LDA DOS_FAT_SECTORS,X
+.394e9b		29 00 f0	and #$f000	                AND #$F000
+.394e9e		80 10		bra $394eb0	                BRA update_fat12
+.394ea0		ad 36 a0	lda $38a036	is_odd          LDA DOS_NEW_CLUSTER             ; Handle the odd case (change the upper 12 bits)
+.394ea3		0a		asl a		                ASL A
+.394ea4		0a		asl a		                ASL A
+.394ea5		0a		asl a		                ASL A
+.394ea6		0a		asl a		                ASL A
+.394ea7		8d 36 a0	sta $38a036	                STA DOS_NEW_CLUSTER
+.394eaa		bd 00 a5	lda $38a500,x	                LDA DOS_FAT_SECTORS,X
+.394ead		29 0f 00	and #$000f	                AND #$000F
+.394eb0		0d 36 a0	ora $38a036	update_fat12    ORA DOS_NEW_CLUSTER
+.394eb3		9d 00 a5	sta $38a500,x	                STA DOS_FAT_SECTORS,X
+.394eb6		22 59 4d 39	jsl $394d59	                JSL WRITEFAT12                  ; Write the two FAT12 sectors back to the drive
+.394eba		b0 22		bcs $394ede	                BCS ret_success
+.394ebc		82 1a 00	brl $394ed9	                BRL pass_failure
+.394ebf						fat32
+.394ebf		c2 20		rep #$20	                REP #$20        ; set A long
+.394ec1		ad 36 a0	lda $38a036	                LDA DOS_NEW_CLUSTER             ; Write the ID of the new cluster to the end of the chain
+.394ec4		9d 00 a5	sta $38a500,x	                STA DOS_FAT_SECTORS,X
+.394ec7		ad 38 a0	lda $38a038	                LDA DOS_NEW_CLUSTER+2
+.394eca		9d 02 a5	sta $38a502,x	                STA DOS_FAT_SECTORS+2,X
+.394ecd		22 24 10 00	jsl $001024	                JSL PUTBLOCK                    ; Write the FAT sector back (assumes BIOS_LBA and BIOS_BUFF_PTR haven't changed)
+.394ed1		b0 0b		bcs $394ede	                BCS ret_success
+.394ed3		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ed5		a9 06		lda #$06	                LDA #DOS_ERR_FAT                ; Problem working with the FAT
+.394ed7		85 0e		sta $032e	                STA DOS_STATUS
+.394ed9		28		plp		pass_failure    PLP
+.394eda		2b		pld		                PLD
+.394edb		ab		plb		                PLB
+.394edc		18		clc		                CLC
+.394edd		6b		rtl		                RTL
+.394ede						ret_success
+.394ede		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ee0		64 0e		stz $032e	                STZ DOS_STATUS
+.394ee2		28		plp		                PLP
+.394ee3		2b		pld		                PLD
+.394ee4		ab		plb		                PLB
+.394ee5		38		sec		                SEC
+.394ee6		6b		rtl		                RTL
+.394ee7						BCD2BIN
+.394ee7		8b		phb		                PHB
+.394ee8		0b		phd		                PHD
+.394ee9		08		php		                PHP
+.394eea		48		pha		                PHA             ; begin setdbr macro
+.394eeb		08		php		                PHP
+.394eec		e2 20		sep #$20	                SEP #$20        ; set A short
+.394eee		a9 00		lda #$00	                LDA #0
+.394ef0		48		pha		                PHA
+.394ef1		ab		plb		                PLB
+.394ef2		28		plp		                PLP
+.394ef3		68		pla		                PLA             ; end setdbr macro
+.394ef4		48		pha		                PHA             ; begin setdp macro
+.394ef5		08		php		                PHP
+.394ef6		c2 20		rep #$20	                REP #$20        ; set A long
+.394ef8		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394efb		5b		tcd		                TCD
+.394efc		28		plp		                PLP
+.394efd		68		pla		                PLA             ; end setdp macro
+.394efe		c2 30		rep #$30	                REP #$30        ; set A&X long
+.394f00		85 28		sta $0348	                STA DOS_TEMP
+.394f02		29 0f 00	and #$000f	                AND #$000F
+.394f05		85 2a		sta $034a	                STA DOS_TEMP+2
+.394f07		a5 28		lda $0348	                LDA DOS_TEMP
+.394f09		4a		lsr a		                LSR A
+.394f0a		4a		lsr a		                LSR A
+.394f0b		4a		lsr a		                LSR A
+.394f0c		4a		lsr a		                LSR A
+.394f0d		85 28		sta $0348	                STA DOS_TEMP
+.394f0f		29 0f 00	and #$000f	                AND #$000F
+.394f12		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
+.394f16		a9 0a 00	lda #$000a	                LDA #10
+.394f19		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
+.394f1d		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
+.394f21		18		clc		                CLC
+.394f22		65 2a		adc $034a	                ADC DOS_TEMP+2
+.394f24		85 2a		sta $034a	                STA DOS_TEMP+2
+.394f26		a5 28		lda $0348	                LDA DOS_TEMP
+.394f28		4a		lsr a		                LSR A
+.394f29		4a		lsr a		                LSR A
+.394f2a		4a		lsr a		                LSR A
+.394f2b		4a		lsr a		                LSR A
+.394f2c		85 28		sta $0348	                STA DOS_TEMP
+.394f2e		29 0f 00	and #$000f	                AND #$000F
+.394f31		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
+.394f35		a9 64 00	lda #$0064	                LDA #100
+.394f38		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
+.394f3c		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
+.394f40		18		clc		                CLC
+.394f41		65 2a		adc $034a	                ADC DOS_TEMP+2
+.394f43		85 2a		sta $034a	                STA DOS_TEMP+2
+.394f45		a5 28		lda $0348	                LDA DOS_TEMP
+.394f47		4a		lsr a		                LSR A
+.394f48		4a		lsr a		                LSR A
+.394f49		4a		lsr a		                LSR A
+.394f4a		4a		lsr a		                LSR A
+.394f4b		29 0f 00	and #$000f	                AND #$000F
+.394f4e		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
+.394f52		a9 e8 03	lda #$03e8	                LDA #1000
+.394f55		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
+.394f59		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
+.394f5d		18		clc		                CLC
+.394f5e		65 2a		adc $034a	                ADC DOS_TEMP+2
+.394f60		28		plp		                PLP
+.394f61		2b		pld		                PLD
+.394f62		ab		plb		                PLB
+.394f63		6b		rtl		                RTL
+.394f64						DOS_RTCCREATE
+.394f64		8b		phb		                PHB
+.394f65		0b		phd		                PHD
+.394f66		08		php		                PHP
+.394f67		48		pha		                PHA             ; begin setdbr macro
+.394f68		08		php		                PHP
+.394f69		e2 20		sep #$20	                SEP #$20        ; set A short
+.394f6b		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.394f6d		48		pha		                PHA
+.394f6e		ab		plb		                PLB
+.394f6f		28		plp		                PLP
+.394f70		68		pla		                PLA             ; end setdbr macro
+.394f71		48		pha		                PHA             ; begin setdp macro
+.394f72		08		php		                PHP
+.394f73		c2 20		rep #$20	                REP #$20        ; set A long
+.394f75		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.394f78		5b		tcd		                TCD
+.394f79		28		plp		                PLP
+.394f7a		68		pla		                PLA             ; end setdp macro
+.394f7b		c2 10		rep #$10	                REP #$10        ; set X long
+.394f7d		e2 20		sep #$20	                SEP #$20        ; set A short
+.394f7f		af 0e 08 af	lda $af080e	                LDA @l RTC_CTRL             ; Turn off the updates to the clock
+.394f83		09 08		ora #$08	                ORA #%00001000
+.394f85		8f 0e 08 af	sta $af080e	                STA @l RTC_CTRL
+.394f89		af 0f 08 af	lda $af080f	                LDA @l RTC_CENTURY
+.394f8d		85 29		sta $0349	                STA DOS_TEMP+1
+.394f8f		af 0a 08 af	lda $af080a	                LDA @l RTC_YEAR             ; Get the year
+.394f93		85 28		sta $0348	                STA DOS_TEMP
+.394f95		c2 20		rep #$20	                REP #$20        ; set A long
+.394f97		a5 28		lda $0348	                LDA DOS_TEMP
+.394f99		22 e7 4e 39	jsl $394ee7	                JSL BCD2BIN                 ; Convert it to binary
+.394f9d		85 28		sta $0348	                STA DOS_TEMP
+.394f9f		38		sec		                SEC                         ; Year is relative to 1980
+.394fa0		e9 bc 07	sbc #$07bc	                SBC #1980
+.394fa3		c2 20		rep #$20	                REP #$20        ; set A long
+.394fa5		0a		asl a		                ASL A
+.394fa6		0a		asl a		                ASL A
+.394fa7		0a		asl a		                ASL A
+.394fa8		0a		asl a		                ASL A
+.394fa9		0a		asl a		                ASL A
+.394faa		0a		asl a		                ASL A
+.394fab		0a		asl a		                ASL A
+.394fac		0a		asl a		                ASL A
+.394fad		0a		asl a		                ASL A
+.394fae		29 00 fe	and #$fe00	                AND #$FE00
+.394fb1		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE   ; And save it to the creation date field
+.394fb4		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.394fb6		e2 20		sep #$20	                SEP #$20        ; set A short
+.394fb8		af 09 08 af	lda $af0809	                LDA @l RTC_MONTH            ; Get the month
+.394fbc		c2 20		rep #$20	                REP #$20        ; set A long
+.394fbe		29 ff 00	and #$00ff	                AND #$00FF
+.394fc1		22 e7 4e 39	jsl $394ee7	                JSL BCD2BIN                 ; Convert it to binary
+.394fc5		29 ff 00	and #$00ff	                AND #$00FF                  ; Move the year to bits 15 - 9
+.394fc8		0a		asl a		                ASL A
+.394fc9		0a		asl a		                ASL A
+.394fca		0a		asl a		                ASL A
+.394fcb		0a		asl a		                ASL A
+.394fcc		0a		asl a		                ASL A
+.394fcd		29 e0 01	and #$01e0	                AND #$01E0                  ; Make sure only the month is covered
+.394fd0		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE   ; And save it to the creation date field
+.394fd3		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
+.394fd5		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.394fd7		e2 20		sep #$20	                SEP #$20        ; set A short
+.394fd9		af 06 08 af	lda $af0806	                LDA @l RTC_DAY              ; Get the day
+.394fdd		c2 20		rep #$20	                REP #$20        ; set A long
+.394fdf		29 ff 00	and #$00ff	                AND #$00FF
+.394fe2		22 e7 4e 39	jsl $394ee7	                JSL BCD2BIN                 ; Convert it to binary
+.394fe6		29 1f 00	and #$001f	                AND #$001F                  ; Make sure only the day is covered
+.394fe9		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE   ; And save it to the creation date field
+.394fec		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
+.394fee		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.394ff0		e2 20		sep #$20	                SEP #$20        ; set A short
+.394ff2		af 04 08 af	lda $af0804	                LDA @l RTC_HRS              ; Get the hour
+.394ff6		29 1f		and #$1f	                AND #$1F                    ; Trim AM/PM bit
+.394ff8		c2 20		rep #$20	                REP #$20        ; set A long
+.394ffa		29 ff 00	and #$00ff	                AND #$00FF
+.394ffd		22 e7 4e 39	jsl $394ee7	                JSL BCD2BIN                 ; Convert it to binary
+.395001		c2 20		rep #$20	                REP #$20        ; set A long
+.395003		0a		asl a		                ASL A
+.395004		0a		asl a		                ASL A
+.395005		0a		asl a		                ASL A
+.395006		0a		asl a		                ASL A
+.395007		0a		asl a		                ASL A
+.395008		0a		asl a		                ASL A
+.395009		0a		asl a		                ASL A
+.39500a		0a		asl a		                ASL A
+.39500b		0a		asl a		                ASL A
+.39500c		0a		asl a		                ASL A
+.39500d		0a		asl a		                ASL A
+.39500e		29 00 f8	and #$f800	                AND #$F800
+.395011		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME   ; And save it to the creation time field
+.395014		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395016		e2 20		sep #$20	                SEP #$20        ; set A short
+.395018		af 02 08 af	lda $af0802	                LDA @l RTC_MIN              ; Get the minute
+.39501c		c2 20		rep #$20	                REP #$20        ; set A long
+.39501e		29 ff 00	and #$00ff	                AND #$00FF
+.395021		22 e7 4e 39	jsl $394ee7	                JSL BCD2BIN                 ; Convert it to binary
+.395025		c2 20		rep #$20	                REP #$20        ; set A long
+.395027		0a		asl a		                ASL A
+.395028		0a		asl a		                ASL A
+.395029		0a		asl a		                ASL A
+.39502a		0a		asl a		                ASL A
+.39502b		0a		asl a		                ASL A
+.39502c		29 e0 07	and #$07e0	                AND #$07E0
+.39502f		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME   ; And save it to the creation time field
+.395032		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
+.395034		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395036		e2 20		sep #$20	                SEP #$20        ; set A short
+.395038		af 00 08 af	lda $af0800	                LDA @l RTC_SEC              ; Get the second
+.39503c		c2 20		rep #$20	                REP #$20        ; set A long
+.39503e		29 ff 00	and #$00ff	                AND #$00FF
+.395041		22 e7 4e 39	jsl $394ee7	                JSL BCD2BIN                 ; Convert it to binary
+.395045		c2 20		rep #$20	                REP #$20        ; set A long
+.395047		29 1f 00	and #$001f	                AND #$001F
+.39504a		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME   ; And save it to the creation time field
+.39504d		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
+.39504f		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395051		af 0e 08 af	lda $af080e	                LDA @l RTC_CTRL             ; Turn on the updates again
+.395055		29 f7 00	and #$00f7	                AND #%11110111
+.395058		8f 0e 08 af	sta $af080e	                STA @l RTC_CTRL
+.39505c		28		plp		                PLP
+.39505d		2b		pld		                PLD
+.39505e		ab		plb		                PLB
+.39505f		6b		rtl		                RTL
+.395060						DOS_CREATE
+.395060		8b		phb		                PHB
+.395061		0b		phd		                PHD
+.395062		08		php		                PHP
+.395063		48		pha		                PHA             ; begin setdbr macro
+.395064		08		php		                PHP
+.395065		e2 20		sep #$20	                SEP #$20        ; set A short
+.395067		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395069		48		pha		                PHA
+.39506a		ab		plb		                PLB
+.39506b		28		plp		                PLP
+.39506c		68		pla		                PLA             ; end setdbr macro
+.39506d		48		pha		                PHA             ; begin setdp macro
+.39506e		08		php		                PHP
+.39506f		c2 20		rep #$20	                REP #$20        ; set A long
+.395071		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395074		5b		tcd		                TCD
+.395075		28		plp		                PLP
+.395076		68		pla		                PLA             ; end setdp macro
+.395077		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395079		a0 02 00	ldy #$0002	                LDY #FILEDESC.PATH              ; DOS_TEMP := DOS_FD_PTR->PATH
+.39507c		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39507e		85 28		sta $0348	                STA DOS_TEMP
+.395080		c8		iny		                INY
+.395081		c8		iny		                INY
+.395082		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395084		85 2a		sta $034a	                STA DOS_TEMP+2
+.395086		e2 20		sep #$20	                SEP #$20        ; set A short
+.395088		a0 00 00	ldy #$0000	                LDY #0
+.39508b		a2 00 00	ldx #$0000	                LDX #0
+.39508e		b7 28		lda [$0348],y	path_loop       LDA [DOS_TEMP],Y                ; Get a byte of the path
+.395090		95 e0		sta $0400,x	                STA DOS_PATH_BUFF,X             ; ... save it to the path buffer
+.395092		f0 04		beq $395098	                BEQ find_file                   ; If it's NULL, we're done
+.395094		e8		inx		                INX
+.395095		c8		iny		                INY
+.395096		80 f6		bra $39508e	                BRA path_loop
+.395098		22 50 47 39	jsl $394750	find_file       JSL DOS_PARSE_PATH
+.39509c		22 e8 47 39	jsl $3947e8	                JSL DOS_FINDFILE
+.3950a0		90 07		bcc $3950a9	                BCC set_device
+.3950a2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3950a4		a9 0b		lda #$0b	                LDA #DOS_ERR_FILEEXISTS
+.3950a6		82 d2 00	brl $39517b	                BRL ret_failure
+.3950a9						set_device
+.3950a9		e2 20		sep #$20	                SEP #$20        ; set A short
+.3950ab		a0 01 00	ldy #$0001	                LDY #FILEDESC.DEV               ; Set the device in the file descriptor
+.3950ae		a5 01		lda $0321	                LDA BIOS_DEV
+.3950b0		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3950b2						validate_name
+.3950b2		22 26 4b 39	jsl $394b26	                JSL DOS_FREECLUS
+.3950b6		b0 03		bcs $3950bb	                BCS save_data
+.3950b8		82 c4 00	brl $39517f	                BRL pass_failure
+.3950bb						save_data
+.3950bb		c2 20		rep #$20	                REP #$20        ; set A long
+.3950bd		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER
+.3950c0		a5 10		lda $0330	                LDA DOS_CLUS_ID             ; DOS_FD_PTR->FIRST_CLUSTER := DOS_CLUS_ID
+.3950c2		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3950c4		c8		iny		                INY
+.3950c5		c8		iny		                INY
+.3950c6		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3950c8		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3950ca		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER        ; DOS_BUFF_PTR := DOS_FD_PTR->BUFFER
+.3950cd		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3950cf		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.3950d1		c8		iny		                INY
+.3950d2		c8		iny		                INY
+.3950d3		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3950d5		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.3950d7		22 3f 46 39	jsl $39463f	                JSL DOS_PUTCLUSTER
+.3950db		b0 00		bcs $3950dd	                BCS find_dir
+.3950dd						find_dir
+.3950dd		c2 20		rep #$20	                REP #$20        ; set A long
+.3950df		22 7a 41 39	jsl $39417a	                JSL DOS_DIRFINDFREE
+.3950e3		b0 1a		bcs $3950ff	                BCS set_entry
+.3950e5		c2 20		rep #$20	                REP #$20        ; set A long
+.3950e7		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER     ; Failed to get the directory entry...
+.3950ea		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y              ; DOS_CLUS_ID := DOS_FD_PTR->FIRST_CLUSTER
+.3950ec		85 10		sta $0330	                STA DOS_CLUS_ID
+.3950ee		c8		iny		                INY
+.3950ef		c8		iny		                INY
+.3950f0		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3950f2		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.3950f4		22 ee 4d 39	jsl $394dee	                JSL DELCLUSTER32                ; Delete the cluster
+.3950f8		e2 20		sep #$20	                SEP #$20        ; set A short
+.3950fa		a9 08		lda #$08	                LDA #DOS_ERR_NODIR              ; Return that we couldn't read the directory
+.3950fc		82 7c 00	brl $39517b	                BRL ret_failure
+.3950ff						set_entry
+.3950ff		e2 20		sep #$20	                SEP #$20        ; set A short
+.395101		a0 00 00	ldy #$0000	                LDY #0
+.395104		a9 00		lda #$00	                LDA #0                          ; NULL
+.395106		97 18		sta [$0338],y	copy_dir_loop   STA [DOS_DIR_PTR],Y             ; Save it to the directory cluster
+.395108		c8		iny		                INY
+.395109		c0 20 00	cpy #$0020	                CPY #SIZE(DIRENTRY)
+.39510c		d0 f8		bne $395106	                BNE copy_dir_loop
+.39510e		a0 00 00	ldy #$0000	                LDY #0
+.395111		b9 3a a0	lda $38a03a,y	name_loop       LDA DOS_SHORT_NAME,Y            ; Copy the name over
+.395114		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.395116		c8		iny		                INY
+.395117		c0 0b 00	cpy #$000b	                CPY #11
+.39511a		d0 f5		bne $395111	                BNE name_loop
+.39511c		c2 20		rep #$20	                REP #$20        ; set A long
+.39511e		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER     ; DOS_DIR_PTR->CLUSTER_L := DOS_FD_PTR->FIRST_CLUSTER[15..0]
+.395121		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395123		a0 1a 00	ldy #$001a	                LDY #DIRENTRY.CLUSTER_L
+.395126		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.395128		a0 0c 00	ldy #$000c	                LDY #FILEDESC.FIRST_CLUSTER+2   ; DOS_DIR_PTR->CLUSTER_H := DOS_FD_PTR->FIRST_CLUSTER[31..16]
+.39512b		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39512d		a0 14 00	ldy #$0014	                LDY #DIRENTRY.CLUSTER_H
+.395130		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.395132		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE              ; DOS_DIR_PTR->SIZE := DOS_FD_PTR->SIZE
+.395135		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395137		a0 1c 00	ldy #$001c	                LDY #DIRENTRY.SIZE
+.39513a		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.39513c		a0 14 00	ldy #$0014	                LDY #FILEDESC.SIZE+2
+.39513f		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395141		a0 1e 00	ldy #$001e	                LDY #DIRENTRY.SIZE+2
+.395144		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.395146		a9 00 00	lda #$0000	                LDA #0                          ; Force create date-time to 0
+.395149		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE       ; TODO: restore the RTC integration when that is working better.
+.39514c		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39514e		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME
+.395151		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395153		a0 16 00	ldy #$0016	                LDY #FILEDESC.CREATE_DATE       ; DOS_DIR_PTR->CREATE_DATE := DOS_FD_PTR->CREATE_DATE
+.395156		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395158		a0 10 00	ldy #$0010	                LDY #DIRENTRY.CREATE_DATE
+.39515b		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.39515d		a0 18 00	ldy #$0018	                LDY #DIRENTRY.MODIFIED_DATE     ; And DOS_DIR_PTR->MODIFIED_DATE
+.395160		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.395162		a0 18 00	ldy #$0018	                LDY #FILEDESC.CREATE_TIME       ; DOS_DIR_PTR->CREATE_TIME := DOS_FD_PTR->CREATE_TIME
+.395165		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395167		a0 0e 00	ldy #$000e	                LDY #DIRENTRY.CREATE_TIME
+.39516a		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.39516c		a0 16 00	ldy #$0016	                LDY #DIRENTRY.MODIFIED_TIME     ; And DOS_DIR_PTR->MODIFIED_TIME
+.39516f		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.395171		c2 20		rep #$20	                REP #$20        ; set A long
+.395173		22 38 42 39	jsl $394238	                JSL DOS_DIRWRITE
+.395177		b0 0b		bcs $395184	                BCS ret_success
+.395179		80 04		bra $39517f	                BRA pass_failure
+.39517b						ret_failure
+.39517b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39517d		85 0e		sta $032e	                STA DOS_STATUS
+.39517f		28		plp		pass_failure    PLP
+.395180		2b		pld		                PLD
+.395181		ab		plb		                PLB
+.395182		18		clc		                CLC
+.395183		6b		rtl		                RTL
+.395184						ret_success
+.395184		e2 20		sep #$20	                SEP #$20        ; set A short
+.395186		64 0e		stz $032e	                STZ DOS_STATUS
+.395188		28		plp		                PLP
+.395189		2b		pld		                PLD
+.39518a		ab		plb		                PLB
+.39518b		38		sec		                SEC
+.39518c		6b		rtl		                RTL
+.39518d						DOS_COPYPATH
+.39518d		da		phx		                PHX
+.39518e		5a		phy		                PHY
+.39518f		8b		phb		                PHB
+.395190		0b		phd		                PHD
+.395191		08		php		                PHP
+.395192		48		pha		                PHA             ; begin setdbr macro
+.395193		08		php		                PHP
+.395194		e2 20		sep #$20	                SEP #$20        ; set A short
+.395196		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395198		48		pha		                PHA
+.395199		ab		plb		                PLB
+.39519a		28		plp		                PLP
+.39519b		68		pla		                PLA             ; end setdbr macro
+.39519c		48		pha		                PHA             ; begin setdp macro
+.39519d		08		php		                PHP
+.39519e		c2 20		rep #$20	                REP #$20        ; set A long
+.3951a0		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3951a3		5b		tcd		                TCD
+.3951a4		28		plp		                PLP
+.3951a5		68		pla		                PLA             ; end setdp macro
+.3951a6		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3951a8		a9 00 00	lda #$0000	                LDA #0                  ; Set the DOS_PATH_BUFF to all zeros
+.3951ab		a2 00 00	ldx #$0000	                LDX #0
+.3951ae		95 e0		sta $0400,x	clr_loop        STA DOS_PATH_BUFF,X
+.3951b0		e8		inx		                INX
+.3951b1		e8		inx		                INX
+.3951b2		e0 00 01	cpx #$0100	                CPX #256
+.3951b5		d0 f7		bne $3951ae	                BNE clr_loop
+.3951b7		a5 20		lda $0340	                LDA DOS_FD_PTR          ; Is the DOS_FD_PTR null?
+.3951b9		d0 04		bne $3951bf	                BNE get_path            ; No: attempt to fetch the path
+.3951bb		a5 22		lda $0342	                LDA DOS_FD_PTR+2
+.3951bd		f0 27		beq $3951e6	                BEQ done                ; Yes: return an empty buffer
+.3951bf		a0 02 00	ldy #$0002	get_path        LDY #FILEDESC.PATH      ; Get the path buffer
+.3951c2		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3951c4		85 28		sta $0348	                STA DOS_TEMP
+.3951c6		c8		iny		                INY
+.3951c7		c8		iny		                INY
+.3951c8		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3951ca		85 2a		sta $034a	                STA DOS_TEMP+2
+.3951cc		a5 28		lda $0348	                LDA DOS_TEMP            ; Is the path pointer NULL?
+.3951ce		d0 04		bne $3951d4	                BNE start_copy          ; No: start copying it
+.3951d0		a5 2a		lda $034a	                LDA DOS_TEMP+2
+.3951d2		f0 12		beq $3951e6	                BEQ done                ; Yes: return an empty buffer
+.3951d4						start_copy
+.3951d4		e2 20		sep #$20	                SEP #$20        ; set A short
+.3951d6		a2 00 00	ldx #$0000	                LDX #0
+.3951d9		a0 00 00	ldy #$0000	                LDY #0
+.3951dc		b7 28		lda [$0348],y	loop            LDA [DOS_TEMP],Y
+.3951de		95 e0		sta $0400,x	                STA DOS_PATH_BUFF,X
+.3951e0		f0 04		beq $3951e6	                BEQ done
+.3951e2		e8		inx		                INX
+.3951e3		c8		iny		                INY
+.3951e4		d0 f6		bne $3951dc	                BNE loop
+.3951e6		28		plp		done            PLP
+.3951e7		2b		pld		                PLD
+.3951e8		ab		plb		                PLB
+.3951e9		7a		ply		                PLY
+.3951ea		fa		plx		                PLX
+.3951eb		6b		rtl		                RTL
+
+;******  Return to file: src\sdos.asm
+
+.3951ec						DOS_TEST
+.3951ec		8b		phb		                PHB
+.3951ed		0b		phd		                PHD
+.3951ee		08		php		                PHP
+.3951ef		48		pha		                PHA             ; begin setdbr macro
+.3951f0		08		php		                PHP
+.3951f1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3951f3		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3951f5		48		pha		                PHA
+.3951f6		ab		plb		                PLB
+.3951f7		28		plp		                PLP
+.3951f8		68		pla		                PLA             ; end setdbr macro
+.3951f9		48		pha		                PHA             ; begin setdp macro
+.3951fa		08		php		                PHP
+.3951fb		c2 20		rep #$20	                REP #$20        ; set A long
+.3951fd		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395200		5b		tcd		                TCD
+.395201		28		plp		                PLP
+.395202		68		pla		                PLA             ; end setdp macro
+.395203		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395205		a9 2b 52	lda #$522b	                LDA #<>src_file
+.395208		8f 64 03 00	sta $000364	                STA @l DOS_STR1_PTR
+.39520c		a9 39 00	lda #$0039	                LDA #`src_file
+.39520f		8f 66 03 00	sta $000366	                STA @l DOS_STR1_PTR+2
+.395213		a9 38 52	lda #$5238	                LDA #<>dst_file
+.395216		8f 68 03 00	sta $000368	                STA @l DOS_STR2_PTR
+.39521a		a9 39 00	lda #$0039	                LDA #`dst_file
+.39521d		8f 6a 03 00	sta $00036a	                STA @l DOS_STR2_PTR+2
+.395221		22 da 58 39	jsl $3958da	                JSL IF_COPY
+.395225		b0 00		bcs $395227	                BCS done
+.395227		28		plp		done            PLP
+.395228		2b		pld		                PLD
+.395229		ab		plb		                PLB
+.39522a		6b		rtl		                RTL
+>39522b		40 73 3a 68 65 6c 6c 6f		src_file        .null "@s:hello.bas"
+>395233		2e 62 61 73 00
+>395238		40 73 3a 68 65 6c 6c 6f		dst_file        .null "@s:hello2.bas"
+>395240		32 2e 62 61 73 00
+.395246						IF_OPEN
+.395246		da		phx		                PHX
+.395247		5a		phy		                PHY
+.395248		0b		phd		                PHD
+.395249		8b		phb		                PHB
+.39524a		08		php		                PHP
+.39524b		48		pha		                PHA             ; begin setdbr macro
+.39524c		08		php		                PHP
+.39524d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39524f		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395251		48		pha		                PHA
+.395252		ab		plb		                PLB
+.395253		28		plp		                PLP
+.395254		68		pla		                PLA             ; end setdbr macro
+.395255		48		pha		                PHA             ; begin setdp macro
+.395256		08		php		                PHP
+.395257		c2 20		rep #$20	                REP #$20        ; set A long
+.395259		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39525c		5b		tcd		                TCD
+.39525d		28		plp		                PLP
+.39525e		68		pla		                PLA             ; end setdp macro
+.39525f		e2 20		sep #$20	                SEP #$20        ; set A short
+.395261		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS            ; Get the status to make sure a open is ok
+.395264		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395266		89 38		bit #$38	                BIT #FD_STAT_OPEN
+.395268		f0 05		beq $39526f	                BEQ ok_to_open
+.39526a		a9 0f		lda #$0f	                LDA #DOS_ERR_OPEN               ; If already open: throw an error
+.39526c		82 1c 05	brl $39578b	                BRL IF_FAILURE
+.39526f		22 8d 51 39	jsl $39518d	ok_to_open      JSL DOS_COPYPATH                ; Copy the path to the path buffer
+.395273		22 e8 47 39	jsl $3947e8	                JSL DOS_FINDFILE                ; Attempt to find the file
+.395277		b0 03		bcs $39527c	                BCS is_found                    ; If OK: we found the file
+.395279		82 13 05	brl $39578f	                BRL IF_PASSFAILURE              ; Otherwise: pass the failure up the chain
+.39527c						is_found
+.39527c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39527e		a0 01 00	ldy #$0001	                LDY #FILEDESC.DEV               ; Set the device in the file descriptor
+.395281		a5 01		lda $0321	                LDA BIOS_DEV
+.395283		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395285		c2 20		rep #$20	                REP #$20        ; set A long
+.395287		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER            ; Set the buffer point to the one provided in the file
+.39528a		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39528c		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.39528e		c8		iny		                INY
+.39528f		c8		iny		                INY
+.395290		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395292		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.395294		22 02 46 39	jsl $394602	                JSL DOS_GETCLUSTER              ; Attempt to load the cluster
+.395298		b0 03		bcs $39529d	                BCS read_cluster
+.39529a		82 f2 04	brl $39578f	                BRL IF_PASSFAILURE
+.39529d		a0 0a 00	ldy #$000a	read_cluster    LDY #FILEDESC.FIRST_CLUSTER     ; Set the first cluster in the file descriptor
+.3952a0		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3952a2		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952a4		c8		iny		                INY
+.3952a5		c8		iny		                INY
+.3952a6		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3952a8		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952aa		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Set the current cluster in the file descriptor
+.3952ad		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3952af		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952b1		c8		iny		                INY
+.3952b2		c8		iny		                INY
+.3952b3		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3952b5		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952b7		a0 1c 00	ldy #$001c	                LDY #DIRENTRY.SIZE              ; Copy the filesize from the directory entry to the file descriptor
+.3952ba		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.3952bc		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE
+.3952bf		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952c1		a0 1e 00	ldy #$001e	                LDY #DIRENTRY.SIZE+2
+.3952c4		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.3952c6		a0 14 00	ldy #$0014	                LDY #FILEDESC.SIZE+2
+.3952c9		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952cb		e2 20		sep #$20	                SEP #$20        ; set A short
+.3952cd		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS            ; Mark file as open and readable
+.3952d0		a9 39		lda #$39	                LDA #FD_STAT_OPEN | FD_STAT_READ
+.3952d2		17 20		ora [$0340],y	                ORA [DOS_FD_PTR],Y
+.3952d4		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3952d6		82 bd 04	brl $395796	                BRL IF_SUCCESS
+.3952d9						IF_CREATE
+.3952d9		da		phx		                PHX
+.3952da		5a		phy		                PHY
+.3952db		0b		phd		                PHD
+.3952dc		8b		phb		                PHB
+.3952dd		08		php		                PHP
+.3952de		48		pha		                PHA             ; begin setdbr macro
+.3952df		08		php		                PHP
+.3952e0		e2 20		sep #$20	                SEP #$20        ; set A short
+.3952e2		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3952e4		48		pha		                PHA
+.3952e5		ab		plb		                PLB
+.3952e6		28		plp		                PLP
+.3952e7		68		pla		                PLA             ; end setdbr macro
+.3952e8		48		pha		                PHA             ; begin setdp macro
+.3952e9		08		php		                PHP
+.3952ea		c2 20		rep #$20	                REP #$20        ; set A long
+.3952ec		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3952ef		5b		tcd		                TCD
+.3952f0		28		plp		                PLP
+.3952f1		68		pla		                PLA             ; end setdp macro
+.3952f2		22 60 50 39	jsl $395060	                JSL DOS_CREATE                  ; Attempt to create the file
+.3952f6		90 18		bcc $395310	                BCC pass_failure                ; If it fails: pass the failure up the chain
+.3952f8		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3952fa		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Sets the current cluster to 0 to make sure the next write appends
+.3952fd		a9 00 00	lda #$0000	                LDA #0
+.395300		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395302		c8		iny		                INY
+.395303		c8		iny		                INY
+.395304		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395306		e2 20		sep #$20	                SEP #$20        ; set A short
+.395308		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS
+.39530b		a9 3a		lda #$3a	                LDA #FD_STAT_OPEN | FD_STAT_WRITE   ; Set the file to open and APPEND only
+.39530d		82 86 04	brl $395796	                BRL IF_SUCCESS
+.395310		82 78 04	brl $39578b	pass_failure    BRL IF_FAILURE
+.395313						IF_CLOSE
+.395313		da		phx		                PHX
+.395314		5a		phy		                PHY
+.395315		0b		phd		                PHD
+.395316		8b		phb		                PHB
+.395317		08		php		                PHP
+.395318		48		pha		                PHA             ; begin setdbr macro
+.395319		08		php		                PHP
+.39531a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39531c		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.39531e		48		pha		                PHA
+.39531f		ab		plb		                PLB
+.395320		28		plp		                PLP
+.395321		68		pla		                PLA             ; end setdbr macro
+.395322		48		pha		                PHA             ; begin setdp macro
+.395323		08		php		                PHP
+.395324		c2 20		rep #$20	                REP #$20        ; set A long
+.395326		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395329		5b		tcd		                TCD
+.39532a		28		plp		                PLP
+.39532b		68		pla		                PLA             ; end setdp macro
+.39532c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39532e		a0 00 00	ldy #$0000	                LDY #FILEDESC.STATUS            ; Check to see if we were writing the file
+.395331		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395333		89 02		bit #$02	                BIT #FD_STAT_WRITE
+.395335		f0 09		beq $395340	                BEQ set_flag                    ; No, just mark it closed
+.395337		22 ac 53 39	jsl $3953ac	                JSL IF_WRITE                    ; Attempt to write the cluster
+.39533b		b0 03		bcs $395340	                BCS set_flag
+.39533d		82 4f 04	brl $39578f	                BRL IF_PASSFAILURE              ; If there was a problem, pass it up the chain
+.395340		22 90 58 39	jsl $395890	set_flag        JSL IF_FREEFD                   ; Free the file descriptor as well
+.395344		82 4f 04	brl $395796	                BRL IF_SUCCESS
+.395347						IF_READ
+.395347		da		phx		                PHX
+.395348		5a		phy		                PHY
+.395349		0b		phd		                PHD
+.39534a		8b		phb		                PHB
+.39534b		08		php		                PHP
+.39534c		48		pha		                PHA             ; begin setdbr macro
+.39534d		08		php		                PHP
+.39534e		e2 20		sep #$20	                SEP #$20        ; set A short
+.395350		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395352		48		pha		                PHA
+.395353		ab		plb		                PLB
+.395354		28		plp		                PLP
+.395355		68		pla		                PLA             ; end setdbr macro
+.395356		48		pha		                PHA             ; begin setdp macro
+.395357		08		php		                PHP
+.395358		c2 20		rep #$20	                REP #$20        ; set A long
+.39535a		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39535d		5b		tcd		                TCD
+.39535e		28		plp		                PLP
+.39535f		68		pla		                PLA             ; end setdp macro
+.395360		c2 10		rep #$10	                REP #$10        ; set X long
+.395362		e2 20		sep #$20	                SEP #$20        ; set A short
+.395364						get_dev
+.395364		e2 20		sep #$20	                SEP #$20        ; set A short
+.395366		a0 01 00	ldy #$0001	                LDY #FILEDESC.DEV               ; Get the device number from the file descriptor
+.395369		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39536b		85 01		sta $0321	                STA BIOS_DEV
+.39536d		22 6a 43 39	jsl $39436a	                JSL DOS_MOUNT                   ; Make sure the device is mounted (if needed)
+.395371		c2 20		rep #$20	                REP #$20        ; set A long
+.395373		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Get the file's current cluster
+.395376		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395378		85 10		sta $0330	                STA DOS_CLUS_ID
+.39537a		c8		iny		                INY
+.39537b		c8		iny		                INY
+.39537c		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39537e		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.395380		22 0d 4a 39	jsl $394a0d	                JSL NEXTCLUSTER                 ; Find the next cluster of the file
+.395384		90 13		bcc $395399	                BCC pass_failure                ; If not OK: pass the failure up the chain
+.395386		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER            ; Get the pointer to the file's cluster buffer
+.395389		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39538b		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.39538d		c8		iny		                INY
+.39538e		c8		iny		                INY
+.39538f		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395391		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.395393		22 02 46 39	jsl $394602	                JSL DOS_GETCLUSTER              ; Get the cluster
+.395397		b0 03		bcs $39539c	                BCS ret_success                 ; If ok: return success
+.395399						pass_failure
+.395399		82 f3 03	brl $39578f	                BRL IF_PASSFAILURE              ; Otherwise: bubble up the failure
+.39539c		a0 06 00	ldy #$0006	ret_success     LDY #FILEDESC.CLUSTER           ; Save the new cluster as the file's current cluster
+.39539f		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3953a1		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3953a3		c8		iny		                INY
+.3953a4		c8		iny		                INY
+.3953a5		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.3953a7		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.3953a9		82 ea 03	brl $395796	                BRL IF_SUCCESS
+.3953ac						IF_WRITE
+.3953ac		da		phx		                PHX
+.3953ad		5a		phy		                PHY
+.3953ae		0b		phd		                PHD
+.3953af		8b		phb		                PHB
+.3953b0		08		php		                PHP
+.3953b1		48		pha		                PHA             ; begin setdbr macro
+.3953b2		08		php		                PHP
+.3953b3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3953b5		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3953b7		48		pha		                PHA
+.3953b8		ab		plb		                PLB
+.3953b9		28		plp		                PLP
+.3953ba		68		pla		                PLA             ; end setdbr macro
+.3953bb		48		pha		                PHA             ; begin setdp macro
+.3953bc		08		php		                PHP
+.3953bd		c2 20		rep #$20	                REP #$20        ; set A long
+.3953bf		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3953c2		5b		tcd		                TCD
+.3953c3		28		plp		                PLP
+.3953c4		68		pla		                PLA             ; end setdp macro
+.3953c5		c2 10		rep #$10	                REP #$10        ; set X long
+.3953c7		e2 20		sep #$20	                SEP #$20        ; set A short
+.3953c9		a0 01 00	ldy #$0001	get_dev         LDY #FILEDESC.DEV               ; Get the device number from the file descriptor
+.3953cc		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3953ce		85 01		sta $0321	                STA BIOS_DEV
+.3953d0		22 6a 43 39	jsl $39436a	                JSL DOS_MOUNT                   ; Make sure the device is mounted (if needed)
+.3953d4		c2 20		rep #$20	                REP #$20        ; set A long
+.3953d6		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER            ; Get the pointer to the file's cluster buffer
+.3953d9		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3953db		85 1c		sta $033c	                STA DOS_BUFF_PTR
+.3953dd		c8		iny		                INY
+.3953de		c8		iny		                INY
+.3953df		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3953e1		85 1e		sta $033e	                STA DOS_BUFF_PTR+2
+.3953e3		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; Get the file's current cluster
+.3953e6		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3953e8		85 10		sta $0330	                STA DOS_CLUS_ID
+.3953ea		c8		iny		                INY
+.3953eb		c8		iny		                INY
+.3953ec		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3953ee		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.3953f0		d0 1a		bne $39540c	                BNE rewrite_cluster             ; If the cluster ID <> 0, overwrite it
+.3953f2		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.3953f4		d0 16		bne $39540c	                BNE rewrite_cluster
+.3953f6		a0 0a 00	ldy #$000a	                LDY #FILEDESC.FIRST_CLUSTER     ; Get the file's first cluster
+.3953f9		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3953fb		85 10		sta $0330	                STA DOS_CLUS_ID
+.3953fd		c8		iny		                INY
+.3953fe		c8		iny		                INY
+.3953ff		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395401		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.395403		22 2e 4e 39	jsl $394e2e	                JSL DOS_APPENDCLUS              ; Append the cluster
+.395407		b0 0c		bcs $395415	                BCS ret_success                 ; If OK: return success
+.395409		82 83 03	brl $39578f	                BRL IF_PASSFAILURE              ; Otherwise: bubble up the failure
+.39540c		22 3f 46 39	jsl $39463f	rewrite_cluster JSL DOS_PUTCLUSTER              ; Over-write the cluster
+.395410		b0 03		bcs $395415	                BCS ret_success                 ; If ok: return success
+.395412		82 7a 03	brl $39578f	pass_failure    BRL IF_PASSFAILURE              ; Otherwise: bubble up the failure
+.395415		82 7e 03	brl $395796	ret_success     BRL IF_SUCCESS
+.395418						IF_DIROPEN
+.395418		da		phx		                PHX
+.395419		5a		phy		                PHY
+.39541a		0b		phd		                PHD
+.39541b		8b		phb		                PHB
+.39541c		08		php		                PHP
+.39541d		48		pha		                PHA             ; begin setdbr macro
+.39541e		08		php		                PHP
+.39541f		e2 20		sep #$20	                SEP #$20        ; set A short
+.395421		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395423		48		pha		                PHA
+.395424		ab		plb		                PLB
+.395425		28		plp		                PLP
+.395426		68		pla		                PLA             ; end setdbr macro
+.395427		48		pha		                PHA             ; begin setdp macro
+.395428		08		php		                PHP
+.395429		c2 20		rep #$20	                REP #$20        ; set A long
+.39542b		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39542e		5b		tcd		                TCD
+.39542f		28		plp		                PLP
+.395430		68		pla		                PLA             ; end setdp macro
+.395431		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395433		22 8d 51 39	jsl $39518d	                JSL DOS_COPYPATH            ; Copy the path from the file descriptor to the path buffer
+.395437		22 50 47 39	jsl $394750	                JSL DOS_PARSE_PATH          ; Parse the path
+.39543b		22 6a 43 39	jsl $39436a	                JSL DOS_MOUNT               ; Make sure we've mounted the SDC.
+.39543f		b0 03		bcs $395444	                BCS get_root_dir            ; If successful: get the root directory
+.395441		82 4b 03	brl $39578f	                BRL IF_PASSFAILURE          ; Otherwise: pass the error up the chain
+.395444						get_root_dir
+.395444		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395446		22 1f 40 39	jsl $39401f	                JSL DOS_DIROPEN
+.39544a		b0 03		bcs $39544f	                BCS success
+.39544c		82 40 03	brl $39578f	                BRL IF_PASSFAILURE
+.39544f		82 44 03	brl $395796	success         BRL IF_SUCCESS
+.395452						IF_DIRNEXT
+.395452		5c b9 40 39	jmp $3940b9	                JML DOS_DIRNEXT
+.395456						IF_DELETE
+.395456		da		phx		                PHX
+.395457		5a		phy		                PHY
+.395458		0b		phd		                PHD
+.395459		8b		phb		                PHB
+.39545a		08		php		                PHP
+.39545b		48		pha		                PHA             ; begin setdbr macro
+.39545c		08		php		                PHP
+.39545d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39545f		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395461		48		pha		                PHA
+.395462		ab		plb		                PLB
+.395463		28		plp		                PLP
+.395464		68		pla		                PLA             ; end setdbr macro
+.395465		48		pha		                PHA             ; begin setdp macro
+.395466		08		php		                PHP
+.395467		c2 20		rep #$20	                REP #$20        ; set A long
+.395469		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.39546c		5b		tcd		                TCD
+.39546d		28		plp		                PLP
+.39546e		68		pla		                PLA             ; end setdp macro
+.39546f		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395471		22 e8 47 39	jsl $3947e8	                JSL DOS_FINDFILE
+.395475		b0 03		bcs $39547a	                BCS get_first_clus
+.395477		82 15 03	brl $39578f	                BRL IF_PASSFAILURE
+.39547a						get_first_clus
+.39547a		a0 1a 00	ldy #$001a	                LDY #DIRENTRY.CLUSTER_L
+.39547d		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.39547f		85 10		sta $0330	                STA DOS_CLUS_ID
+.395481		a0 14 00	ldy #$0014	                LDY #DIRENTRY.CLUSTER_H
+.395484		b7 18		lda [$0338],y	                LDA [DOS_DIR_PTR],Y
+.395486		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.395488		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.39548a		8d 2a a0	sta $38a02a	                STA DOS_CURR_CLUS
+.39548d		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.39548f		8d 2c a0	sta $38a02c	                STA DOS_CURR_CLUS+2
+.395492		22 0d 4a 39	jsl $394a0d	del_loop        JSL NEXTCLUSTER
+.395496		90 2f		bcc $3954c7	                BCC del_one
+.395498		a5 10		lda $0330	                LDA DOS_CLUS_ID
+.39549a		8d 2e a0	sta $38a02e	                STA DOS_NEXT_CLUS
+.39549d		a5 12		lda $0332	                LDA DOS_CLUS_ID+2
+.39549f		8d 30 a0	sta $38a030	                STA DOS_NEXT_CLUS+2
+.3954a2		ad 2a a0	lda $38a02a	                LDA DOS_CURR_CLUS
+.3954a5		85 10		sta $0330	                STA DOS_CLUS_ID
+.3954a7		ad 2c a0	lda $38a02c	                LDA DOS_CURR_CLUS+2
+.3954aa		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.3954ac		22 ee 4d 39	jsl $394dee	                JSL DELCLUSTER32
+.3954b0		b0 03		bcs $3954b5	                BCS go_next
+.3954b2		82 da 02	brl $39578f	                BRL IF_PASSFAILURE
+.3954b5						go_next
+.3954b5		ad 2e a0	lda $38a02e	                LDA DOS_NEXT_CLUS
+.3954b8		85 10		sta $0330	                STA DOS_CLUS_ID
+.3954ba		8d 2a a0	sta $38a02a	                STA DOS_CURR_CLUS
+.3954bd		ad 30 a0	lda $38a030	                LDA DOS_NEXT_CLUS+2
+.3954c0		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.3954c2		8d 2c a0	sta $38a02c	                STA DOS_CURR_CLUS+2
+.3954c5		80 cb		bra $395492	                BRA del_loop
+.3954c7						del_one
+.3954c7		ad 2a a0	lda $38a02a	                LDA DOS_CURR_CLUS
+.3954ca		85 10		sta $0330	                STA DOS_CLUS_ID
+.3954cc		ad 2c a0	lda $38a02c	                LDA DOS_CURR_CLUS+2
+.3954cf		85 12		sta $0332	                STA DOS_CLUS_ID+2
+.3954d1		22 48 4d 39	jsl $394d48	                JSL DELCLUSTER
+.3954d5		b0 03		bcs $3954da	                BCS free_dir_entry
+.3954d7		82 b5 02	brl $39578f	                BRL IF_PASSFAILURE
+.3954da						free_dir_entry
+.3954da		e2 20		sep #$20	                SEP #$20        ; set A short
+.3954dc		a0 00 00	ldy #$0000	                LDY #DIRENTRY.SHORTNAME         ; Flag the directory entry as deleted
+.3954df		a9 e5		lda #$e5	                LDA #DOS_DIR_ENT_UNUSED
+.3954e1		97 18		sta [$0338],y	                STA [DOS_DIR_PTR],Y
+.3954e3		22 38 42 39	jsl $394238	                JSL DOS_DIRWRITE                ; Write the directory entry back
+.3954e7		b0 03		bcs $3954ec	                BCS ret_success
+.3954e9		82 a3 02	brl $39578f	                BRL IF_PASSFAILURE
+.3954ec		82 a7 02	brl $395796	ret_success     BRL IF_SUCCESS
+.3954ef						IF_DIRREAD
+.3954ef		da		phx		                PHX
+.3954f0		5a		phy		                PHY
+.3954f1		0b		phd		                PHD
+.3954f2		8b		phb		                PHB
+.3954f3		08		php		                PHP
+.3954f4		48		pha		                PHA             ; begin setdbr macro
+.3954f5		08		php		                PHP
+.3954f6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3954f8		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3954fa		48		pha		                PHA
+.3954fb		ab		plb		                PLB
+.3954fc		28		plp		                PLP
+.3954fd		68		pla		                PLA             ; end setdbr macro
+.3954fe		48		pha		                PHA             ; begin setdp macro
+.3954ff		08		php		                PHP
+.395500		c2 20		rep #$20	                REP #$20        ; set A long
+.395502		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395505		5b		tcd		                TCD
+.395506		28		plp		                PLP
+.395507		68		pla		                PLA             ; end setdp macro
+.395508		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39550a		22 e8 47 39	jsl $3947e8	                JSL DOS_FINDFILE
+.39550e		b0 03		bcs $395513	                BCS success
+.395510		82 78 02	brl $39578b	                BRL IF_FAILURE
+.395513		82 80 02	brl $395796	success         BRL IF_SUCCESS
+.395516						IF_DIRWRITE
+.395516		5c 38 42 39	jmp $394238	                JML DOS_DIRWRITE
+.39551a						IF_LOAD
+.39551a		da		phx		                PHX
+.39551b		5a		phy		                PHY
+.39551c		0b		phd		                PHD
+.39551d		8b		phb		                PHB
+.39551e		08		php		                PHP
+.39551f		48		pha		                PHA             ; begin setdbr macro
+.395520		08		php		                PHP
+.395521		e2 20		sep #$20	                SEP #$20        ; set A short
+.395523		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395525		48		pha		                PHA
+.395526		ab		plb		                PLB
+.395527		28		plp		                PLP
+.395528		68		pla		                PLA             ; end setdbr macro
+.395529		48		pha		                PHA             ; begin setdp macro
+.39552a		08		php		                PHP
+.39552b		c2 20		rep #$20	                REP #$20        ; set A long
+.39552d		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395530		5b		tcd		                TCD
+.395531		28		plp		                PLP
+.395532		68		pla		                PLA             ; end setdp macro
+.395533		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395535		22 46 52 39	jsl $395246	                JSL IF_OPEN
+.395539		b0 03		bcs $39553e	                BCS setup                   ; If success: start setting things up
+.39553b		82 51 02	brl $39578f	                BRL IF_PASSFAILURE          ; Otherwise: pass the failure up the chain
+.39553e						setup
+.39553e		c2 20		rep #$20	                REP #$20        ; set A long
+.395540		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE          ; Record the size of the file in DOS_FILE_SIZE
+.395543		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395545		85 2c		sta $034c	                STA DOS_FILE_SIZE
+.395547		c8		iny		                INY
+.395548		c8		iny		                INY
+.395549		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39554b		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
+.39554d		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER        ; Set up the source pointer
+.395550		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395552		85 30		sta $0350	                STA DOS_SRC_PTR
+.395554		c8		iny		                INY
+.395555		c8		iny		                INY
+.395556		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395558		85 32		sta $0352	                STA DOS_SRC_PTR+2
+.39555a		a5 36		lda $0356	                LDA DOS_DST_PTR+2           ; Is there a destination address in RAM?
+.39555c		c9 40 00	cmp #$0040	                CMP #$0040
+.39555f		b0 04		bcs $395565	                BGE load_by_type            ; No: try to load it by type
+.395561		5c 40 56 39	jmp $395640	                JML IF_LOADRAW              ; Otherwise, load it to the supplied destination
+.395565		a0 08 00	ldy #$0008	load_by_type    LDY #8                      ; Point to the first extension byte
+.395568		a2 00 00	ldx #$0000	                LDX #0                      ; and the first byte of the table
+.39556b						type_loop
+.39556b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39556d		bf b1 55 39	lda $3955b1,x	                LDA LOAD_TYPE_TABLE,X       ; Get 1st extension character of the entry
+.395571		f0 37		beq $3955aa	                BEQ no_match                ; If NULL... we didn't get a match
+.395573		d9 3a a0	cmp $38a03a,y	                CMP DOS_SHORT_NAME,Y        ; Get the character of the extension
+.395576		d0 28		bne $3955a0	                BNE next_entry              ; If they don't match, try the next entry
+.395578		bf b2 55 39	lda $3955b2,x	                LDA LOAD_TYPE_TABLE+1,X     ; Get 2nd extension character of the entry
+.39557c		d9 3b a0	cmp $38a03b,y	                CMP DOS_SHORT_NAME+1,Y      ; Get the 2nd character of the extension
+.39557f		d0 1f		bne $3955a0	                BNE next_entry              ; If they don't match, try the next entry
+.395581		bf b3 55 39	lda $3955b3,x	                LDA LOAD_TYPE_TABLE+2,X     ; Get 3rd extension character of the entry
+.395585		d9 3c a0	cmp $38a03c,y	                CMP DOS_SHORT_NAME+2,Y      ; Get the 3rd character of the extension
+.395588		d0 16		bne $3955a0	                BNE next_entry              ; If they don't match, try the next entry
+.39558a		c2 20		rep #$20	                REP #$20        ; set A long
+.39558c		bf b4 55 39	lda $3955b4,x	                LDA LOAD_TYPE_TABLE+3,X     ; Get the low word of the address
+.395590		85 28		sta $0348	                STA DOS_TEMP                ; Save it to the jump vector
+.395592		e2 20		sep #$20	                SEP #$20        ; set A short
+.395594		bf b6 55 39	lda $3955b6,x	                LDA LOAD_TYPE_TABLE+5,X     ; Get the high byte of the address
+.395598		85 2a		sta $034a	                STA DOS_TEMP+2              ; Save it to the jump vector
+.39559a		a2 00 00	ldx #$0000	                LDX #0
+.39559d		dc 48 03	jmp [$0348]	                JML [DOS_TEMP]              ; Jump to the loading routine
+.3955a0						next_entry
+.3955a0		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3955a2		8a		txa		                TXA
+.3955a3		18		clc		                CLC
+.3955a4		69 06 00	adc #$0006	                ADC #6
+.3955a7		aa		tax		                TAX
+.3955a8		80 c1		bra $39556b	                BRA type_loop               ; And check it against the file
+.3955aa						no_match
+.3955aa		e2 20		sep #$20	                SEP #$20        ; set A short
+.3955ac		a9 11		lda #$11	                LDA #DOS_ERR_NOEXEC         ; Return an not-executable error
+.3955ae		82 da 01	brl $39578b	                BRL IF_FAILURE
+>3955b1		50 47 58			LOAD_TYPE_TABLE .text "PGX"                 ; "PGX" --> IF_LOADPGX
+>3955b4		b8 55				                .word <>IF_LOADPGX
+>3955b6		39				                .byte `IF_LOADPGX
+>3955b7		00				                .byte 0
+.3955b8						IF_LOADPGX
+.3955b8		c2 10		rep #$10	                REP #$10        ; set X long
+.3955ba		e2 20		sep #$20	                SEP #$20        ; set A short
+.3955bc		a0 00 00	ldy #$0000	                LDY #0
+.3955bf		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Check for "PGX" signature
+.3955c1		c9 50		cmp #$50	                CMP #'P'
+.3955c3		d0 15		bne $3955da	                BNE fail_sig                        ; If not found, fail
+.3955c5		c8		iny		                INY
+.3955c6		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
+.3955c8		c9 47		cmp #$47	                CMP #'G'
+.3955ca		d0 0e		bne $3955da	                BNE fail_sig
+.3955cc		c8		iny		                INY
+.3955cd		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
+.3955cf		c9 58		cmp #$58	                CMP #'X'
+.3955d1		d0 07		bne $3955da	                BNE fail_sig
+.3955d3		c8		iny		                INY                                 ; Check for CPU and version code ($01 for 65816)
+.3955d4		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
+.3955d6		c9 01		cmp #$01	                CMP #$01
+.3955d8		f0 17		beq $3955f1	                BEQ get_dest                        ; All passes: go to get the destination address
+.3955da		a9 10		lda #$10	fail_sig        LDA #DOS_ERR_PGXSIG                 ; Fail with a PGXSIG error code
+.3955dc		22 8b 57 39	jsl $39578b	                JSL IF_FAILURE
+.3955e0						adjust_size
+.3955e0		c2 20		rep #$20	                REP #$20        ; set A long
+.3955e2		38		sec		                SEC                                 ; Subtract the 8 bytes of the header from the file size
+.3955e3		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
+.3955e5		e9 08 00	sbc #$0008	                SBC #8
+.3955e8		85 2c		sta $034c	                STA DOS_FILE_SIZE
+.3955ea		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
+.3955ec		e9 00 00	sbc #$0000	                SBC #0
+.3955ef		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
+.3955f1						get_dest
+.3955f1		c2 20		rep #$20	                REP #$20        ; set A long
+.3955f3		c8		iny		                INY
+.3955f4		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Get low word of destination address
+.3955f6		85 34		sta $0354	                STA DOS_DST_PTR                     ; And save it to the destination pointer
+.3955f8		85 3c		sta $035c	                STA DOS_RUN_PTR                     ; And save it to the RUN pointer
+.3955fa		c8		iny		                INY
+.3955fb		c8		iny		                INY
+.3955fc		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Get high word of destination address
+.3955fe		85 36		sta $0356	                STA DOS_DST_PTR+2
+.395600		85 3e		sta $035e	                STA DOS_RUN_PTR+2
+.395602		c8		iny		                INY                                 ; Point to the first data byte
+.395603		c8		iny		                INY
+.395604						copy_loop
+.395604		e2 20		sep #$20	                SEP #$20        ; set A short
+.395606		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y                 ; Read a byte from the file
+.395608		87 34		sta [$0354]	                STA [DOS_DST_PTR]                   ; Write it to the destination
+.39560a		c2 20		rep #$20	                REP #$20        ; set A long
+.39560c		e6 34		inc $0354	                INC DOS_DST_PTR                     ; Move to the next destination location
+.39560e		d0 02		bne $395612	                BNE dec_file_size
+.395610		e6 36		inc $0356	                INC DOS_DST_PTR+2
+.395612		38		sec		dec_file_size   SEC                                 ; Count down the number of bytes to read
+.395613		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
+.395615		e9 01 00	sbc #$0001	                SBC #1
+.395618		85 2c		sta $034c	                STA DOS_FILE_SIZE
+.39561a		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
+.39561c		e9 00 00	sbc #$0000	                SBC #0
+.39561f		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
+.395621		a5 2c		lda $034c	                LDA DOS_FILE_SIZE                   ; Are we at the end of the file?
+.395623		d0 04		bne $395629	                BNE next_byte
+.395625		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
+.395627		f0 14		beq $39563d	                BEQ done                            ; Yes: we're done
+.395629		c8		iny		next_byte       INY                                 ; Otherwise, move to the next source location
+.39562a		cc 0e a0	cpy $38a00e	                CPY CLUSTER_SIZE                    ; Are we at the end of the cluster?
+.39562d		d0 d5		bne $395604	                BNE copy_loop                       ; No: keep copying
+.39562f		22 11 4b 39	jsl $394b11	                JSL DOS_READNEXT                    ; Yes: Load the next cluster
+.395633		b0 03		bcs $395638	                BCS next_cluster
+.395635		82 57 01	brl $39578f	                BRL IF_PASSFAILURE                  ; If failed: pass that up the chain
+.395638		a0 00 00	ldy #$0000	next_cluster    LDY #0
+.39563b		80 c7		bra $395604	                BRA copy_loop                       ; Go back to copying
+.39563d		82 56 01	brl $395796	done            BRL IF_SUCCESS
+.395640						IF_LOADRAW
+.395640		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395642		a0 00 00	ldy #$0000	copy_cluster    LDY #0
+.395645						copy_loop
+.395645		e2 20		sep #$20	                SEP #$20        ; set A short
+.395647		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y         ; Copy byte from cluster to destination
+.395649		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.39564b		c2 20		rep #$20	                REP #$20        ; set A long
+.39564d		38		sec		                SEC                         ; Count down the number of bytes left
+.39564e		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
+.395650		e9 01 00	sbc #$0001	                SBC #1
+.395653		85 2c		sta $034c	                STA DOS_FILE_SIZE
+.395655		a5 2e		lda $034e	                LDA DOS_FILE_SIZE+2
+.395657		e9 00 00	sbc #$0000	                SBC #0
+.39565a		85 2e		sta $034e	                STA DOS_FILE_SIZE+2
+.39565c		d0 04		bne $395662	                BNE continue
+.39565e		a5 2c		lda $034c	                LDA DOS_FILE_SIZE
+.395660		f0 1b		beq $39567d	                BEQ close_file              ; If not: we're done
+.395662		c8		iny		continue        INY
+.395663		cc 0e a0	cpy $38a00e	                CPY CLUSTER_SIZE            ; Are we done with the cluster?
+.395666		d0 dd		bne $395645	                BNE copy_loop               ; No: keep processing the bytes
+.395668		18		clc		                CLC                         ; Advance the destination pointer to the next chunk of memory
+.395669		a5 34		lda $0354	                LDA DOS_DST_PTR
+.39566b		6d 0e a0	adc $38a00e	                ADC CLUSTER_SIZE
+.39566e		85 34		sta $0354	                STA DOS_DST_PTR
+.395670		a5 36		lda $0356	                LDA DOS_DST_PTR+2
+.395672		69 00 00	adc #$0000	                ADC #0
+.395675		85 36		sta $0356	                STA DOS_DST_PTR+2
+.395677		22 47 53 39	jsl $395347	                JSL IF_READ                 ; Yes: load the next cluster
+.39567b		b0 c5		bcs $395642	                BCS copy_cluster            ; And start copying it
+.39567d						close_file
+.39567d		82 16 01	brl $395796	ret_success     BRL IF_SUCCESS
+.395680						IF_NULLBUFFER
+.395680		5a		phy		                PHY
+.395681		8b		phb		                PHB
+.395682		0b		phd		                PHD
+.395683		08		php		                PHP
+.395684		48		pha		                PHA             ; begin setdbr macro
+.395685		08		php		                PHP
+.395686		e2 20		sep #$20	                SEP #$20        ; set A short
+.395688		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.39568a		48		pha		                PHA
+.39568b		ab		plb		                PLB
+.39568c		28		plp		                PLP
+.39568d		68		pla		                PLA             ; end setdbr macro
+.39568e		48		pha		                PHA             ; begin setdp macro
+.39568f		08		php		                PHP
+.395690		c2 20		rep #$20	                REP #$20        ; set A long
+.395692		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395695		5b		tcd		                TCD
+.395696		28		plp		                PLP
+.395697		68		pla		                PLA             ; end setdp macro
+.395698		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39569a		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER
+.39569d		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39569f		85 28		sta $0348	                STA DOS_TEMP
+.3956a1		c8		iny		                INY
+.3956a2		c8		iny		                INY
+.3956a3		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3956a5		85 2a		sta $034a	                STA DOS_TEMP+2
+.3956a7		a0 00 00	ldy #$0000	                LDY #0
+.3956aa		a9 00 00	lda #$0000	                LDA #0
+.3956ad		97 28		sta [$0348],y	loop            STA [DOS_TEMP],Y
+.3956af		c8		iny		                INY
+.3956b0		c8		iny		                INY
+.3956b1		c0 00 02	cpy #$0200	                CPY #DOS_SECTOR_SIZE
+.3956b4		d0 f7		bne $3956ad	                BNE loop
+.3956b6		28		plp		                PLP
+.3956b7		2b		pld		                PLD
+.3956b8		ab		plb		                PLB
+.3956b9		7a		ply		                PLY
+.3956ba		6b		rtl		                RTL
+.3956bb						IF_COPY2BUFF
+.3956bb		5a		phy		                PHY
+.3956bc		8b		phb		                PHB
+.3956bd		0b		phd		                PHD
+.3956be		08		php		                PHP
+.3956bf		48		pha		                PHA             ; begin setdbr macro
+.3956c0		08		php		                PHP
+.3956c1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3956c3		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.3956c5		48		pha		                PHA
+.3956c6		ab		plb		                PLB
+.3956c7		28		plp		                PLP
+.3956c8		68		pla		                PLA             ; end setdbr macro
+.3956c9		48		pha		                PHA             ; begin setdp macro
+.3956ca		08		php		                PHP
+.3956cb		c2 20		rep #$20	                REP #$20        ; set A long
+.3956cd		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3956d0		5b		tcd		                TCD
+.3956d1		28		plp		                PLP
+.3956d2		68		pla		                PLA             ; end setdp macro
+.3956d3		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3956d5		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER
+.3956d8		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3956da		85 28		sta $0348	                STA DOS_TEMP
+.3956dc		c8		iny		                INY
+.3956dd		c8		iny		                INY
+.3956de		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.3956e0		85 2a		sta $034a	                STA DOS_TEMP+2
+.3956e2		a0 00 00	ldy #$0000	                LDY #0
+.3956e5						copy_loop
+.3956e5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3956e7		a7 30		lda [$0350]	                LDA [DOS_SRC_PTR]           ; Copy a byte
+.3956e9		97 28		sta [$0348],y	                STA [DOS_TEMP],Y
+.3956eb		c2 20		rep #$20	                REP #$20        ; set A long
+.3956ed		e6 30		inc $0350	                INC DOS_SRC_PTR             ; Advance the source pointer
+.3956ef		d0 02		bne $3956f3	                BNE adv_dest
+.3956f1		e6 32		inc $0352	                INC DOS_SRC_PTR+2
+.3956f3		c8		iny		adv_dest        INY                         ; Count it
+.3956f4		c0 00 02	cpy #$0200	                CPY #DOS_SECTOR_SIZE        ; Have we reached the limit?
+.3956f7		f0 0c		beq $395705	                BEQ done                    ; Yes: we're done
+.3956f9		a5 30		lda $0350	                LDA DOS_SRC_PTR             ; Check if we copied the last byte
+.3956fb		c5 38		cmp $0358	                CMP DOS_END_PTR
+.3956fd		d0 e6		bne $3956e5	                BNE copy_loop               ; No: keep copying
+.3956ff		a5 32		lda $0352	                LDA DOS_SRC_PTR+2
+.395701		c5 3a		cmp $035a	                CMP DOS_END_PTR+2
+.395703		d0 e0		bne $3956e5	                BNE copy_loop
+.395705		28		plp		done            PLP
+.395706		2b		pld		                PLD
+.395707		ab		plb		                PLB
+.395708		7a		ply		                PLY
+.395709		6b		rtl		                RTL
+.39570a						IF_SAVE
+.39570a		da		phx		                PHX
+.39570b		5a		phy		                PHY
+.39570c		0b		phd		                PHD
+.39570d		8b		phb		                PHB
+.39570e		08		php		                PHP
+.39570f		48		pha		                PHA             ; begin setdbr macro
+.395710		08		php		                PHP
+.395711		e2 20		sep #$20	                SEP #$20        ; set A short
+.395713		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395715		48		pha		                PHA
+.395716		ab		plb		                PLB
+.395717		28		plp		                PLP
+.395718		68		pla		                PLA             ; end setdbr macro
+.395719		48		pha		                PHA             ; begin setdp macro
+.39571a		08		php		                PHP
+.39571b		c2 20		rep #$20	                REP #$20        ; set A long
+.39571d		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395720		5b		tcd		                TCD
+.395721		28		plp		                PLP
+.395722		68		pla		                PLA             ; end setdp macro
+.395723		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395725		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE      ; DOS_FD_PTR->SIZE := DOS_END_PTR - DOS_SRC_PTR
+.395728		38		sec		                SEC
+.395729		a5 38		lda $0358	                LDA DOS_END_PTR
+.39572b		e5 30		sbc $0350	                SBC DOS_SRC_PTR
+.39572d		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39572f		c8		iny		                INY
+.395730		c8		iny		                INY
+.395731		a5 3a		lda $035a	                LDA DOS_END_PTR+2
+.395733		e5 32		sbc $0352	                SBC DOS_SRC_PTR+2
+.395735		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395737		a0 12 00	ldy #$0012	                LDY #FILEDESC.SIZE      ; DOS_FD_PTR->SIZE++
+.39573a		18		clc		                CLC
+.39573b		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.39573d		69 01 00	adc #$0001	                ADC #1
+.395740		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395742		90 09		bcc $39574d	                BCC first_block
+.395744		c8		iny		                INY
+.395745		c8		iny		                INY
+.395746		b7 20		lda [$0340],y	                LDA [DOS_FD_PTR],Y
+.395748		69 00 00	adc #$0000	                ADC #0
+.39574b		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39574d		22 80 56 39	jsl $395680	first_block     JSL IF_NULLBUFFER       ; Fill FD buffer with NULL
+.395751		22 bb 56 39	jsl $3956bb	                JSL IF_COPY2BUFF        ; Copy first (at most) 512 bytes of data to FD buffer
+.395755		22 d9 52 39	jsl $3952d9	                JSL IF_CREATE           ; Create file.
+.395759		b0 03		bcs $39575e	                BCS check_for_end
+.39575b		82 31 00	brl $39578f	                BRL IF_PASSFAILURE      ; If we couldn't create the file, pass the failure up
+.39575e		a5 30		lda $0350	check_for_end   LDA DOS_SRC_PTR         ; Check if we copied the last byte
+.395760		c5 38		cmp $0358	                CMP DOS_END_PTR
+.395762		d0 06		bne $39576a	                BNE next_block
+.395764		a5 32		lda $0352	                LDA DOS_SRC_PTR+2
+.395766		c5 3a		cmp $035a	                CMP DOS_END_PTR+2
+.395768		f0 1d		beq $395787	                BEQ done                ; Yes: we're done
+.39576a		22 80 56 39	jsl $395680	next_block      JSL IF_NULLBUFFER       ; Fill FD buffer with NULL
+.39576e		22 bb 56 39	jsl $3956bb	                JSL IF_COPY2BUFF        ; Copy next (at most) 512 bytes of data to FD buffer
+.395772		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER   ; Make sure the CLUSTER is 0 to force an append
+.395775		a9 00 00	lda #$0000	                LDA #0
+.395778		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39577a		c8		iny		                INY
+.39577b		c8		iny		                INY
+.39577c		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39577e		22 ac 53 39	jsl $3953ac	                JSL IF_WRITE            ; Append to the file
+.395782		b0 da		bcs $39575e	                BCS check_for_end       ; And try again
+.395784		82 08 00	brl $39578f	                BRL IF_PASSFAILURE      ; If we couldn't update the file, pass the failure up
+.395787		5c 96 57 39	jmp $395796	done            JML IF_SUCCESS
+.39578b						IF_FAILURE
+.39578b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39578d		85 0e		sta $032e	                STA DOS_STATUS
+.39578f		28		plp		IF_PASSFAILURE  PLP
+.395790		18		clc		                CLC
+.395791		ab		plb		                PLB
+.395792		2b		pld		                PLD
+.395793		7a		ply		                PLY
+.395794		fa		plx		                PLX
+.395795		6b		rtl		                RTL
+.395796						IF_SUCCESS
+.395796		e2 20		sep #$20	                SEP #$20        ; set A short
+.395798		64 00		stz $0320	                STZ BIOS_STATUS
+.39579a		64 0e		stz $032e	                STZ DOS_STATUS
+.39579c		28		plp		                PLP
+.39579d		38		sec		                SEC
+.39579e		ab		plb		                PLB
+.39579f		2b		pld		                PLD
+.3957a0		7a		ply		                PLY
+.3957a1		fa		plx		                PLX
+.3957a2		6b		rtl		                RTL
+.3957a3						IF_RUN
+.3957a3		da		phx		                PHX
+.3957a4		5a		phy		                PHY
+.3957a5		0b		phd		                PHD
+.3957a6		8b		phb		                PHB
+.3957a7		08		php		                PHP
+.3957a8		48		pha		                PHA             ; begin setdbr macro
+.3957a9		08		php		                PHP
+.3957aa		e2 20		sep #$20	                SEP #$20        ; set A short
+.3957ac		a9 00		lda #$00	                LDA #0
+.3957ae		48		pha		                PHA
+.3957af		ab		plb		                PLB
+.3957b0		28		plp		                PLP
+.3957b1		68		pla		                PLA             ; end setdbr macro
+.3957b2		48		pha		                PHA             ; begin setdp macro
+.3957b3		08		php		                PHP
+.3957b4		c2 20		rep #$20	                REP #$20        ; set A long
+.3957b6		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3957b9		5b		tcd		                TCD
+.3957ba		28		plp		                PLP
+.3957bb		68		pla		                PLA             ; end setdp macro
+.3957bc		e2 20		sep #$20	                SEP #$20        ; set A short
+.3957be		c2 10		rep #$10	                REP #$10        ; set X long
+.3957c0		a9 00		lda #$00	                LDA #0                                  ; Zero out the file descriptor
+.3957c2		a2 00 00	ldx #$0000	                LDX #0
+.3957c5		9f 00 ad 38	sta $38ad00,x	clr_fd_loop     STA @l DOS_SPARE_FD,X
+.3957c9		e8		inx		                INX
+.3957ca		e0 20 00	cpx #$0020	                CPX #SIZE(FILEDESC)
+.3957cd		d0 f6		bne $3957c5	                BNE clr_fd_loop
+.3957cf		c2 20		rep #$20	                REP #$20        ; set A long
+.3957d1		a9 00 ab	lda #$ab00	                LDA #<>DOS_SPARE_SECTOR                 ; Set the buffer for the file descriptor
+.3957d4		8f 0e ad 38	sta $38ad0e	                STA @l DOS_SPARE_FD+FILEDESC.BUFFER
+.3957d8		a9 38 00	lda #$0038	                LDA #`DOS_SPARE_SECTOR
+.3957db		8f 10 ad 38	sta $38ad10	                STA @l DOS_SPARE_FD+FILEDESC.BUFFER+2
+.3957df		a5 40		lda $0360	                LDA DOS_RUN_PARAM                        ; Set the path for the file descriptor
+.3957e1		8f 02 ad 38	sta $38ad02	                STA @l DOS_SPARE_FD+FILEDESC.PATH
+.3957e5		a5 42		lda $0362	                LDA DOS_RUN_PARAM+2
+.3957e7		8f 04 ad 38	sta $38ad04	                STA @l DOS_SPARE_FD+FILEDESC.PATH+2
+.3957eb		a9 00 00	lda #$0000	                LDA #0                                  ; Clear the run pointer
+.3957ee		85 3c		sta $035c	                STA DOS_RUN_PTR                         ; This is used to check that we loaded an executable binary
+.3957f0		85 3e		sta $035e	                STA DOS_RUN_PTR+2
+.3957f2		a9 00 ad	lda #$ad00	                LDA #<>DOS_SPARE_FD
+.3957f5		85 20		sta $0340	                STA DOS_FD_PTR
+.3957f7		a9 38 00	lda #$0038	                LDA #`DOS_SPARE_FD
+.3957fa		85 22		sta $0342	                STA DOS_FD_PTR+2
+.3957fc		a9 ff ff	lda #$ffff	                LDA #$FFFF                              ; We want to load to the address provided by the file
+.3957ff		8f 54 03 00	sta $000354	                STA @l DOS_DST_PTR
+.395803		8f 56 03 00	sta $000356	                STA @l DOS_DST_PTR+2
+.395807		22 18 11 00	jsl $001118	                JSL F_LOAD                              ; Try to load the file
+.39580b		b0 14		bcs $395821	                BCS try_execute
+.39580d		82 7f ff	brl $39578f	                BRL IF_PASSFAILURE                      ; On error: pass failure up the chain
+.395810						chk_execute
+.395810		c2 20		rep #$20	                REP #$20        ; set A long
+.395812		a5 3c		lda $035c	                LDA DOS_RUN_PTR                         ; Check to see if we got a startup address back
+.395814		d0 0b		bne $395821	                BNE try_execute                         ; If so: call it
+.395816		a5 3e		lda $035e	                LDA DOS_RUN_PTR+2
+.395818		d0 07		bne $395821	                BNE try_execute
+.39581a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39581c		a9 11		lda #$11	                LDA #DOS_ERR_NOEXEC                     ; If not: return an error that it's not executable
+.39581e		82 6a ff	brl $39578b	                BRL IF_FAILURE
+.395821						try_execute
+.395821		e2 20		sep #$20	                SEP #$20        ; set A short
+.395823		a5 42		lda $0362	                LDA DOS_RUN_PARAM+2
+.395825		48		pha		                PHA
+.395826		a5 41		lda $0361	                LDA DOS_RUN_PARAM+1
+.395828		48		pha		                PHA
+.395829		a5 40		lda $0360	                LDA DOS_RUN_PARAM
+.39582b		48		pha		                PHA
+.39582c		a9 5c		lda #$5c	                LDA #$5C                                ; Write a JML opcode
+.39582e		85 3b		sta $035b	                STA DOS_RUN_PTR-1
+.395830		22 5b 03 00	jsl $00035b	                JSL DOS_RUN_PTR-1                       ; And call to it
+.395834		e2 20		sep #$20	                SEP #$20        ; set A short
+.395836		68		pla		                PLA                                     ; Remove the path and parameters string from the stack
+.395837		68		pla		                PLA
+.395838		68		pla		                PLA
+.395839		82 5a ff	brl $395796	                BRL IF_SUCCESS                          ; Return success
+.39583c						IF_ALLOCFD
+.39583c		da		phx		                PHX
+.39583d		5a		phy		                PHY
+.39583e		0b		phd		                PHD
+.39583f		8b		phb		                PHB
+.395840		08		php		                PHP
+.395841		48		pha		                PHA             ; begin setdbr macro
+.395842		08		php		                PHP
+.395843		e2 20		sep #$20	                SEP #$20        ; set A short
+.395845		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.395847		48		pha		                PHA
+.395848		ab		plb		                PLB
+.395849		28		plp		                PLP
+.39584a		68		pla		                PLA             ; end setdbr macro
+.39584b		48		pha		                PHA             ; begin setdp macro
+.39584c		08		php		                PHP
+.39584d		c2 20		rep #$20	                REP #$20        ; set A long
+.39584f		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395852		5b		tcd		                TCD
+.395853		28		plp		                PLP
+.395854		68		pla		                PLA             ; end setdp macro
+.395855		c2 10		rep #$10	                REP #$10        ; set X long
+.395857		a2 00 00	ldx #$0000	                LDX #0                              ; Point to the first file descriptor
+.39585a						chk_fd
+.39585a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39585c		bd 20 ad	lda $38ad20,x	                LDA @w DOS_FILE_DESCS,X             ; Check the file descriptor's status
+.39585f		89 10		bit #$10	                BIT #FD_STAT_ALLOC                  ; Is the file descriptor allocated?
+.395861		f0 14		beq $395877	                BEQ found                           ; No: flag and return the found descriptor
+.395863						next_fd
+.395863		c2 20		rep #$20	                REP #$20        ; set A long
+.395865		8a		txa		                TXA                                 ; Yes: Move to the next file descriptor
+.395866		18		clc		                CLC
+.395867		69 20 00	adc #$0020	                ADC #SIZE(FILEDESC)
+.39586a		aa		tax		                TAX
+.39586b		e0 00 01	cpx #$0100	                CPX #SIZE(FILEDESC) * DOS_FD_MAX    ; Are we out of file descriptors?
+.39586e		90 ea		bcc $39585a	                BLT chk_fd                          ; No: check this new file descriptor
+.395870		e2 20		sep #$20	                SEP #$20        ; set A short
+.395872		a9 16		lda #$16	                LDA #DOS_ERR_NOFD                   ; Yes: Return failure (no file descriptors available)
+.395874		82 14 ff	brl $39578b	                BRL IF_FAILURE
+.395877		09 10		ora #$10	found           ORA #FD_STAT_ALLOC                  ; No: Set the ALLOC bit
+.395879		9d 20 ad	sta $38ad20,x	                STA @w DOS_FILE_DESCS,X             ; And store it in the file descriptor's status
+.39587c		c2 20		rep #$20	                REP #$20        ; set A long
+.39587e		8a		txa		                TXA
+.39587f		18		clc		                CLC
+.395880		69 20 ad	adc #$ad20	                ADC #<>DOS_FILE_DESCS
+.395883		85 20		sta $0340	                STA @b DOS_FD_PTR
+.395885		a9 38 00	lda #$0038	                LDA #`DOS_FILE_DESCS
+.395888		69 00 00	adc #$0000	                ADC #0
+.39588b		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.39588d		82 06 ff	brl $395796	                BRL IF_SUCCESS                      ; Return this file descriptor
+.395890						IF_FREEFD
+.395890		da		phx		                PHX
+.395891		5a		phy		                PHY
+.395892		0b		phd		                PHD
+.395893		8b		phb		                PHB
+.395894		08		php		                PHP
+.395895		48		pha		                PHA             ; begin setdbr macro
+.395896		08		php		                PHP
+.395897		e2 20		sep #$20	                SEP #$20        ; set A short
+.395899		a9 38		lda #$38	                LDA #`DOS_HIGH_VARIABLES
+.39589b		48		pha		                PHA
+.39589c		ab		plb		                PLB
+.39589d		28		plp		                PLP
+.39589e		68		pla		                PLA             ; end setdbr macro
+.39589f		48		pha		                PHA             ; begin setdp macro
+.3958a0		08		php		                PHP
+.3958a1		c2 20		rep #$20	                REP #$20        ; set A long
+.3958a3		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3958a6		5b		tcd		                TCD
+.3958a7		28		plp		                PLP
+.3958a8		68		pla		                PLA             ; end setdp macro
+.3958a9		e2 20		sep #$20	                SEP #$20        ; set A short
+.3958ab		c2 10		rep #$10	                REP #$10        ; set X long
+.3958ad		a9 00		lda #$00	                LDA #0
+.3958af		87 20		sta [$0340]	                STA [DOS_FD_PTR]
+.3958b1		82 e2 fe	brl $395796	                BRL IF_SUCCESS
+.3958b4						DOS_SRC2DST
+.3958b4		da		phx		                PHX
+.3958b5		5a		phy		                PHY
+.3958b6		0b		phd		                PHD
+.3958b7		8b		phb		                PHB
+.3958b8		08		php		                PHP
+.3958b9		48		pha		                PHA             ; begin setdp macro
+.3958ba		08		php		                PHP
+.3958bb		c2 20		rep #$20	                REP #$20        ; set A long
+.3958bd		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3958c0		5b		tcd		                TCD
+.3958c1		28		plp		                PLP
+.3958c2		68		pla		                PLA             ; end setdp macro
+.3958c3		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3958c5		a0 0e 00	ldy #$000e	                LDY #FILEDESC.BUFFER
+.3958c8		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
+.3958ca		aa		tax		                TAX                                     ; X := source buffer address
+.3958cb		b7 34		lda [$0354],y	                LDA [DOS_DST_PTR],Y
+.3958cd		a8		tay		                TAY                                     ; Y := destination buffer address
+.3958ce		a9 00 02	lda #$0200	                LDA #DOS_SECTOR_SIZE                    ; A := the size of the buffers
+.3958d1		54 38 38	mvn $38,$38	                MVN #`DOS_FILE_BUFFS,#`DOS_FILE_BUFFS   ; Copy the sector data
+.3958d4		28		plp		                PLP
+.3958d5		ab		plb		                PLB
+.3958d6		2b		pld		                PLD
+.3958d7		7a		ply		                PLY
+.3958d8		fa		plx		                PLX
+.3958d9		6b		rtl		                RTL
+.3958da						IF_COPY
+.3958da		da		phx		                PHX
+.3958db		5a		phy		                PHY
+.3958dc		0b		phd		                PHD
+.3958dd		8b		phb		                PHB
+.3958de		08		php		                PHP
+.3958df		48		pha		                PHA             ; begin setdbr macro
+.3958e0		08		php		                PHP
+.3958e1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3958e3		a9 00		lda #$00	                LDA #0
+.3958e5		48		pha		                PHA
+.3958e6		ab		plb		                PLB
+.3958e7		28		plp		                PLP
+.3958e8		68		pla		                PLA             ; end setdbr macro
+.3958e9		48		pha		                PHA             ; begin setdp macro
+.3958ea		08		php		                PHP
+.3958eb		c2 20		rep #$20	                REP #$20        ; set A long
+.3958ed		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3958f0		5b		tcd		                TCD
+.3958f1		28		plp		                PLP
+.3958f2		68		pla		                PLA             ; end setdp macro
+.3958f3		22 3c 58 39	jsl $39583c	                JSL IF_ALLOCFD                  ; Allocate an FD for the source
+.3958f7		b0 03		bcs $3958fc	                BCS set_src_path
+.3958f9		82 93 fe	brl $39578f	                BRL IF_PASSFAILURE              ; If failed: pass the failure up the chain
+.3958fc						set_src_path
+.3958fc		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3958fe		a0 02 00	ldy #$0002	                LDY #FILEDESC.PATH              ; Set the source path
+.395901		a5 44		lda $0364	                LDA @b DOS_STR1_PTR
+.395903		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.395905		c8		iny		                INY
+.395906		c8		iny		                INY
+.395907		a5 46		lda $0366	                LDA @b DOS_STR1_PTR+2
+.395909		97 20		sta [$0340],y	                STA [DOS_FD_PTR],Y
+.39590b						alloc_dest
+.39590b		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39590d		a5 20		lda $0340	                LDA @b DOS_FD_PTR               ; set DOS_SRC_PTR to the file descriptor pointer
+.39590f		85 30		sta $0350	                STA @b DOS_SRC_PTR
+.395911		a5 22		lda $0342	                LDA @b DOS_FD_PTR+2
+.395913		85 32		sta $0352	                STA @b DOS_SRC_PTR+2
+.395915		22 3c 58 39	jsl $39583c	                JSL IF_ALLOCFD                  ; Allocate an FD for the destination
+.395919		b0 0f		bcs $39592a	                BCS set_paths                   ; If everything is ok... start setting the paths
+.39591b		a5 30		lda $0350	err_free_src_fd LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
+.39591d		85 20		sta $0340	                STA @b DOS_FD_PTR
+.39591f		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
+.395921		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.395923		22 90 58 39	jsl $395890	                JSL IF_FREEFD                   ; And free it
+.395927		82 65 fe	brl $39578f	                BRL IF_PASSFAILURE              ; Pass the failure up the chain
+.39592a						set_paths
+.39592a		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39592c		a5 20		lda $0340	                LDA @b DOS_FD_PTR               ; Set DOS_DST_PTR to the file descriptor pointer for the destination
+.39592e		85 34		sta $0354	                STA @b DOS_DST_PTR
+.395930		a5 22		lda $0342	                LDA @b DOS_FD_PTR+2
+.395932		85 36		sta $0356	                STA @b DOS_DST_PTR+2
+.395934		a0 02 00	ldy #$0002	                LDY #FILEDESC.PATH              ; Set the destination path
+.395937		a5 48		lda $0368	                LDA @b DOS_STR2_PTR
+.395939		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.39593b		c8		iny		                INY
+.39593c		c8		iny		                INY
+.39593d		a5 4a		lda $036a	                LDA @b DOS_STR2_PTR+2
+.39593f		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.395941		a5 30		lda $0350	                LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
+.395943		85 20		sta $0340	                STA @b DOS_FD_PTR
+.395945		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
+.395947		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.395949		22 f0 10 00	jsl $0010f0	                JSL F_OPEN                      ; Try to open the file
+.39594d		b0 0f		bcs $39595e	                BCS src_open                    ; If success, work with the openned file
+.39594f		a5 34		lda $0354	err_free_dst_fd LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
+.395951		85 20		sta $0340	                STA @b DOS_FD_PTR
+.395953		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
+.395955		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.395957		22 90 58 39	jsl $395890	                JSL IF_FREEFD                   ; And free it
+.39595b		82 bd ff	brl $39591b	                BRL err_free_src_fd             ; Free the source file descriptor
+.39595e		a0 12 00	ldy #$0012	src_open        LDY #FILEDESC.SIZE              ; destination file size := source file size
+.395961		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
+.395963		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.395965		c8		iny		                INY
+.395966		c8		iny		                INY
+.395967		b7 30		lda [$0350],y	                LDA [DOS_SRC_PTR],Y
+.395969		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.39596b		22 b4 58 39	jsl $3958b4	                JSL DOS_SRC2DST                 ; Copy the first sector's worth of data
+.39596f		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
+.395971		85 20		sta $0340	                STA @b DOS_FD_PTR
+.395973		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
+.395975		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.395977		22 f4 10 00	jsl $0010f4	                JSL F_CREATE                    ; Attempt to create the file
+.39597b		b0 0f		bcs $39598c	                BCS read_next                   ; If sucessful, try to get the next cluster
+.39597d		a5 30		lda $0350	err_src_close   LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
+.39597f		85 20		sta $0340	                STA @b DOS_FD_PTR
+.395981		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
+.395983		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.395985		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Close the source file (maybe not really necessary)
+.395989		82 c3 ff	brl $39594f	                BRL err_free_dst_fd             ; Free the file descriptors and return an error
+.39598c						read_next
+.39598c		a5 30		lda $0350	                LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
+.39598e		85 20		sta $0340	                STA @b DOS_FD_PTR
+.395990		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
+.395992		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.395994		22 00 11 00	jsl $001100	                JSL F_READ                      ; Attempt to read the next sector of the source
+.395998		b0 19		bcs $3959b3	                BCS copy2dest                   ; If successful, copy the sector
+.39599a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39599c		a5 0e		lda $032e	                LDA @b DOS_STATUS
+.39599e		c9 0a		cmp #$0a	                CMP #DOS_ERR_NOCLUSTER          ; Are there no more clusters in the source file?
+.3959a0		f0 32		beq $3959d4	                BEQ file_copied                 ; Yes: we're done copying
+.3959a2						err_dest_close
+.3959a2		c2 20		rep #$20	                REP #$20        ; set A long
+.3959a4		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
+.3959a6		85 20		sta $0340	                STA @b DOS_FD_PTR
+.3959a8		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
+.3959aa		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.3959ac		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Attempt to close the destination
+.3959b0		82 ca ff	brl $39597d	                BRL err_src_close               ; Close the source and throw an error
+.3959b3						copy2dest
+.3959b3		22 b4 58 39	jsl $3958b4	                JSL DOS_SRC2DST                 ; Copy the source sector to the destination sector
+.3959b7		a0 06 00	ldy #$0006	                LDY #FILEDESC.CLUSTER           ; destination sector cluster ID := 0 to append
+.3959ba		a9 00 00	lda #$0000	                LDA #0
+.3959bd		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.3959bf		c8		iny		                INY
+.3959c0		c8		iny		                INY
+.3959c1		97 34		sta [$0354],y	                STA [DOS_DST_PTR],Y
+.3959c3		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
+.3959c5		85 20		sta $0340	                STA @b DOS_FD_PTR
+.3959c7		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
+.3959c9		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.3959cb		22 fc 10 00	jsl $0010fc	                JSL F_WRITE                     ; Attempt to write the destionation sector to the disk
+.3959cf		90 d1		bcc $3959a2	                BCC err_dest_close              ; If error: close all files and throw the error
+.3959d1		82 b8 ff	brl $39598c	                BRL read_next                   ; Otherwise: repeat the loop
+.3959d4						file_copied
+.3959d4		c2 20		rep #$20	                REP #$20        ; set A long
+.3959d6		a5 34		lda $0354	                LDA @b DOS_DST_PTR              ; Get the destination file descriptor pointer
+.3959d8		85 20		sta $0340	                STA @b DOS_FD_PTR
+.3959da		a5 36		lda $0356	                LDA @b DOS_DST_PTR+2
+.3959dc		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.3959de		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Close the destination
+.3959e2		a5 30		lda $0350	                LDA @b DOS_SRC_PTR              ; Get the source file descriptor pointer
+.3959e4		85 20		sta $0340	                STA @b DOS_FD_PTR
+.3959e6		a5 32		lda $0352	                LDA @b DOS_SRC_PTR+2
+.3959e8		85 22		sta $0342	                STA @b DOS_FD_PTR+2
+.3959ea		22 f8 10 00	jsl $0010f8	                JSL F_CLOSE                     ; Close the source
+.3959ee		82 a5 fd	brl $395796	                BRL IF_SUCCESS
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\uart.asm
+
+=$af18f8					    UART1_BASE = $AF18F8        ; Base address for UART 1 (COM1) in the C256 Foenix U (only 1 Serial port)
+=$af18f8					    UART2_BASE = $AF18F8
+=$00						UART_TRHB = $00             ; Transmit/Receive Hold Buffer
+=$00						UART_DLL = UART_TRHB        ; Divisor Latch Low Byte
+=$01						UART_DLH = $01              ; Divisor Latch High Byte
+=$01						UART_IER = UART_DLH         ; Interupt Enable Register
+=$02						UART_FCR = $02              ; FIFO Control Register
+=$02						UART_IIR = UART_FCR         ; Interupt Indentification Register
+=$03						UART_LCR = $03              ; Line Control Register
+=$04						UART_MCR = $04              ; Modem Control REgister
+=$05						UART_LSR = $05              ; Line Status Register
+=$06						UART_MSR = $06              ; Modem Status Register
+=$07						UART_SR = $07               ; Scratch Register
+=$20						UINT_LOW_POWER = $20        ; Enable Low Power Mode (16750)
+=$10						UINT_SLEEP_MODE = $10       ; Enable Sleep Mode (16750)
+=$08						UINT_MODEM_STATUS = $08     ; Enable Modem Status Interrupt
+=$04						UINT_LINE_STATUS = $04      ; Enable Receiver Line Status Interupt
+=$02						UINT_THR_EMPTY = $02        ; Enable Transmit Holding Register Empty interrupt
+=$01						UINT_DATA_AVAIL = $01       ; Enable Recieve Data Available interupt
+=$80						IIR_FIFO_ENABLED = $80      ; FIFO is enabled
+=$40						IIR_FIFO_NONFUNC = $40      ; FIFO is not functioning
+=$20						IIR_FIFO_64BYTE = $20       ; 64 byte FIFO enabled (16750)
+=$00						IIR_MODEM_STATUS = $00      ; Modem Status Interrupt
+=$02						IIR_THR_EMPTY = $02         ; Transmit Holding Register Empty Interrupt
+=$04						IIR_DATA_AVAIL = $04        ; Data Available Interrupt
+=$06						IIR_LINE_STATUS = $06       ; Line Status Interrupt
+=$0c						IIR_TIMEOUT = $0C           ; Time-out Interrupt (16550 and later)
+=$01						IIR_INTERRUPT_PENDING = $01 ; Interrupt Pending Flag
+=$80						LCR_DLB = $80               ; Divisor Latch Access Bit
+=$60						LCR_SBE = $60               ; Set Break Enable
+=$00						LCR_PARITY_NONE = $00       ; Parity: None
+=$08						LCR_PARITY_ODD = $08        ; Parity: Odd
+=$18						LCR_PARITY_EVEN = $18       ; Parity: Even
+=$28						LCR_PARITY_MARK = $28       ; Parity: Mark
+=$38						LCR_PARITY_SPACE = $38      ; Parity: Space
+=$00						LCR_STOPBIT_1 = $00         ; One Stop Bit
+=$04						LCR_STOPBIT_2 = $04         ; 1.5 or 2 Stop Bits
+=$00						LCR_DATABITS_5 = $00        ; Data Bits: 5
+=$01						LCR_DATABITS_6 = $01        ; Data Bits: 6
+=$02						LCR_DATABITS_7 = $02        ; Data Bits: 7
+=$03						LCR_DATABITS_8 = $03        ; Data Bits: 8
+=$80						LSR_ERR_RECIEVE = $80       ; Error in Received FIFO
+=$40						LSR_XMIT_DONE = $40         ; All data has been transmitted
+=$20						LSR_XMIT_EMPTY = $20        ; Empty transmit holding register
+=$10						LSR_BREAK_INT = $10         ; Break interrupt
+=$08						LSR_ERR_FRAME = $08         ; Framing error
+=$04						LSR_ERR_PARITY = $04        ; Parity error
+=$02						LSR_ERR_OVERRUN = $02       ; Overrun error
+=$01						LSR_DATA_AVAIL = $01        ; Data is ready in the receive buffer
+=384						UART_300 = 384              ; Code for 300 bps
+=96						UART_1200 = 96              ; Code for 1200 bps
+=48						UART_2400 = 48              ; Code for 2400 bps
+=24						UART_4800 = 24              ; Code for 4800 bps
+=12						UART_9600 = 12              ; Code for 9600 bps
+=6						UART_19200 = 6              ; Code for 19200 bps
+=3						UART_38400 = 3              ; Code for 28400 bps
+=2						UART_57600 = 2              ; Code for 57600 bps
+=1						UART_115200 = 1             ; Code for 115200 bps
+.3959f1						UART_SELECT
+.3959f1		08		php		            PHP
+.3959f2		c2 20		rep #$20	                REP #$20        ; set A long
+.3959f4		c9 02 00	cmp #$0002	            CMP #2
+.3959f7		f0 07		beq $395a00	            BEQ is_COM2
+.3959f9		c2 20		rep #$20	                REP #$20        ; set A long
+.3959fb		a9 f8 18	lda #$18f8	            LDA #<>UART1_BASE
+.3959fe		80 05		bra $395a05	            BRA setaddr
+.395a00						is_COM2
+.395a00		c2 20		rep #$20	                REP #$20        ; set A long
+.395a02		a9 f8 18	lda #$18f8	            LDA #<>UART2_BASE
+.395a05		8f 00 07 00	sta $000700	setaddr     STA @lCURRUART
+.395a09		e2 20		sep #$20	                SEP #$20        ; set A short
+.395a0b		a9 af		lda #$af	            LDA #`UART1_BASE
+.395a0d		8f 02 07 00	sta $000702	            STA @lCURRUART+2
+.395a11		28		plp		            PLP
+.395a12		6b		rtl		            RTL
+.395a13						UART_SETBPS
+.395a13		08		php		            PHP
+.395a14		0b		phd		            PHD
+.395a15		48		pha		                PHA             ; begin setdp macro
+.395a16		08		php		                PHP
+.395a17		c2 20		rep #$20	                REP #$20        ; set A long
+.395a19		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
+.395a1c		5b		tcd		                TCD
+.395a1d		28		plp		                PLP
+.395a1e		68		pla		                PLA             ; end setdp macro
+.395a1f		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395a21		48		pha		            PHA
+.395a22		e2 20		sep #$20	                SEP #$20        ; set A short
+.395a24		a0 03 00	ldy #$0003	            LDY #UART_LCR       ; Enable divisor latch
+.395a27		b7 00		lda [$0700],y	            LDA [CURRUART],Y
+.395a29		09 80		ora #$80	            ORA #LCR_DLB
+.395a2b		97 00		sta [$0700],y	            STA [CURRUART],Y
+.395a2d		c2 20		rep #$20	                REP #$20        ; set A long
+.395a2f		68		pla		            PLA
+.395a30		a0 00 00	ldy #$0000	            LDY #UART_DLL
+.395a33		97 00		sta [$0700],y	            STA [CURRUART],Y    ; Save the divisor to the UART
+.395a35		e2 20		sep #$20	                SEP #$20        ; set A short
+.395a37		a0 03 00	ldy #$0003	            LDY #UART_LCR       ; Disable divisor latch
+.395a3a		b7 00		lda [$0700],y	            LDA [CURRUART],Y
+.395a3c		49 80		eor #$80	            EOR #LCR_DLB
+.395a3e		97 00		sta [$0700],y	            STA [CURRUART],Y
+.395a40		2b		pld		            PLD
+.395a41		28		plp		            PLP
+.395a42		6b		rtl		            RTL
+.395a43						UART_SETLCR
+.395a43		08		php		            PHP
+.395a44		0b		phd		            PHD
+.395a45		48		pha		                PHA             ; begin setdp macro
+.395a46		08		php		                PHP
+.395a47		c2 20		rep #$20	                REP #$20        ; set A long
+.395a49		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
+.395a4c		5b		tcd		                TCD
+.395a4d		28		plp		                PLP
+.395a4e		68		pla		                PLA             ; end setdp macro
+.395a4f		e2 20		sep #$20	                SEP #$20        ; set A short
+.395a51		c2 10		rep #$10	                REP #$10        ; set X long
+.395a53		29 7f		and #$7f	            AND #$7F            ; We don't want to alter divisor latch
+.395a55		a0 03 00	ldy #$0003	            LDY #UART_LCR
+.395a58		97 00		sta [$0700],y	            STA [CURRUART],Y
+.395a5a		2b		pld		            PLD
+.395a5b		28		plp		            PLP
+.395a5c		6b		rtl		            RTL
+.395a5d						UART_INIT
+.395a5d		08		php		            PHP
+.395a5e		0b		phd		            PHD
+.395a5f		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395a61		48		pha		                PHA             ; begin setdp macro
+.395a62		08		php		                PHP
+.395a63		c2 20		rep #$20	                REP #$20        ; set A long
+.395a65		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
+.395a68		5b		tcd		                TCD
+.395a69		28		plp		                PLP
+.395a6a		68		pla		                PLA             ; end setdp macro
+.395a6b		a9 01 00	lda #$0001	            LDA #UART_115200
+.395a6e		22 13 5a 39	jsl $395a13	            JSL UART_SETBPS
+.395a72		e2 20		sep #$20	                SEP #$20        ; set A short
+.395a74		a9 03		lda #$03	            LDA #LCR_PARITY_NONE | LCR_STOPBIT_1 | LCR_DATABITS_8
+.395a76		22 43 5a 39	jsl $395a43	            JSL UART_SETLCR
+.395a7a		a9 e1		lda #$e1	            LDA #%11100001
+.395a7c		a0 02 00	ldy #$0002	            LDY #UART_FCR
+.395a7f		97 00		sta [$0700],y	            STA [CURRUART],Y
+.395a81		2b		pld		            PLD
+.395a82		28		plp		            PLP
+.395a83		6b		rtl		            RTL
+.395a84						UART_HASBYT
+.395a84		08		php		            PHP
+.395a85		0b		phd		            PHD
+.395a86		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395a88		48		pha		                PHA             ; begin setdp macro
+.395a89		08		php		                PHP
+.395a8a		c2 20		rep #$20	                REP #$20        ; set A long
+.395a8c		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
+.395a8f		5b		tcd		                TCD
+.395a90		28		plp		                PLP
+.395a91		68		pla		                PLA             ; end setdp macro
+.395a92		e2 20		sep #$20	                SEP #$20        ; set A short
+.395a94		a0 05 00	ldy #$0005	            LDY #UART_LSR           ; Check the receive FIFO
+.395a97		b7 00		lda [$0700],y	wait_putc   LDA [CURRUART],Y
+.395a99		29 01		and #$01	            AND #LSR_DATA_AVAIL
+.395a9b		d0 04		bne $395aa1	            BNE ret_true            ; If flag is set, return true
+.395a9d		2b		pld		ret_false   PLD                     ; Return false
+.395a9e		28		plp		            PLP
+.395a9f		18		clc		            CLC
+.395aa0		6b		rtl		            RTL
+.395aa1		2b		pld		ret_true    PLD                     ; Return true
+.395aa2		28		plp		            PLP
+.395aa3		38		sec		            SEC
+.395aa4		6b		rtl		            RTL
+.395aa5						UART_GETC
+.395aa5		08		php		            PHP
+.395aa6		0b		phd		            PHD
+.395aa7		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395aa9		48		pha		                PHA             ; begin setdp macro
+.395aaa		08		php		                PHP
+.395aab		c2 20		rep #$20	                REP #$20        ; set A long
+.395aad		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
+.395ab0		5b		tcd		                TCD
+.395ab1		28		plp		                PLP
+.395ab2		68		pla		                PLA             ; end setdp macro
+.395ab3		e2 20		sep #$20	                SEP #$20        ; set A short
+.395ab5		a0 05 00	ldy #$0005	            LDY #UART_LSR           ; Check the receive FIFO
+.395ab8		b7 00		lda [$0700],y	wait_getc   LDA [CURRUART],Y
+.395aba		29 01		and #$01	            AND #LSR_DATA_AVAIL
+.395abc		f0 fa		beq $395ab8	            BEQ wait_getc           ; If the flag is clear, wait
+.395abe		a0 00 00	ldy #$0000	            LDY #UART_TRHB          ; Get the byte from the receive FIFO
+.395ac1		b7 00		lda [$0700],y	            LDA [CURRUART],Y
+.395ac3		2b		pld		            PLD
+.395ac4		28		plp		            PLP
+.395ac5		6b		rtl		            RTL
+.395ac6						UART_PUTC
+.395ac6		08		php		            PHP
+.395ac7		0b		phd		            PHD
+.395ac8		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395aca		48		pha		                PHA             ; begin setdp macro
+.395acb		08		php		                PHP
+.395acc		c2 20		rep #$20	                REP #$20        ; set A long
+.395ace		a9 00 07	lda #$0700	                LDA #CURRUART         ; set DP to page 0
+.395ad1		5b		tcd		                TCD
+.395ad2		28		plp		                PLP
+.395ad3		68		pla		                PLA             ; end setdp macro
+.395ad4		e2 20		sep #$20	                SEP #$20        ; set A short
+.395ad6		48		pha		            PHA                     ; Wait for the transmit FIFO to free up
+.395ad7		a0 05 00	ldy #$0005	            LDY #UART_LSR
+.395ada		b7 00		lda [$0700],y	wait_putc   LDA [CURRUART],Y
+.395adc		29 20		and #$20	            AND #LSR_XMIT_EMPTY
+.395ade		f0 fa		beq $395ada	            BEQ wait_putc
+.395ae0		68		pla		            PLA
+.395ae1		a0 00 00	ldy #$0000	            LDY #UART_TRHB
+.395ae4		97 00		sta [$0700],y	            STA [CURRUART],Y
+.395ae6		2b		pld		            PLD
+.395ae7		28		plp		            PLP
+.395ae8		6b		rtl		            RTL
+.395ae9						UART_PUTS
+.395ae9		08		php		            PHP
+.395aea		e2 20		sep #$20	                SEP #$20        ; set A short
+.395aec		bd 00 00	lda $0000,x	put_loop    LDA #0,B,X
+.395aef		f0 07		beq $395af8	            BEQ done
+.395af1		22 c6 5a 39	jsl $395ac6	            JSL UART_PUTC
+.395af5		e8		inx		            INX
+.395af6		80 f4		bra $395aec	            BRA put_loop
+.395af8		28		plp		done        PLP
+.395af9		6b		rtl		            RTL
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\joystick.asm
+
+.395afa						JOYSTICK_SET_NES_MODE
+.395afa		e2 20		sep #$20	                SEP #$20        ; set A short
+.395afc		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b00		29 fb		and #$fb	          AND #~NES_SNES_JOY  ; 0 = NES (8 bit shift)
+.395b02		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b06		6b		rtl		          RTL
+.395b07						JOYSTICK_SET_SNES_MODE
+.395b07		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b09		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b0d		29 fb		and #$fb	          AND #~NES_SNES_JOY
+.395b0f		09 04		ora #$04	          ORA #NES_SNES_JOY   ; 1 = SNES (12 Bit Shift)
+.395b11		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b15		6b		rtl		          RTL
+.395b16						JOYSTICK_ENABLE_NES_SNES_PORT0
+.395b16		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b18		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b1c		29 fe		and #$fe	          AND #~NES_SNES_EN0
+.395b1e		09 01		ora #$01	          ORA #NES_SNES_EN0
+.395b20		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b24		6b		rtl		          RTL
+.395b25						JOYSTICK_ENABLE_NES_SNES_PORT1
+.395b25		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b27		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b2b		29 fd		and #$fd	          AND #~NES_SNES_EN1
+.395b2d		09 02		ora #$02	          ORA #NES_SNES_EN1
+.395b2f		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b33		6b		rtl		          RTL
+.395b34						JOYSTICK_DISABLE_NES_SNES_PORT0
+.395b34		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b36		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b3a		29 fe		and #$fe	          AND #~NES_SNES_EN0
+.395b3c		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b40		6b		rtl		          RTL
+.395b41						JOYSTICK_DISABLE_NES_SNES_PORT1
+.395b41		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b43		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b47		29 fd		and #$fd	          AND #~NES_SNES_EN1
+.395b49		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b4d		6b		rtl		          RTL
+.395b4e						JOYSTICK_NES_SNES_TRIG_WITH_POLL
+.395b4e		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b50		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b54		29 03		and #$03	          AND #(NES_SNES_EN0 | NES_SNES_EN1)
+.395b56		c9 00		cmp #$00	          CMP #$00
+.395b58		f0 14		beq $395b6e	          BEQ END_OF_JOYSTICK_POLL
+.395b5a		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE
+.395b5e		09 80		ora #$80	          ORA #NES_SNES_TRIG   ; Set to 1 (Will auto Clear)
+.395b60		8f 04 e8 af	sta $afe804	          STA JOYSTICK_MODE
+.395b64						JOYSTICK_POLLING_ISNOTOVER
+.395b64		af 04 e8 af	lda $afe804	          LDA JOYSTICK_MODE ;
+.395b68		29 40		and #$40	          AND #NES_SNES_DONE
+.395b6a		c9 40		cmp #$40	          CMP #NES_SNES_DONE
+.395b6c		d0 f6		bne $395b64	          BNE JOYSTICK_POLLING_ISNOTOVER
+.395b6e						END_OF_JOYSTICK_POLL
+.395b6e		6b		rtl		          RTL
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Libraries/sdc_library.asm
+
+.395b6f						SDC_TEST
+.395b6f		8b		phb		                PHB
+.395b70		0b		phd		                PHD
+.395b71		08		php		                PHP
+.395b72		48		pha		                PHA             ; begin setdbr macro
+.395b73		08		php		                PHP
+.395b74		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b76		a9 00		lda #$00	                LDA #0
+.395b78		48		pha		                PHA
+.395b79		ab		plb		                PLB
+.395b7a		28		plp		                PLP
+.395b7b		68		pla		                PLA             ; end setdbr macro
+.395b7c		48		pha		                PHA             ; begin setdp macro
+.395b7d		08		php		                PHP
+.395b7e		c2 20		rep #$20	                REP #$20        ; set A long
+.395b80		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395b83		5b		tcd		                TCD
+.395b84		28		plp		                PLP
+.395b85		68		pla		                PLA             ; end setdp macro
+.395b86		e2 20		sep #$20	                SEP #$20        ; set A short
+.395b88		a9 f0		lda #$f0	                LDA #$F0                            ; Set white on black background
+.395b8a		8d 1e 00	sta $001e	                STA @w CURCOLOR
+.395b8d		22 a8 10 00	jsl $0010a8	                JSL CLRSCREEN
+.395b91		22 a0 10 00	jsl $0010a0	                JSL CSRHOME
+.395b95		22 d5 5b 39	jsl $395bd5	                JSL SDC_INIT                        ; Attempt to initilize the SDC interface
+.395b99		b0 03		bcs $395b9e	                BCS init_ok
+.395b9b		82 15 00	brl $395bb3	                BRL done
+.395b9e		a9 02		lda #$02	init_ok         LDA #BIOS_DEV_SD
+.395ba0		85 01		sta $0321	                STA BIOS_DEV
+.395ba2		22 6a 43 39	jsl $39436a	                JSL DOS_MOUNT                       ; Attempt to mount the SDC
+.395ba6		b0 03		bcs $395bab	                BCS mount_ok
+.395ba8		82 08 00	brl $395bb3	                BRL done
+.395bab		22 18 54 39	jsl $395418	mount_ok        JSL IF_DIROPEN
+.395baf		b0 02		bcs $395bb3	                BCS all_ok
+.395bb1		80 00		bra $395bb3	                BRA done
+.395bb3						all_ok
+.395bb3		22 6c 10 00	jsl $00106c	done            JSL PRINTCR
+.395bb7		28		plp		                PLP
+.395bb8		2b		pld		                PLD
+.395bb9		ab		plb		                PLB
+.395bba		6b		rtl		                RTL
+.395bbb						SDC_WAITBUSY
+.395bbb		08		php		                PHP
+.395bbc		e2 20		sep #$20	                SEP #$20        ; set A short
+.395bbe		af 04 ea af	lda $afea04	wait_xact       LDA @l SDC_TRANS_STATUS_REG         ; Wait for the transaction to complete
+.395bc2		29 01		and #$01	                AND #SDC_TRANS_BUSY
+.395bc4		c9 01		cmp #$01	                CMP #SDC_TRANS_BUSY
+.395bc6		f0 f6		beq $395bbe	                BEQ wait_xact
+.395bc8		28		plp		                PLP
+.395bc9		6b		rtl		                RTL
+.395bca						SDC_RESET
+.395bca		08		php		                PHP
+.395bcb		e2 20		sep #$20	                SEP #$20        ; set A short
+.395bcd		a9 01		lda #$01	                LDA #1
+.395bcf		8f 01 ea af	sta $afea01	                STA @l SDC_CONTROL_REG
+.395bd3		28		plp		                PLP
+.395bd4		6b		rtl		                RTL
+.395bd5						SDC_INIT
+.395bd5		0b		phd		                PHD
+.395bd6		8b		phb		                PHB
+.395bd7		08		php		                PHP
+.395bd8		48		pha		                PHA             ; begin setdbr macro
+.395bd9		08		php		                PHP
+.395bda		e2 20		sep #$20	                SEP #$20        ; set A short
+.395bdc		a9 00		lda #$00	                LDA #0
+.395bde		48		pha		                PHA
+.395bdf		ab		plb		                PLB
+.395be0		28		plp		                PLP
+.395be1		68		pla		                PLA             ; end setdbr macro
+.395be2		48		pha		                PHA             ; begin setdp macro
+.395be3		08		php		                PHP
+.395be4		c2 20		rep #$20	                REP #$20        ; set A long
+.395be6		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395be9		5b		tcd		                TCD
+.395bea		28		plp		                PLP
+.395beb		68		pla		                PLA             ; end setdp macro
+.395bec		e2 20		sep #$20	                SEP #$20        ; set A short
+.395bee		a9 01		lda #$01	start_trans     LDA #SDC_TRANS_INIT_SD
+.395bf0		8f 02 ea af	sta $afea02	                STA @l SDC_TRANS_TYPE_REG           ; Set Init SD
+.395bf4		a9 01		lda #$01	                LDA #SDC_TRANS_START                ; Set the transaction to start
+.395bf6		8f 03 ea af	sta $afea03	                STA @l SDC_TRANS_CONTROL_REG
+.395bfa		22 bb 5b 39	jsl $395bbb	                JSL SDC_WAITBUSY                    ; Wait for initialization to complete
+.395bfe		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
+.395c02		d0 07		bne $395c0b	                BNE ret_error                       ; Is there one? Process the error
+.395c04		64 00		stz $0320	ret_success     STZ BIOS_STATUS
+.395c06		28		plp		                PLP
+.395c07		ab		plb		                PLB
+.395c08		2b		pld		                PLD
+.395c09		38		sec		                SEC
+.395c0a		6b		rtl		                RTL
+.395c0b		8d 06 03	sta $0306	ret_error       STA @w FDC_ST0
+.395c0e		a9 8b		lda #$8b	                LDA #BIOS_ERR_NOTINIT
+.395c10		85 00		sta $0320	set_error       STA BIOS_STATUS
+.395c12		28		plp		                PLP
+.395c13		ab		plb		                PLB
+.395c14		2b		pld		                PLD
+.395c15		18		clc		                CLC
+.395c16		6b		rtl		                RTL
+.395c17						SDC_GETBLOCK
+.395c17		0b		phd		                PHD
+.395c18		8b		phb		                PHB
+.395c19		08		php		                PHP
+.395c1a		48		pha		                PHA             ; begin setdbr macro
+.395c1b		08		php		                PHP
+.395c1c		e2 20		sep #$20	                SEP #$20        ; set A short
+.395c1e		a9 00		lda #$00	                LDA #0
+.395c20		48		pha		                PHA
+.395c21		ab		plb		                PLB
+.395c22		28		plp		                PLP
+.395c23		68		pla		                PLA             ; end setdbr macro
+.395c24		48		pha		                PHA             ; begin setdp macro
+.395c25		08		php		                PHP
+.395c26		c2 20		rep #$20	                REP #$20        ; set A long
+.395c28		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395c2b		5b		tcd		                TCD
+.395c2c		28		plp		                PLP
+.395c2d		68		pla		                PLA             ; end setdp macro
+.395c2e		e2 20		sep #$20	                SEP #$20        ; set A short
+.395c30		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn on the SDC activity light
+.395c34		09 02		ora #$02	                ORA #GABE_CTRL_SDC_LED
+.395c36		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
+.395c3a		a9 00		lda #$00	                LDA #0
+.395c3c		8f 07 ea af	sta $afea07	                STA @l SDC_SD_ADDR_7_0_REG
+.395c40		a5 02		lda $0322	                LDA BIOS_LBA                        ; Set the LBA to read
+.395c42		0a		asl a		                ASL A
+.395c43		8f 08 ea af	sta $afea08	                STA @l SDC_SD_ADDR_15_8_REG
+.395c47		a5 03		lda $0323	                LDA BIOS_LBA+1
+.395c49		2a		rol a		                ROL A
+.395c4a		8f 09 ea af	sta $afea09	                STA @l SDC_SD_ADDR_23_16_REG
+.395c4e		a5 04		lda $0324	                LDA BIOS_LBA+2
+.395c50		2a		rol a		                ROL A
+.395c51		8f 0a ea af	sta $afea0a	                STA @l SDC_SD_ADDR_31_24_REG
+.395c55		a9 02		lda #$02	                LDA #SDC_TRANS_READ_BLK             ; Set the transaction to READ
+.395c57		8f 02 ea af	sta $afea02	                STA @l SDC_TRANS_TYPE_REG
+.395c5b		a9 01		lda #$01	                LDA #SDC_TRANS_START                ; Set the transaction to start
+.395c5d		8f 03 ea af	sta $afea03	                STA @l SDC_TRANS_CONTROL_REG
+.395c61		22 bb 5b 39	jsl $395bbb	                JSL SDC_WAITBUSY                    ; Wait for transaction to complete
+.395c65		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
+.395c69		d0 36		bne $395ca1	                BNE ret_error                       ; Is there one? Process the error
+.395c6b		e2 20		sep #$20	                SEP #$20        ; set A short
+.395c6d		af 13 ea af	lda $afea13	                LDA @l SDC_RX_FIFO_DATA_CNT_LO      ; Record the number of bytes read
+.395c71		85 0a		sta $032a	                STA BIOS_FIFO_COUNT
+.395c73		af 12 ea af	lda $afea12	                LDA @l SDC_RX_FIFO_DATA_CNT_HI
+.395c77		85 0b		sta $032b	                STA BIOS_FIFO_COUNT+1
+.395c79		c2 10		rep #$10	                REP #$10        ; set X long
+.395c7b		a0 00 00	ldy #$0000	                LDY #0
+.395c7e		af 10 ea af	lda $afea10	loop_rd         LDA @l SDC_RX_FIFO_DATA_REG         ; Get the byte...
+.395c82		97 06		sta [$0326],y	                STA [BIOS_BUFF_PTR],Y               ; Save it to the buffer
+.395c84		c8		iny		                INY                                 ; Advance to the next byte
+.395c85		c0 00 02	cpy #$0200	                CPY #512                            ; Have we read all the bytes?
+.395c88		d0 f4		bne $395c7e	                BNE loop_rd                         ; No: keep reading
+.395c8a		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
+.395c8e		d0 11		bne $395ca1	                BNE ret_error                       ; Is there one? Process the error
+.395c90		64 00		stz $0320	ret_success     STZ BIOS_STATUS                     ; Return success
+.395c92		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
+.395c96		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
+.395c98		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
+.395c9c		28		plp		                PLP
+.395c9d		ab		plb		                PLB
+.395c9e		2b		pld		                PLD
+.395c9f		38		sec		                SEC
+.395ca0		6b		rtl		                RTL
+.395ca1		8d 06 03	sta $0306	ret_error       STA @w FDC_ST0
+.395ca4		a9 82		lda #$82	                LDA #BIOS_ERR_READ
+.395ca6		85 00		sta $0320	                STA BIOS_STATUS
+.395ca8		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
+.395cac		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
+.395cae		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
+.395cb2		28		plp		                PLP
+.395cb3		ab		plb		                PLB
+.395cb4		2b		pld		                PLD
+.395cb5		18		clc		                CLC
+.395cb6		6b		rtl		                RTL
+.395cb7						SDC_PUTBLOCK
+.395cb7		0b		phd		                PHD
+.395cb8		8b		phb		                PHB
+.395cb9		08		php		                PHP
+.395cba		48		pha		                PHA             ; begin setdbr macro
+.395cbb		08		php		                PHP
+.395cbc		e2 20		sep #$20	                SEP #$20        ; set A short
+.395cbe		a9 00		lda #$00	                LDA #0
+.395cc0		48		pha		                PHA
+.395cc1		ab		plb		                PLB
+.395cc2		28		plp		                PLP
+.395cc3		68		pla		                PLA             ; end setdbr macro
+.395cc4		48		pha		                PHA             ; begin setdp macro
+.395cc5		08		php		                PHP
+.395cc6		c2 20		rep #$20	                REP #$20        ; set A long
+.395cc8		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.395ccb		5b		tcd		                TCD
+.395ccc		28		plp		                PLP
+.395ccd		68		pla		                PLA             ; end setdp macro
+.395cce		e2 20		sep #$20	                SEP #$20        ; set A short
+.395cd0		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn on the SDC activity light
+.395cd4		09 02		ora #$02	                ORA #GABE_CTRL_SDC_LED
+.395cd6		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
+.395cda		c2 10		rep #$10	                REP #$10        ; set X long
+.395cdc		a0 00 00	ldy #$0000	                LDY #0
+.395cdf		b7 06		lda [$0326],y	loop_wr         LDA [BIOS_BUFF_PTR],Y               ; Get the byte...
+.395ce1		8f 20 ea af	sta $afea20	                STA @l SDC_TX_FIFO_DATA_REG         ; Save it to the SDC
+.395ce5		c8		iny		                INY                                 ; Advance to the next byte
+.395ce6		c0 00 02	cpy #$0200	                CPY #512                            ; Have we read all the bytes?
+.395ce9		d0 f4		bne $395cdf	                BNE loop_wr                         ; No: keep writing
+.395ceb		a9 00		lda #$00	                LDA #0
+.395ced		8f 07 ea af	sta $afea07	                STA @l SDC_SD_ADDR_7_0_REG
+.395cf1		a5 02		lda $0322	                LDA BIOS_LBA                        ; Set the LBA to write
+.395cf3		0a		asl a		                ASL A
+.395cf4		8f 08 ea af	sta $afea08	                STA @l SDC_SD_ADDR_15_8_REG
+.395cf8		a5 03		lda $0323	                LDA BIOS_LBA+1
+.395cfa		2a		rol a		                ROL A
+.395cfb		8f 09 ea af	sta $afea09	                STA @l SDC_SD_ADDR_23_16_REG
+.395cff		a5 04		lda $0324	                LDA BIOS_LBA+2
+.395d01		2a		rol a		                ROL A
+.395d02		8f 0a ea af	sta $afea0a	                STA @l SDC_SD_ADDR_31_24_REG
+.395d06		a9 03		lda #$03	                LDA #SDC_TRANS_WRITE_BLK            ; Set the transaction to WRITE
+.395d08		8f 02 ea af	sta $afea02	                STA @l SDC_TRANS_TYPE_REG
+.395d0c		a9 01		lda #$01	                LDA #SDC_TRANS_START                ; Set the transaction to start
+.395d0e		8f 03 ea af	sta $afea03	                STA @l SDC_TRANS_CONTROL_REG
+.395d12		22 bb 5b 39	jsl $395bbb	                JSL SDC_WAITBUSY                    ; Wait for transaction to complete
+.395d16		af 05 ea af	lda $afea05	                LDA @l SDC_TRANS_ERROR_REG          ; Check for errors
+.395d1a		d0 11		bne $395d2d	                BNE ret_error                       ; Is there one? Process the error
+.395d1c		64 00		stz $0320	ret_success     STZ BIOS_STATUS                     ; Return success
+.395d1e		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
+.395d22		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
+.395d24		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
+.395d28		28		plp		                PLP
+.395d29		ab		plb		                PLB
+.395d2a		2b		pld		                PLD
+.395d2b		38		sec		                SEC
+.395d2c		6b		rtl		                RTL
+.395d2d		8d 06 03	sta $0306	ret_error       STA @w FDC_ST0
+.395d30		a9 82		lda #$82	                LDA #BIOS_ERR_READ
+.395d32		85 00		sta $0320	                STA BIOS_STATUS
+.395d34		af 80 e8 af	lda $afe880	                LDA @l GABE_MSTR_CTRL               ; Turn off the SDC activity light
+.395d38		29 fd		and #$fd	                AND #~GABE_CTRL_SDC_LED
+.395d3a		8f 80 e8 af	sta $afe880	                STA @l GABE_MSTR_CTRL
+.395d3e		28		plp		                PLP
+.395d3f		ab		plb		                PLB
+.395d40		2b		pld		                PLD
+.395d41		18		clc		                CLC
+.395d42		6b		rtl		                RTL
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Libraries/fdc_library.asm
+
+=4295454					FDC_MOTOR_TIME = 4295454        ; Time to wait for the motor to come on: 300ms
+=2147727					FDC_SEEK_TIME = 2147727         ; Time to wait for a seek to happen: 150ms
+=900						FDC_MOTOR_ON_TIME = 60*15       ; Time (in SOF interrupt counts) for the motor to stay on: ~15s?
+=30						FDC_WAIT_TIME = 30              ; Time (in SOF interrupt counts) to allow for a waiting loop to continue
+=13						BPB_SECPERCLUS12_OFF = 13       ; Offset to sectors per cluster in a FAT12 boot sector
+=17						BPB_ROOT_MAX_ENTRY12_OFF = 17   ; Offset to the maximum number of entries in the root directory in FAT12 boot sector
+=22						BPB_SECPERFAT12_OFF = 22        ; Offset to sectors per FAT on a FAT12 boot sector
+.395d43						FDC_TEST
+.395d43		8b		phb		                    PHB
+.395d44		0b		phd		                    PHD
+.395d45		08		php		                    PHP
+.395d46		48		pha		                PHA             ; begin setdbr macro
+.395d47		08		php		                PHP
+.395d48		e2 20		sep #$20	                SEP #$20        ; set A short
+.395d4a		a9 00		lda #$00	                LDA #0
+.395d4c		48		pha		                PHA
+.395d4d		ab		plb		                PLB
+.395d4e		28		plp		                PLP
+.395d4f		68		pla		                PLA             ; end setdbr macro
+.395d50		48		pha		                PHA             ; begin setdp macro
+.395d51		08		php		                PHP
+.395d52		c2 20		rep #$20	                REP #$20        ; set A long
+.395d54		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395d57		5b		tcd		                TCD
+.395d58		28		plp		                PLP
+.395d59		68		pla		                PLA             ; end setdp macro
+.395d5a		e2 20		sep #$20	                SEP #$20        ; set A short
+.395d5c		a9 f0		lda #$f0	                    LDA #$F0
+.395d5e		8d 1e 00	sta $001e	                    STA @w CURCOLOR
+.395d61		22 23 0b 39	jsl $390b23	                    JSL ICLRSCREEN
+.395d65		22 47 09 39	jsl $390947	                    JSL ICSRHOME
+.395d69		c2 30		rep #$30	                REP #$30        ; set A&X long
+.395d6b		22 39 60 39	jsl $396039	                    JSL FDC_Init
+.395d6f		b0 03		bcs $395d74	                    BCS init_ok
+.395d71		82 20 00	brl $395d94	                    BRL motor_off
+.395d74		22 38 67 39	jsl $396738	init_ok             JSL FDC_CHK_MEDIA
+.395d78		90 03		bcc $395d7d	                    BCC no_media
+.395d7a		82 03 00	brl $395d80	                    BRL is_ok1
+.395d7d						no_media
+.395d7d		82 14 00	brl $395d94	                    BRL motor_off
+.395d80		22 cb 65 39	jsl $3965cb	is_ok1              JSL FDC_MOUNT
+.395d84		90 03		bcc $395d89	                    BCC mount_err
+.395d86		82 03 00	brl $395d8c	                    BRL is_ok2
+.395d89						mount_err
+.395d89		82 08 00	brl $395d94	                    BRL motor_off
+.395d8c		22 a0 5d 39	jsl $395da0	is_ok2              JSL FDC_TEST_PUTBLOCK
+.395d90		b0 02		bcs $395d94	                    BCS all_ok
+.395d92		80 00		bra $395d94	                    BRA motor_off
+.395d94						all_ok
+.395d94		22 6c 10 00	jsl $00106c	motor_off           JSL PRINTCR
+.395d98		22 e9 60 39	jsl $3960e9	                    JSL FDC_Motor_Off
+.395d9c		28		plp		                    PLP
+.395d9d		2b		pld		                    PLD
+.395d9e		ab		plb		                    PLB
+.395d9f		6b		rtl		                    RTL
+.395da0						FDC_TEST_PUTBLOCK
+.395da0		e2 20		sep #$20	                SEP #$20        ; set A short
+.395da2		a9 00		lda #$00	                    LDA #0                          ; Initialize the data to write to the drive
+.395da4		a2 00 00	ldx #$0000	                    LDX #0
+.395da7		9f 00 00 03	sta $030000,x	init_loop           STA @l TEST_BUFFER,X
+.395dab		1a		inc a		                    INC A
+.395dac		e8		inx		                    INX
+.395dad		e0 00 02	cpx #$0200	                    CPX #512
+.395db0		d0 f5		bne $395da7	                    BNE init_loop
+.395db2		c2 20		rep #$20	                REP #$20        ; set A long
+.395db4		a9 00 00	lda #$0000	                    LDA #<>TEST_BUFFER              ; Set BIOS_BUFF_PTR
+.395db7		8f 26 03 00	sta $000326	                    STA @l BIOS_BUFF_PTR
+.395dbb		a9 03 00	lda #$0003	                    LDA #`TEST_BUFFER
+.395dbe		8f 28 03 00	sta $000328	                    STA @l BIOS_BUFF_PTR+2
+.395dc2		a9 64 00	lda #$0064	                    LDA #100                        ; Set LBA = 100
+.395dc5		8f 22 03 00	sta $000322	                    STA @l BIOS_LBA
+.395dc9		a9 00 00	lda #$0000	                    LDA #0
+.395dcc		8f 24 03 00	sta $000324	                    STA @l BIOS_LBA+2
+.395dd0		22 5f 65 39	jsl $39655f	                    JSL FDC_PUTBLOCK                ; Try to write the data
+.395dd4		6b		rtl		                    RTL
+>395dd5		40 46 3a 53 41 4d 50 4c		BOOT_FILE           .null "@F:SAMPLE.PGX Hello, world!"
+>395ddd		45 2e 50 47 58 20 48 65 6c 6c 6f 2c 20 77 6f 72
+>395ded		6c 64 21 00
+=$020000					TEST_LOCATION = $020000                     ; Location to try to load it
+=$030000					TEST_BUFFER = $030000                       ; Temporary location for a cluster buffer
+.395df1						FDC_Check_RQM
+.395df1		0b		phd		                    PHD
+.395df2		08		php		                    PHP
+.395df3		48		pha		                PHA             ; begin setdp macro
+.395df4		08		php		                PHP
+.395df5		c2 20		rep #$20	                REP #$20        ; set A long
+.395df7		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395dfa		5b		tcd		                TCD
+.395dfb		28		plp		                PLP
+.395dfc		68		pla		                PLA             ; end setdp macro
+.395dfd		e2 20		sep #$20	                SEP #$20        ; set A short
+.395dff		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
+.395e01		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e05		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
+.395e07		30 12		bmi $395e1b	                    BMI time_out            ; If so: signal a time out
+.395e09		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
+.395e0d		89 80		bit #$80	                    BIT #FDC_MSR_RQM
+.395e0f		f0 f4		beq $395e05	                    BEQ loop
+.395e11		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
+.395e13		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e17		28		plp		                    PLP
+.395e18		2b		pld		                    PLD
+.395e19		38		sec		                    SEC
+.395e1a		60		rts		                    RTS
+.395e1b		28		plp		time_out            PLP
+.395e1c		2b		pld		                    PLD
+.395e1d		18		clc		                    CLC
+.395e1e		60		rts		                    RTS
+.395e1f						FDC_Check_DRV0_BSY
+.395e1f		0b		phd		                    PHD
+.395e20		08		php		                    PHP
+.395e21		48		pha		                PHA             ; begin setdp macro
+.395e22		08		php		                PHP
+.395e23		c2 20		rep #$20	                REP #$20        ; set A long
+.395e25		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395e28		5b		tcd		                TCD
+.395e29		28		plp		                PLP
+.395e2a		68		pla		                PLA             ; end setdp macro
+.395e2b		e2 20		sep #$20	                SEP #$20        ; set A short
+.395e2d		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
+.395e2f		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e33		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
+.395e35		30 12		bmi $395e49	                    BMI time_out            ; If so: signal a time out
+.395e37		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
+.395e3b		89 01		bit #$01	                    BIT #FDC_MSR_DRV0BSY
+.395e3d		d0 f4		bne $395e33	                    BNE loop
+.395e3f		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
+.395e41		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e45		28		plp		                    PLP
+.395e46		2b		pld		                    PLD
+.395e47		38		sec		                    SEC
+.395e48		60		rts		                    RTS
+.395e49		28		plp		time_out            PLP
+.395e4a		2b		pld		                    PLD
+.395e4b		18		clc		                    CLC
+.395e4c		60		rts		                    RTS
+.395e4d						FDC_Check_CMD_BSY
+.395e4d		0b		phd		                    PHD
+.395e4e		08		php		                    PHP
+.395e4f		48		pha		                PHA             ; begin setdp macro
+.395e50		08		php		                PHP
+.395e51		c2 20		rep #$20	                REP #$20        ; set A long
+.395e53		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395e56		5b		tcd		                TCD
+.395e57		28		plp		                PLP
+.395e58		68		pla		                PLA             ; end setdp macro
+.395e59		e2 20		sep #$20	                SEP #$20        ; set A short
+.395e5b		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
+.395e5d		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e61		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
+.395e63		30 12		bmi $395e77	                    BMI time_out            ; If so: signal a time out
+.395e65		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
+.395e69		89 10		bit #$10	                    BIT #FDC_MSR_CMDBSY
+.395e6b		d0 f4		bne $395e61	                    BNE loop
+.395e6d		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
+.395e6f		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e73		28		plp		                    PLP
+.395e74		2b		pld		                    PLD
+.395e75		38		sec		                    SEC
+.395e76		60		rts		                    RTS
+.395e77		28		plp		time_out            PLP
+.395e78		2b		pld		                    PLD
+.395e79		18		clc		                    CLC
+.395e7a		60		rts		                    RTS
+.395e7b						FDC_Can_Read_Data
+.395e7b		0b		phd		                    PHD
+.395e7c		08		php		                    PHP
+.395e7d		48		pha		                PHA             ; begin setdp macro
+.395e7e		08		php		                PHP
+.395e7f		c2 20		rep #$20	                REP #$20        ; set A long
+.395e81		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395e84		5b		tcd		                TCD
+.395e85		28		plp		                PLP
+.395e86		68		pla		                PLA             ; end setdp macro
+.395e87		e2 20		sep #$20	                SEP #$20        ; set A short
+.395e89		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
+.395e8b		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395e8f		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
+.395e91		30 14		bmi $395ea7	                    BMI time_out            ; If so: signal a time out
+.395e93		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
+.395e97		29 40		and #$40	                    AND #FDC_MSR_DIO
+.395e99		c9 40		cmp #$40	                    CMP #FDC_MSR_DIO
+.395e9b		d0 f2		bne $395e8f	                    BNE loop
+.395e9d		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
+.395e9f		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395ea3		28		plp		                    PLP
+.395ea4		2b		pld		                    PLD
+.395ea5		38		sec		                    SEC
+.395ea6		60		rts		                    RTS
+.395ea7		28		plp		time_out            PLP
+.395ea8		2b		pld		                    PLD
+.395ea9		18		clc		                    CLC
+.395eaa		60		rts		                    RTS
+.395eab						FDC_CAN_WRITE
+.395eab		0b		phd		                    PHD
+.395eac		08		php		                    PHP
+.395ead		48		pha		                PHA             ; begin setdp macro
+.395eae		08		php		                PHP
+.395eaf		c2 20		rep #$20	                REP #$20        ; set A long
+.395eb1		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395eb4		5b		tcd		                TCD
+.395eb5		28		plp		                PLP
+.395eb6		68		pla		                PLA             ; end setdp macro
+.395eb7		e2 20		sep #$20	                SEP #$20        ; set A short
+.395eb9		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME      ; Set a time out for the loop
+.395ebb		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395ebf		a5 2c		lda $032c	loop                LDA @b BIOS_FLAGS       ; Check if there was a time out
+.395ec1		30 14		bmi $395ed7	                    BMI time_out            ; If so: signal a time out
+.395ec3		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR
+.395ec7		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
+.395ec9		c9 80		cmp #$80	                    CMP #FDC_MSR_RQM
+.395ecb		d0 f2		bne $395ebf	                    BNE loop
+.395ecd		a9 00		lda #$00	                    LDA #0                  ; Clear the time out
+.395ecf		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395ed3		28		plp		                    PLP
+.395ed4		2b		pld		                    PLD
+.395ed5		38		sec		                    SEC
+.395ed6		60		rts		                    RTS
+.395ed7		28		plp		time_out            PLP
+.395ed8		2b		pld		                    PLD
+.395ed9		18		clc		                    CLC
+.395eda		60		rts		                    RTS
+.395edb						FDC_DELAY_10MS
+.395edb		da		phx		                    PHX
+.395edc		08		php		                    PHP
+.395edd		c2 10		rep #$10	                REP #$10        ; set X long
+.395edf		a2 80 3e	ldx #$3e80	                    LDX #16000          ; Wait for around 10ms
+.395ee2		ea		nop		loop                NOP                 ; Each iteration should take 9 cycles
+.395ee3		ca		dex		                    DEX
+.395ee4		e0 00 00	cpx #$0000	                    CPX #0
+.395ee7		d0 f9		bne $395ee2	                    BNE loop
+.395ee9		28		plp		                    PLP
+.395eea		fa		plx		                    PLX
+.395eeb		6b		rtl		                    RTL
+.395eec						FDC_COMMAND
+.395eec		da		phx		                    PHX
+.395eed		8b		phb		                    PHB
+.395eee		0b		phd		                    PHD
+.395eef		08		php		                    PHP
+.395ef0		48		pha		                PHA             ; begin setdbr macro
+.395ef1		08		php		                PHP
+.395ef2		e2 20		sep #$20	                SEP #$20        ; set A short
+.395ef4		a9 00		lda #$00	                LDA #0
+.395ef6		48		pha		                PHA
+.395ef7		ab		plb		                PLB
+.395ef8		28		plp		                PLP
+.395ef9		68		pla		                PLA             ; end setdbr macro
+.395efa		48		pha		                PHA             ; begin setdp macro
+.395efb		08		php		                PHP
+.395efc		c2 20		rep #$20	                REP #$20        ; set A long
+.395efe		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.395f01		5b		tcd		                TCD
+.395f02		28		plp		                PLP
+.395f03		68		pla		                PLA             ; end setdp macro
+.395f04		22 db 5e 39	jsl $395edb	                    JSL FDC_DELAY_10MS                      ; Wait around 10ms
+.395f08		e2 30		sep #$30	                SEP #$30        ; set A&X short
+.395f0a		a2 00		ldx #$00	                    LDX #0
+.395f0c		a9 00		lda #$00	                    LDA #0
+.395f0e		9d 10 05	sta $0510,x	clr_results         STA FDC_RESULTS,X                       ; Clear the result buffer
+.395f11		e8		inx		                    INX
+.395f12		e0 10		cpx #$10	                    CPX #16
+.395f14		d0 f8		bne $395f0e	                    BNE clr_results
+.395f16		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Validate we can send a command
+.395f1a		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
+.395f1c		c9 80		cmp #$80	                    CMP #FDC_MSR_RQM
+.395f1e		f0 04		beq $395f24	                    BEQ start_send                          ; If so, start sending
+.395f20		22 39 60 39	jsl $396039	fdc_reset           JSL FDC_INIT                            ; Reset the FDC
+.395f24						start_send
+.395f24		e2 10		sep #$10	                SEP #$10        ; set X short
+.395f26		a2 00		ldx #$00	                    LDX #0
+.395f28		20 f1 5d	jsr $395df1	send_loop           JSR FDC_Check_RQM                       ; Wait until we can write
+.395f2b		b0 03		bcs $395f30	                    BCS send_param
+.395f2d		82 5e 00	brl $395f8e	                    BRL time_out                            ; If there was a timeout, flag the time out
+.395f30		bd 00 05	lda $0500,x	send_param          LDA FDC_PARAMETERS,X                    ; Get the parameter/command byte to write
+.395f33		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA                      ; Send it
+.395f37		22 db 5e 39	jsl $395edb	                    JSL FDC_DELAY_10MS                      ; Wait around 10ms for things to settle
+.395f3b		e8		inx		                    INX                                     ; Advance to the next byte
+.395f3c		ec 30 05	cpx $0530	                    CPX FDC_PARAM_NUM
+.395f3f		d0 e7		bne $395f28	                    BNE send_loop                           ; Keep sending until we've sent them all
+.395f41		ad 33 05	lda $0533	                    LDA FDC_EXPECT_DAT                      ; Check the data expectation byte
+.395f44		d0 03		bne $395f49	                    BNE chk_data_dir
+.395f46		82 80 00	brl $395fc9	                    BRL result_phase                        ; If 0: we just want a result
+.395f49		10 3c		bpl $395f87	chk_data_dir        BPL rd_data                             ; If >0: we want to read data
+.395f4b						wr_data
+.395f4b		a5 0b		lda $030b	wr_data_rdy         LDA FDC_STATUS                          ; Check that the motor is still spinning
+.395f4d		30 03		bmi $395f52	                    BMI wr_chk_rqm
+.395f4f		82 3c 00	brl $395f8e	                    BRL time_out                            ; If not, raise an error
+.395f52		af f4 13 af	lda $af13f4	wr_chk_rqm          LDA @l SIO_FDC_MSR                      ; Wait for ready to write
+.395f56		89 80		bit #$80	                    BIT #FDC_MSR_RQM
+.395f58		f0 f1		beq $395f4b	                    BEQ wr_data_rdy
+.395f5a		89 20		bit #$20	                    BIT #FDC_MSR_NONDMA                     ; Check if in execution mode
+.395f5c		d0 03		bne $395f61	                    BNE wr_data_phase                       ; If so: transfer the data
+.395f5e		82 68 00	brl $395fc9	                    BRL result_phase                          ; If not: it's an error
+.395f61						wr_data_phase
+.395f61		c2 10		rep #$10	                REP #$10        ; set X long
+.395f63		a0 00 00	ldy #$0000	                    LDY #0
+.395f66		a5 0b		lda $030b	wr_data_loop        LDA FDC_STATUS                          ; Check that the motor is still spinning
+.395f68		30 03		bmi $395f6d	                    BMI wr_chk_nondma
+.395f6a		82 21 00	brl $395f8e	                    BRL time_out                            ; If not, raise an error
+.395f6d		af f4 13 af	lda $af13f4	wr_chk_nondma       LDA @l SIO_FDC_MSR                      ; Check to see if the FDC is in execution phase
+.395f71		89 20		bit #$20	                    BIT #FDC_MSR_NONDMA
+.395f73		f0 54		beq $395fc9	                    BEQ result_phase                        ; If not: break out to result phase
+.395f75		89 80		bit #$80	                    BIT #FDC_MSR_RQM                        ; Check if we can read data
+.395f77		f0 ed		beq $395f66	                    BEQ wr_data_loop                        ; No: keep waiting
+.395f79		b7 26		lda [$0326],y	                    LDA [BIOS_BUFF_PTR],Y                   ; Get the data byte
+.395f7b		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA                      ; And save it to the buffer
+.395f7f		c8		iny		                    INY                                     ; Move to the next position
+.395f80		c0 00 02	cpy #$0200	                    CPY #512                                ; TODO: set this from the parameters?
+.395f83		d0 e1		bne $395f66	                    BNE wr_data_loop                        ; If not at the end, keep fetching
+.395f85		80 42		bra $395fc9	                    BRA result_phase                        ; ready for the result phase
+.395f87		20 7b 5e	jsr $395e7b	rd_data             JSR FDC_Can_Read_Data
+.395f8a		a5 0b		lda $030b	rd_data_rdy         LDA FDC_STATUS                          ; Check that the motor is still spinning
+.395f8c		30 07		bmi $395f95	                    BMI chk_rd_rdy                          ; If so, check to see if the data is ready
+.395f8e						time_out
+.395f8e		e2 20		sep #$20	                SEP #$20        ; set A short
+.395f90		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT                   ; Otherwise: throw a BIOS_ERR_TIMEOUT error
+.395f92		82 9c 00	brl $396031	                    BRL pass_error
+.395f95		af f4 13 af	lda $af13f4	chk_rd_rdy          LDA @l SIO_FDC_MSR                      ; Wait for data to be ready
+.395f99		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
+.395f9b		c9 c0		cmp #$c0	                    CMP #FDC_MSR_RQM | FDC_MSR_DIO
+.395f9d		d0 eb		bne $395f8a	                    BNE rd_data_rdy
+.395f9f		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Check to see if the FDC is in execution phase
+.395fa3		89 20		bit #$20	                    BIT #FDC_MSR_NONDMA
+.395fa5		d0 03		bne $395faa	                    BNE rd_data_phase                       ; If so: transfer the data
+.395fa7		82 83 00	brl $39602d	                    BRL error                               ; If not: it's an error
+.395faa						rd_data_phase
+.395faa		c2 10		rep #$10	                REP #$10        ; set X long
+.395fac		a0 00 00	ldy #$0000	                    LDY #0
+.395faf		a5 0b		lda $030b	rd_data_loop        LDA FDC_STATUS                          ; Check that the motor is still spinning
+.395fb1		10 db		bpl $395f8e	                    BPL time_out                            ; If not: throw a timeout error
+.395fb3		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Wait for the next byte to be ready
+.395fb7		29 c0		and #$c0	                    AND #FDC_MSR_RQM | FDC_MSR_DIO
+.395fb9		c9 c0		cmp #$c0	                    CMP #FDC_MSR_RQM | FDC_MSR_DIO
+.395fbb		d0 f2		bne $395faf	                    BNE rd_data_loop
+.395fbd		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA                      ; Get the data byte
+.395fc1		97 26		sta [$0326],y	                    STA [BIOS_BUFF_PTR],Y                   ; And save it to the buffer
+.395fc3		c8		iny		                    INY                                     ; Move to the next position
+.395fc4		c0 00 02	cpy #$0200	                    CPY #512                                ; TODO: set this from the parameters?
+.395fc7		d0 e6		bne $395faf	                    BNE rd_data_loop                        ; If not at the end, keep fetching
+.395fc9		ad 32 05	lda $0532	result_phase        LDA FDC_RESULT_NUM                      ; If no results are expected...
+.395fcc		f0 34		beq $396002	                    BEQ chk_busy                            ; Then we're done
+.395fce		e2 10		sep #$10	                SEP #$10        ; set X short
+.395fd0		a2 00		ldx #$00	                    LDX #0
+.395fd2		a9 1e		lda #$1e	                    LDA #FDC_WAIT_TIME                      ; Set the watchdog timer
+.395fd4		22 19 3f 39	jsl $393f19	                    JSL ISETTIMEOUT
+.395fd8		20 7b 5e	jsr $395e7b	result_loop         JSR FDC_Can_Read_Data                   ; Wait until we can read
+.395fdb		90 b1		bcc $395f8e	                    BCC time_out                            ; If there was a time out, raise an error
+.395fdd		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA                      ; Yes: get the data
+.395fe1		20 7b 5e	jsr $395e7b	                    JSR FDC_Can_Read_Data                   ; Wait until we can read
+.395fe4		90 a8		bcc $395f8e	                    BCC time_out                            ; If there was a time out, raise an error
+.395fe6		af f5 13 af	lda $af13f5	read_result         LDA @l SIO_FDC_DTA                      ; Yes: get the data
+.395fea		9d 10 05	sta $0510,x	                    STA FDC_RESULTS,X                       ; Save it to the result buffer
+.395fed		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM
+.395ff0		90 9c		bcc $395f8e	                    BCC time_out                            ; If there was a time out, flag the error
+.395ff2		af f4 13 af	lda $af13f4	rd_chk_1            LDA @l SIO_FDC_MSR
+.395ff6		29 50		and #$50	                    AND #FDC_MSR_DIO | FDC_MSR_CMDBSY
+.395ff8		c9 50		cmp #$50	                    CMP #FDC_MSR_DIO | FDC_MSR_CMDBSY
+.395ffa		d0 06		bne $396002	                    BNE chk_busy
+.395ffc		e8		inx		                    INX                                     ; Move to the next result positions
+.395ffd		ec 32 05	cpx $0532	                    CPX FDC_RESULT_NUM
+.396000		d0 e4		bne $395fe6	                    BNE read_result                         ; And keep looping until we've read all
+.396002						chk_busy
+.396002		c2 10		rep #$10	                REP #$10        ; set X long
+.396004		a2 0a 00	ldx #$000a	                    LDX #10                                 ; Wait 10ms (I guess?)
+.396007		22 2f 14 39	jsl $39142f	                    JSL ILOOP_MS
+.39600b		af f4 13 af	lda $af13f4	                    LDA @l SIO_FDC_MSR                      ; Check the command busy bit
+.39600f		89 10		bit #$10	                    BIT #FDC_MSR_CMDBSY
+.396011		f0 12		beq $396025	                    BEQ done                                ; If not set: we're done
+.396013		20 7b 5e	jsr $395e7b	                    JSR FDC_Can_Read_Data                   ; Wait until we can read
+.396016		b0 03		bcs $39601b	                    BCS get_result_byte
+.396018		82 73 ff	brl $395f8e	                    BRL time_out                            ; If there was a time out, flag the error
+.39601b		af f5 13 af	lda $af13f5	get_result_byte     LDA @l SIO_FDC_DTA                      ; Read the data
+.39601f		9d 10 05	sta $0510,x	                    STA FDC_RESULTS,X
+.396022		e8		inx		                    INX
+.396023		80 dd		bra $396002	                    BRA chk_busy                            ; And keep checking
+.396025						done
+.396025		64 20		stz $0320	                    STZ BIOS_STATUS
+.396027		28		plp		                    PLP
+.396028		2b		pld		                    PLD
+.396029		ab		plb		                    PLB
+.39602a		fa		plx		                    PLX
+.39602b		38		sec		                    SEC
+.39602c		6b		rtl		                    RTL
+.39602d						error
+.39602d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39602f		a9 85		lda #$85	                    LDA #BIOS_ERR_CMD
+.396031		85 20		sta $0320	pass_error          STA BIOS_STATUS
+.396033		28		plp		                    PLP
+.396034		2b		pld		                    PLD
+.396035		ab		plb		                    PLB
+.396036		fa		plx		                    PLX
+.396037		18		clc		                    CLC
+.396038		6b		rtl		                    RTL
+.396039						FDC_Init
+.396039		08		php		                    PHP
+.39603a		c2 10		rep #$10	                REP #$10        ; set X long
+.39603c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39603e		a9 00		lda #$00	                    LDA #0
+.396040		8f f2 13 af	sta $af13f2	                    STA @l SIO_FDC_DOR
+.396044		a2 e8 03	ldx #$03e8	                    LDX #1000                   ; Wait
+.396047		a0 00 00	ldy #$0000	                    LDY #0
+.39604a		22 3c 14 39	jsl $39143c	                    JSL IDELAY
+.39604e		a9 04		lda #$04	                    LDA #FDC_DOR_NRESET         ; Reset the FDC
+.396050		8f f2 13 af	sta $af13f2	                    STA @l SIO_FDC_DOR
+.396054		ea		nop		                    NOP
+.396055		ea		nop		                    NOP
+.396056		ea		nop		                    NOP
+.396057		ea		nop		                    NOP
+.396058		a9 00		lda #$00	                    LDA #$00                    ; Make sure the Speed and Compensation has been set
+.39605a		8f f4 13 af	sta $af13f4	                    STA @l SIO_FDC_DSR
+.39605e		a9 00		lda #$00	                    LDA #$00                    ; Precompensation set to 0
+.396060		8f f7 13 af	sta $af13f7	                    STA @l SIO_FDC_CCR
+.396064		a2 8f c5	ldx #$c58f	                    LDX #<>FDC_SEEK_TIME
+.396067		a0 20 00	ldy #$0020	                    LDY #`FDC_SEEK_TIME
+.39606a		22 3c 14 39	jsl $39143c	                    JSL IDELAY
+.39606e		22 49 61 39	jsl $396149	                    JSL FDC_Sense_Int_Status
+.396072		90 25		bcc $396099	                    BCC pass_failure
+.396074		22 49 61 39	jsl $396149	                    JSL FDC_Sense_Int_Status
+.396078		90 1f		bcc $396099	                    BCC pass_failure
+.39607a		22 49 61 39	jsl $396149	                    JSL FDC_Sense_Int_Status
+.39607e		90 19		bcc $396099	                    BCC pass_failure
+.396080		22 49 61 39	jsl $396149	                    JSL FDC_Sense_Int_Status
+.396084		90 13		bcc $396099	                    BCC pass_failure
+.396086		22 0b 62 39	jsl $39620b	                    JSL FDC_Configure_Command
+.39608a		90 0d		bcc $396099	                    BCC pass_failure
+.39608c		22 b2 61 39	jsl $3961b2	                    JSL FDC_Specify_Command
+.396090		90 07		bcc $396099	                    BCC pass_failure
+.396092		22 b5 60 39	jsl $3960b5	                    JSL FDC_Motor_On
+.396096		28		plp		                    PLP
+.396097		38		sec		                    SEC
+.396098		6b		rtl		                    RTL
+.396099		28		plp		pass_failure        PLP
+.39609a		18		clc		                    CLC
+.39609b		6b		rtl		                    RTL
+.39609c						FDC_MOTOR_NEEDED
+.39609c		08		php		                    PHP
+.39609d		c2 20		rep #$20	                REP #$20        ; set A long
+.39609f		78		sei		                    SEI                         ; Turn off interrupts
+.3960a0		a9 84 03	lda #$0384	                    LDA #FDC_MOTOR_ON_TIME      ; Reset the FDC timeout clock
+.3960a3		8f 4e a0 38	sta $38a04e	                    STA @l FDC_MOTOR_TIMER
+.3960a7		e2 20		sep #$20	                SEP #$20        ; set A short
+.3960a9		af 4c 01 00	lda $00014c	                    LDA @l INT_MASK_REG0
+.3960ad		29 fe		and #$fe	                    AND #~FNX0_INT00_SOF        ; Enable the SOF interrupt
+.3960af		8f 4c 01 00	sta $00014c	                    STA @l INT_MASK_REG0
+.3960b3		28		plp		                    PLP
+.3960b4		6b		rtl		                    RTL
+.3960b5						FDC_Motor_On
+.3960b5		08		php		                    PHP
+.3960b6		22 9c 60 39	jsl $39609c	                    JSL FDC_MOTOR_NEEDED        ; Reset the spindle motor timeout clock
+.3960ba		e2 20		sep #$20	                SEP #$20        ; set A short
+.3960bc		af f2 13 af	lda $af13f2	                    LDA @l SIO_FDC_DOR          ; Check to see if the motor is already on
+.3960c0		89 10		bit #$10	                    BIT #FDC_DOR_MOT0
+.3960c2		d0 1f		bne $3960e3	                    BNE done                    ; If so: skip
+.3960c4		a9 14		lda #$14	                    LDA #FDC_DOR_MOT0 | FDC_DOR_NRESET
+.3960c6		8f f2 13 af	sta $af13f2	                    STA @l SIO_FDC_DOR
+.3960ca		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM           ; Make sure we can leave knowing that everything set properly
+.3960cd		90 17		bcc $3960e6	                    BCC time_out
+.3960cf		a2 1e 8b	ldx #$8b1e	                    LDX #<>FDC_MOTOR_TIME       ; Wait a suitable time for the motor to spin up
+.3960d2		a0 41 00	ldy #$0041	                    LDY #`FDC_MOTOR_TIME
+.3960d5		22 3c 14 39	jsl $39143c	                    JSL IDELAY
+.3960d9		af 0b 03 00	lda $00030b	                    LDA @l FDC_STATUS
+.3960dd		09 80		ora #$80	                    ORA #$80                    ; Flag that the motor should be on
+.3960df		8f 0b 03 00	sta $00030b	                    STA @l FDC_STATUS
+.3960e3		28		plp		done                PLP
+.3960e4		38		sec		                    SEC
+.3960e5		6b		rtl		                    RTL
+.3960e6		28		plp		time_out            PLP                         ; Return a timeout error
+.3960e7		18		clc		                    CLC
+.3960e8		6b		rtl		                    RTL
+.3960e9						FDC_Motor_Off
+.3960e9		08		php		                    PHP
+.3960ea		e2 20		sep #$20	                SEP #$20        ; set A short
+.3960ec		a9 04		lda #$04	                    LDA #FDC_DOR_NRESET
+.3960ee		8f f2 13 af	sta $af13f2	                    STA @L SIO_FDC_DOR
+.3960f2		c2 20		rep #$20	                REP #$20        ; set A long
+.3960f4		78		sei		                    SEI                         ; Turn off interrupts
+.3960f5		a9 00 00	lda #$0000	                    LDA #0                      ; Set FDC motor timeout counter to 0 to disable it
+.3960f8		8f 4e a0 38	sta $38a04e	                    STA @l FDC_MOTOR_TIMER
+.3960fc		e2 20		sep #$20	                SEP #$20        ; set A short
+.3960fe		af 4c 01 00	lda $00014c	                    LDA @l INT_MASK_REG0
+.396102		09 01		ora #$01	                    ORA #FNX0_INT00_SOF         ; Disable the SOF interrupt
+.396104		8f 4c 01 00	sta $00014c	                    STA @l INT_MASK_REG0
+.396108		af 0b 03 00	lda $00030b	                    LDA @l FDC_STATUS
+.39610c		29 7f		and #$7f	                    AND #$7F                    ; Flag that the motor should be off
+.39610e		8f 0b 03 00	sta $00030b	                    STA @l FDC_STATUS
+.396112		28		plp		                    PLP
+.396113		6b		rtl		                    RTL
+.396114						FDC_Recalibrate_Command
+.396114		0b		phd		                    PHD
+.396115		08		php		                    PHP
+.396116		48		pha		                PHA             ; begin setdp macro
+.396117		08		php		                PHP
+.396118		c2 20		rep #$20	                REP #$20        ; set A long
+.39611a		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.39611d		5b		tcd		                TCD
+.39611e		28		plp		                PLP
+.39611f		68		pla		                PLA             ; end setdp macro
+.396120		22 9c 60 39	jsl $39609c	                    JSL FDC_MOTOR_NEEDED        ; Reset the spindle motor timeout clock
+.396124		e2 20		sep #$20	                SEP #$20        ; set A short
+.396126		a9 07		lda #$07	                    LDA #FDC_CMD_RECALIBRATE    ; RECALIBRATE Command
+.396128		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
+.39612b		a5 00		lda $0300	                    LDA FDC_DRIVE
+.39612d		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
+.396130		a9 02		lda #$02	                    LDA #2
+.396132		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM           ; 2 parameters
+.396135		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT          ; 0 data
+.396138		9c 32 05	stz $0532	                    STZ FDC_RESULT_NUM          ; 0 results
+.39613b		22 ec 5e 39	jsl $395eec	                    JSL FDC_COMMAND             ; Issue the command
+.39613f		90 04		bcc $396145	                    BCC pass_failure            ; If failure, pass the failure up
+.396141		28		plp		                    PLP
+.396142		2b		pld		                    PLD
+.396143		38		sec		                    SEC
+.396144		6b		rtl		                    RTL
+.396145		28		plp		pass_failure        PLP
+.396146		2b		pld		                    PLD
+.396147		18		clc		                    CLC
+.396148		6b		rtl		                    RTL
+.396149						FDC_Sense_Int_Status
+.396149		8b		phb		                    PHB
+.39614a		0b		phd		                    PHD
+.39614b		08		php		                    PHP
+.39614c		48		pha		                PHA             ; begin setdbr macro
+.39614d		08		php		                PHP
+.39614e		e2 20		sep #$20	                SEP #$20        ; set A short
+.396150		a9 00		lda #$00	                LDA #0
+.396152		48		pha		                PHA
+.396153		ab		plb		                PLB
+.396154		28		plp		                PLP
+.396155		68		pla		                PLA             ; end setdbr macro
+.396156		48		pha		                PHA             ; begin setdp macro
+.396157		08		php		                PHP
+.396158		c2 20		rep #$20	                REP #$20        ; set A long
+.39615a		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.39615d		5b		tcd		                TCD
+.39615e		28		plp		                PLP
+.39615f		68		pla		                PLA             ; end setdp macro
+.396160		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396162		a2 0a 00	ldx #$000a	                    LDX #10                            ; Wait for 10ms
+.396165		22 2f 14 39	jsl $39142f	                    JSL ILOOP_MS
+.396169		e2 20		sep #$20	                SEP #$20        ; set A short
+.39616b		64 06		stz $0306	                    STZ FDC_ST0                         ; Clear ST0
+.39616d		a9 ff		lda #$ff	                    LDA #$FF
+.39616f		85 0a		sta $030a	                    STA FDC_PCN                         ; Set PCN to some obviously bad value
+.396171		20 4d 5e	jsr $395e4d	                    JSR FDC_Check_CMD_BSY               ; Check I can send a command
+.396174		90 30		bcc $3961a6	                    BCC time_out                        ; If there was a time out, raise an error
+.396176		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM                   ; Check if I can transfer data
+.396179		90 2b		bcc $3961a6	                    BCC time_out                        ; If there was a time out, raise an error
+.39617b		a9 08		lda #$08	                    LDA #FDC_CMD_SENSE_INTERRUPT
+.39617d		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.396181		20 7b 5e	jsr $395e7b	                    JSR FDC_Can_Read_Data
+.396184		90 20		bcc $3961a6	                    BCC time_out                        ; If there was a time out, raise an error
+.396186		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM                   ; Check if I can transfer data
+.396189		90 1b		bcc $3961a6	                    BCC time_out                        ; If there was a time out, raise an error
+.39618b		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA
+.39618f		85 06		sta $0306	                    STA FDC_ST0                         ; --- ST0 ---
+.396191		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM                   ; Check if I can transfer data
+.396194		90 10		bcc $3961a6	                    BCC time_out                        ; If there was a time out, raise an error
+.396196		af f5 13 af	lda $af13f5	                    LDA @l SIO_FDC_DTA
+.39619a		85 0a		sta $030a	                    STA FDC_PCN                         ; --- Cylinder ---
+.39619c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39619e		9c 20 03	stz $0320	                    STZ @w BIOS_STATUS
+.3961a1		28		plp		                    PLP
+.3961a2		2b		pld		                    PLD
+.3961a3		ab		plb		                    PLB
+.3961a4		38		sec		                    SEC
+.3961a5		6b		rtl		                    RTL
+.3961a6						time_out
+.3961a6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3961a8		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT               ; Return a time out error
+.3961aa		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
+.3961ad		28		plp		                    PLP
+.3961ae		2b		pld		                    PLD
+.3961af		ab		plb		                    PLB
+.3961b0		18		clc		                    CLC
+.3961b1		6b		rtl		                    RTL
+.3961b2						FDC_Specify_Command
+.3961b2		8b		phb		                    PHB
+.3961b3		0b		phd		                    PHD
+.3961b4		08		php		                    PHP
+.3961b5		48		pha		                PHA             ; begin setdbr macro
+.3961b6		08		php		                PHP
+.3961b7		e2 20		sep #$20	                SEP #$20        ; set A short
+.3961b9		a9 00		lda #$00	                LDA #0
+.3961bb		48		pha		                PHA
+.3961bc		ab		plb		                PLB
+.3961bd		28		plp		                PLP
+.3961be		68		pla		                PLA             ; end setdbr macro
+.3961bf		48		pha		                PHA             ; begin setdp macro
+.3961c0		08		php		                PHP
+.3961c1		c2 20		rep #$20	                REP #$20        ; set A long
+.3961c3		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.3961c6		5b		tcd		                TCD
+.3961c7		28		plp		                PLP
+.3961c8		68		pla		                PLA             ; end setdp macro
+.3961c9		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3961cb		a2 0a 00	ldx #$000a	                    LDX #10                 ; Wait for 10ms
+.3961ce		22 2f 14 39	jsl $39142f	                    JSL ILOOP_MS
+.3961d2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3961d4		20 4d 5e	jsr $395e4d	                    JSR FDC_Check_CMD_BSY   ; Check I can send a command
+.3961d7		90 26		bcc $3961ff	                    BCC time_out            ; If there was a time out, raise an error
+.3961d9		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.3961dc		90 21		bcc $3961ff	                    BCC time_out            ; If there was a time out, raise an error
+.3961de		a9 03		lda #$03	                    LDA #FDC_CMD_SPECIFY    ; Specify Command
+.3961e0		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.3961e4		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.3961e7		90 16		bcc $3961ff	                    BCC time_out            ; If there was a time out, raise an error
+.3961e9		a9 cf		lda #$cf	                    LDA #$CF
+.3961eb		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.3961ef		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.3961f2		90 0b		bcc $3961ff	                    BCC time_out            ; If there was a time out, raise an error
+.3961f4		a9 01		lda #$01	                    LDA #$01                ; 1 = Non-DMA
+.3961f6		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.3961fa		28		plp		                    PLP
+.3961fb		2b		pld		                    PLD
+.3961fc		ab		plb		                    PLB
+.3961fd		38		sec		                    SEC
+.3961fe		6b		rtl		                    RTL
+.3961ff						time_out
+.3961ff		e2 20		sep #$20	                SEP #$20        ; set A short
+.396201		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT   ; Return a time out error
+.396203		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
+.396206		28		plp		                    PLP
+.396207		2b		pld		                    PLD
+.396208		ab		plb		                    PLB
+.396209		18		clc		                    CLC
+.39620a		6b		rtl		                    RTL
+.39620b						FDC_Configure_Command
+.39620b		8b		phb		                    PHB
+.39620c		0b		phd		                    PHD
+.39620d		08		php		                    PHP
+.39620e		48		pha		                PHA             ; begin setdbr macro
+.39620f		08		php		                PHP
+.396210		e2 20		sep #$20	                SEP #$20        ; set A short
+.396212		a9 00		lda #$00	                LDA #0
+.396214		48		pha		                PHA
+.396215		ab		plb		                PLB
+.396216		28		plp		                PLP
+.396217		68		pla		                PLA             ; end setdbr macro
+.396218		48		pha		                PHA             ; begin setdp macro
+.396219		08		php		                PHP
+.39621a		c2 20		rep #$20	                REP #$20        ; set A long
+.39621c		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.39621f		5b		tcd		                TCD
+.396220		28		plp		                PLP
+.396221		68		pla		                PLA             ; end setdp macro
+.396222		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396224		a2 0a 00	ldx #$000a	                    LDX #10                 ; Wait for 10ms
+.396227		22 2f 14 39	jsl $39142f	                    JSL ILOOP_MS
+.39622b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39622d		20 4d 5e	jsr $395e4d	                    JSR FDC_Check_CMD_BSY   ; Check I can send a command
+.396230		90 36		bcc $396268	                    BCC time_out            ; If there was a time out, raise an error
+.396232		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.396235		90 31		bcc $396268	                    BCC time_out            ; If there was a time out, raise an error
+.396237		a9 13		lda #$13	                    LDA #FDC_CMD_CONFIGURE  ; Specify Command
+.396239		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.39623d		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.396240		90 26		bcc $396268	                    BCC time_out            ; If there was a time out, raise an error
+.396242		a9 00		lda #$00	                    LDA #$00
+.396244		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.396248		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.39624b		90 1b		bcc $396268	                    BCC time_out            ; If there was a time out, raise an error
+.39624d		a9 44		lda #$44	                    LDA #$44                ; Implied Seek, FIFOTHR = 4 byte
+.39624f		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.396253		20 f1 5d	jsr $395df1	                    JSR FDC_Check_RQM       ; Check if I can transfer data
+.396256		90 10		bcc $396268	                    BCC time_out            ; If there was a time out, raise an error
+.396258		a9 00		lda #$00	                    LDA #$00
+.39625a		8f f5 13 af	sta $af13f5	                    STA @l SIO_FDC_DTA
+.39625e		20 4d 5e	jsr $395e4d	                    JSR FDC_Check_CMD_BSY   ; Check I can send a command
+.396261		90 05		bcc $396268	                    BCC time_out            ; If there was a time out, raise an error
+.396263		28		plp		                    PLP
+.396264		2b		pld		                    PLD
+.396265		ab		plb		                    PLB
+.396266		38		sec		                    SEC
+.396267		6b		rtl		                    RTL
+.396268						time_out
+.396268		e2 20		sep #$20	                SEP #$20        ; set A short
+.39626a		a9 8c		lda #$8c	                    LDA #BIOS_ERR_TIMEOUT   ; Return a time out error
+.39626c		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
+.39626f		28		plp		                    PLP
+.396270		2b		pld		                    PLD
+.396271		ab		plb		                    PLB
+.396272		18		clc		                    CLC
+.396273		6b		rtl		                    RTL
+.396274						FDC_Read_ID_Command
+.396274		8b		phb		                    PHB
+.396275		0b		phd		                    PHD
+.396276		08		php		                    PHP
+.396277		48		pha		                PHA             ; begin setdbr macro
+.396278		08		php		                PHP
+.396279		e2 20		sep #$20	                SEP #$20        ; set A short
+.39627b		a9 00		lda #$00	                LDA #0
+.39627d		48		pha		                PHA
+.39627e		ab		plb		                PLB
+.39627f		28		plp		                PLP
+.396280		68		pla		                PLA             ; end setdbr macro
+.396281		48		pha		                PHA             ; begin setdp macro
+.396282		08		php		                PHP
+.396283		c2 20		rep #$20	                REP #$20        ; set A long
+.396285		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.396288		5b		tcd		                TCD
+.396289		28		plp		                PLP
+.39628a		68		pla		                PLA             ; end setdp macro
+.39628b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39628d		a9 0a		lda #$0a	                    LDA #FDC_CMD_READ_ID                ; READID Command
+.39628f		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
+.396292		a9 01		lda #$01	                    LDA #1
+.396294		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 4 parameter (the command)
+.396297		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT                  ; 0 data
+.39629a		a9 07		lda #$07	                    LDA #7
+.39629c		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 7 results
+.39629f		22 ec 5e 39	jsl $395eec	                    JSL FDC_COMMAND                     ; Issue the command
+.3962a3		90 27		bcc $3962cc	                    BCC pass_failure
+.3962a5		ad 10 05	lda $0510	                    LDA FDC_RESULTS
+.3962a8		85 06		sta $0306	                    STA FDC_ST0                         ; Get ST0
+.3962aa		ad 11 05	lda $0511	                    LDA FDC_RESULTS+1
+.3962ad		85 07		sta $0307	                    STA FDC_ST1                         ; Get ST1
+.3962af		ad 12 05	lda $0512	                    LDA FDC_RESULTS+2
+.3962b2		85 08		sta $0308	                    STA FDC_ST2                         ; Get ST2
+.3962b4		ad 13 05	lda $0513	                    LDA FDC_RESULTS+3
+.3962b7		85 02		sta $0302	                    STA FDC_CYLINDER                    ; Get the cylinder
+.3962b9		ad 14 05	lda $0514	                    LDA FDC_RESULTS+4
+.3962bc		85 01		sta $0301	                    STA FDC_HEAD                        ; Get the head
+.3962be		ad 15 05	lda $0515	                    LDA FDC_RESULTS+5
+.3962c1		85 0a		sta $030a	                    STA FDC_PCN                         ; Get the sector
+.3962c3		ad 16 05	lda $0516	                    LDA FDC_RESULTS+6
+.3962c6		85 04		sta $0304	                    STA FDC_SECTOR_SIZE                 ; Get the sector size code
+.3962c8		28		plp		                    PLP
+.3962c9		2b		pld		                    PLD
+.3962ca		ab		plb		                    PLB
+.3962cb		6b		rtl		                    RTL
+.3962cc		28		plp		pass_failure        PLP
+.3962cd		2b		pld		                    PLD
+.3962ce		ab		plb		                    PLB
+.3962cf		18		clc		                    CLC
+.3962d0		6b		rtl		                    RTL
+.3962d1						FDC_DumpReg_Command
+.3962d1		0b		phd		                    PHD
+.3962d2		08		php		                    PHP
+.3962d3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3962d5		a9 0e		lda #$0e	                    LDA #FDC_CMD_DUMPREG                ; DUMPREG Command
+.3962d7		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
+.3962da		a9 01		lda #$01	                    LDA #1
+.3962dc		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 4 parameter (the command)
+.3962df		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT                  ; 0 data
+.3962e2		a9 0a		lda #$0a	                    LDA #10
+.3962e4		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 10 results
+.3962e7		22 ec 5e 39	jsl $395eec	                    JSL FDC_COMMAND                     ; Issue the command
+.3962eb		90 03		bcc $3962f0	                    BCC pass_failure
+.3962ed		28		plp		                    PLP
+.3962ee		2b		pld		                    PLD
+.3962ef		6b		rtl		                    RTL
+.3962f0		28		plp		pass_failure        PLP
+.3962f1		2b		pld		                    PLD
+.3962f2		18		clc		                    CLC
+.3962f3		6b		rtl		                    RTL
+.3962f4						FDC_Seek_Track
+.3962f4		8b		phb		                    PHB
+.3962f5		0b		phd		                    PHD
+.3962f6		08		php		                    PHP
+.3962f7		48		pha		                PHA             ; begin setdbr macro
+.3962f8		08		php		                PHP
+.3962f9		e2 20		sep #$20	                SEP #$20        ; set A short
+.3962fb		a9 00		lda #$00	                LDA #0
+.3962fd		48		pha		                PHA
+.3962fe		ab		plb		                PLB
+.3962ff		28		plp		                PLP
+.396300		68		pla		                PLA             ; end setdbr macro
+.396301		48		pha		                PHA             ; begin setdp macro
+.396302		08		php		                PHP
+.396303		c2 20		rep #$20	                REP #$20        ; set A long
+.396305		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.396308		5b		tcd		                TCD
+.396309		28		plp		                PLP
+.39630a		68		pla		                PLA             ; end setdp macro
+.39630b		22 9c 60 39	jsl $39609c	                    JSL FDC_MOTOR_NEEDED                ; Reset the spindle motor timeout clock
+.39630f		e2 20		sep #$20	                SEP #$20        ; set A short
+.396311		a9 0f		lda #$0f	                    LDA #FDC_CMD_SEEK                   ; Seek Command
+.396313		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
+.396316		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Get the head
+.396318		29 01		and #$01	                    AND #$01
+.39631a		0a		asl a		                    ASL A
+.39631b		0a		asl a		                    ASL A
+.39631c		05 00		ora $0300	                    ORA FDC_DRIVE                       ; And the drive number
+.39631e		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
+.396321		a5 02		lda $0302	                    LDA FDC_CYLINDER                    ; And the track
+.396323		8d 02 05	sta $0502	                    STA FDC_PARAMETERS+2
+.396326		a9 03		lda #$03	                    LDA #3
+.396328		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 3 parameter (the command)
+.39632b		9c 33 05	stz $0533	                    STZ FDC_EXPECT_DAT                  ; 0 data
+.39632e		9c 32 05	stz $0532	                    STZ FDC_RESULT_NUM                  ; 0 results
+.396331		22 ec 5e 39	jsl $395eec	                    JSL FDC_COMMAND                     ; Issue the command
+.396335		90 05		bcc $39633c	                    BCC pass_failure
+.396337		28		plp		                    PLP
+.396338		2b		pld		                    PLD
+.396339		ab		plb		                    PLB
+.39633a		38		sec		                    SEC
+.39633b		6b		rtl		                    RTL
+.39633c		28		plp		pass_failure        PLP
+.39633d		2b		pld		                    PLD
+.39633e		ab		plb		                    PLB
+.39633f		18		clc		                    CLC
+.396340		6b		rtl		                    RTL
+.396341						FDC_Read_Sector
+.396341		8b		phb		                    PHB
+.396342		0b		phd		                    PHD
+.396343		08		php		                    PHP
+.396344		48		pha		                PHA             ; begin setdbr macro
+.396345		08		php		                PHP
+.396346		e2 20		sep #$20	                SEP #$20        ; set A short
+.396348		a9 00		lda #$00	                LDA #0
+.39634a		48		pha		                PHA
+.39634b		ab		plb		                PLB
+.39634c		28		plp		                PLP
+.39634d		68		pla		                PLA             ; end setdbr macro
+.39634e		48		pha		                PHA             ; begin setdp macro
+.39634f		08		php		                PHP
+.396350		c2 20		rep #$20	                REP #$20        ; set A long
+.396352		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.396355		5b		tcd		                TCD
+.396356		28		plp		                PLP
+.396357		68		pla		                PLA             ; end setdp macro
+.396358		22 9c 60 39	jsl $39609c	                    JSL FDC_MOTOR_NEEDED                ; Reset the spindle motor timeout clock
+.39635c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39635e		a9 06		lda #$06	                    LDA #FDC_CMD_READ_DATA              ; The READ_DATA command
+.396360		09 40		ora #$40	                    ORA #FDC_CMD_MFM                    ; Turn on MFM mode
+.396362		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
+.396365		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Get the head
+.396367		29 01		and #$01	                    AND #$01
+.396369		0a		asl a		                    ASL A
+.39636a		0a		asl a		                    ASL A
+.39636b		05 00		ora $0300	                    ORA FDC_DRIVE                       ; And the drive number
+.39636d		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
+.396370		a5 02		lda $0302	                    LDA FDC_CYLINDER                    ; Send the cylinder number
+.396372		8d 02 05	sta $0502	                    STA FDC_PARAMETERS+2
+.396375		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Send the head number
+.396377		8d 03 05	sta $0503	                    STA FDC_PARAMETERS+3
+.39637a		a5 03		lda $0303	                    LDA FDC_SECTOR                      ; Send the sector number
+.39637c		8d 04 05	sta $0504	                    STA FDC_PARAMETERS+4
+.39637f		a9 02		lda #$02	                    LDA #$02                            ; --- N ---- Sector Size (2 = 512Bytes)
+.396381		8d 05 05	sta $0505	                    STA FDC_PARAMETERS+5
+.396384		a9 12		lda #$12	                    LDA #18                             ; --- EOT ---- End of Track
+.396386		8d 06 05	sta $0506	                    STA FDC_PARAMETERS+6
+.396389		a9 1b		lda #$1b	                    LDA #$1B                            ; --- GPL ---- End of Track
+.39638b		8d 07 05	sta $0507	                    STA FDC_PARAMETERS+7
+.39638e		a9 ff		lda #$ff	                    LDA #$FF                            ; --- DTL ---- Special sector size
+.396390		8d 08 05	sta $0508	                    STA FDC_PARAMETERS+8
+.396393		a9 09		lda #$09	                    LDA #9
+.396395		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 9 parameter (the command)
+.396398		a9 01		lda #$01	                    LDA #1
+.39639a		8d 33 05	sta $0533	                    STA FDC_EXPECT_DAT                  ; Expect data
+.39639d		a9 07		lda #$07	                    LDA #7
+.39639f		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 7 results
+.3963a2		22 ec 5e 39	jsl $395eec	command             JSL FDC_COMMAND                     ; Issue the command
+.3963a6		08		php		                    PHP
+.3963a7		ad 10 05	lda $0510	get_results         LDA FDC_RESULTS
+.3963aa		85 06		sta $0306	                    STA FDC_ST0                         ; --- ST0 ----
+.3963ac		ad 11 05	lda $0511	                    LDA FDC_RESULTS+1
+.3963af		85 07		sta $0307	                    STA FDC_ST1                         ; --- ST1 ----
+.3963b1		ad 12 05	lda $0512	                    LDA FDC_RESULTS+2
+.3963b4		85 08		sta $0308	                    STA FDC_ST2                         ; --- ST2 ----
+.3963b6		ad 13 05	lda $0513	                    LDA FDC_RESULTS+3
+.3963b9		85 02		sta $0302	                    STA FDC_CYLINDER                    ; -- C ---
+.3963bb		ad 14 05	lda $0514	                    LDA FDC_RESULTS+4
+.3963be		85 01		sta $0301	                    STA FDC_HEAD                        ; --- H ---
+.3963c0		ad 15 05	lda $0515	                    LDA FDC_RESULTS+5
+.3963c3		85 0a		sta $030a	                    STA FDC_PCN                      ; --- R ---
+.3963c5		ad 16 05	lda $0516	                    LDA FDC_RESULTS+6
+.3963c8		85 04		sta $0304	                    STA FDC_SECTOR_SIZE                 ; --- N ---
+.3963ca		28		plp		                    PLP
+.3963cb		90 04		bcc $3963d1	                    BCC pass_failure
+.3963cd		28		plp		done                PLP
+.3963ce		2b		pld		                    PLD
+.3963cf		ab		plb		                    PLB
+.3963d0		6b		rtl		                    RTL
+.3963d1		28		plp		pass_failure        PLP
+.3963d2		2b		pld		                    PLD
+.3963d3		ab		plb		                    PLB
+.3963d4		18		clc		                    CLC
+.3963d5		6b		rtl		                    RTL
+.3963d6						FDC_Write_Sector
+.3963d6		8b		phb		                    PHB
+.3963d7		0b		phd		                    PHD
+.3963d8		08		php		                    PHP
+.3963d9		48		pha		                PHA             ; begin setdbr macro
+.3963da		08		php		                PHP
+.3963db		e2 20		sep #$20	                SEP #$20        ; set A short
+.3963dd		a9 00		lda #$00	                LDA #0
+.3963df		48		pha		                PHA
+.3963e0		ab		plb		                PLB
+.3963e1		28		plp		                PLP
+.3963e2		68		pla		                PLA             ; end setdbr macro
+.3963e3		48		pha		                PHA             ; begin setdp macro
+.3963e4		08		php		                PHP
+.3963e5		c2 20		rep #$20	                REP #$20        ; set A long
+.3963e7		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.3963ea		5b		tcd		                TCD
+.3963eb		28		plp		                PLP
+.3963ec		68		pla		                PLA             ; end setdp macro
+.3963ed		e2 20		sep #$20	                SEP #$20        ; set A short
+.3963ef		22 9c 60 39	jsl $39609c	                    JSL FDC_MOTOR_NEEDED                ; Reset the spindle motor timeout clock
+.3963f3		a9 05		lda #$05	                    LDA #FDC_CMD_WRITE_DATA             ; The WRITE_DATA command
+.3963f5		09 40		ora #$40	                    ORA #FDC_CMD_MFM                    ; Turn on MFM mode
+.3963f7		8d 00 05	sta $0500	                    STA FDC_PARAMETERS
+.3963fa		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Get the head
+.3963fc		29 01		and #$01	                    AND #$01
+.3963fe		0a		asl a		                    ASL A
+.3963ff		0a		asl a		                    ASL A
+.396400		05 00		ora $0300	                    ORA FDC_DRIVE                       ; And the drive number
+.396402		8d 01 05	sta $0501	                    STA FDC_PARAMETERS+1
+.396405		a5 02		lda $0302	                    LDA FDC_CYLINDER                    ; Send the cylinder number
+.396407		8d 02 05	sta $0502	                    STA FDC_PARAMETERS+2
+.39640a		a5 01		lda $0301	                    LDA FDC_HEAD                        ; Send the head number
+.39640c		8d 03 05	sta $0503	                    STA FDC_PARAMETERS+3
+.39640f		a5 03		lda $0303	                    LDA FDC_SECTOR                      ; Send the sector number
+.396411		8d 04 05	sta $0504	                    STA FDC_PARAMETERS+4
+.396414		a9 02		lda #$02	                    LDA #$02                            ; --- N ---- Sector Size (2 = 512Bytes)
+.396416		8d 05 05	sta $0505	                    STA FDC_PARAMETERS+5
+.396419		a9 12		lda #$12	                    LDA #18                             ; --- EOT ---- End of Track
+.39641b		8d 06 05	sta $0506	                    STA FDC_PARAMETERS+6
+.39641e		a9 1b		lda #$1b	                    LDA #$1B                            ; --- GPL ---- End of Track
+.396420		8d 07 05	sta $0507	                    STA FDC_PARAMETERS+7
+.396423		a9 ff		lda #$ff	                    LDA #$FF                            ; --- DTL ---- Special sector size
+.396425		8d 08 05	sta $0508	                    STA FDC_PARAMETERS+8
+.396428		a9 09		lda #$09	                    LDA #9
+.39642a		8d 30 05	sta $0530	                    STA FDC_PARAM_NUM                   ; 9 parameter (the command)
+.39642d		a9 ff		lda #$ff	                    LDA #$FF
+.39642f		8d 33 05	sta $0533	                    STA FDC_EXPECT_DAT                  ; Expect to write data
+.396432		a9 07		lda #$07	                    LDA #7
+.396434		8d 32 05	sta $0532	                    STA FDC_RESULT_NUM                  ; 7 results
+.396437		22 ec 5e 39	jsl $395eec	command             JSL FDC_COMMAND                     ; Issue the command
+.39643b		08		php		                    PHP
+.39643c		ad 10 05	lda $0510	get_results         LDA FDC_RESULTS
+.39643f		85 06		sta $0306	                    STA FDC_ST0                         ; --- ST0 ---
+.396441		ad 11 05	lda $0511	                    LDA FDC_RESULTS+1
+.396444		85 07		sta $0307	                    STA FDC_ST1                         ; --- ST1 ---
+.396446		ad 12 05	lda $0512	                    LDA FDC_RESULTS+2
+.396449		85 08		sta $0308	                    STA FDC_ST2                         ; --- ST2 ---
+.39644b		ad 13 05	lda $0513	                    LDA FDC_RESULTS+3
+.39644e		85 02		sta $0302	                    STA FDC_CYLINDER                    ; --- C ---
+.396450		ad 14 05	lda $0514	                    LDA FDC_RESULTS+4
+.396453		85 01		sta $0301	                    STA FDC_HEAD                        ; --- H ---
+.396455		ad 15 05	lda $0515	                    LDA FDC_RESULTS+5
+.396458		85 0a		sta $030a	                    STA FDC_PCN                      ; --- R ---
+.39645a		ad 16 05	lda $0516	                    LDA FDC_RESULTS+6
+.39645d		85 04		sta $0304	                    STA FDC_SECTOR_SIZE                 ; --- N ---
+.39645f		28		plp		check_status        PLP
+.396460		90 04		bcc $396466	                    BCC pass_failure
+.396462		28		plp		done                PLP
+.396463		2b		pld		                    PLD
+.396464		ab		plb		                    PLB
+.396465		6b		rtl		                    RTL
+.396466		28		plp		pass_failure        PLP
+.396467		2b		pld		                    PLD
+.396468		ab		plb		                    PLB
+.396469		18		clc		                    CLC
+.39646a		6b		rtl		                    RTL
+.39646b						DIVIDE32
+.39646b		da		phx		                    PHX
+.39646c		5a		phy		                    PHY
+.39646d		0b		phd		                    PHD
+.39646e		08		php		                    PHP
+.39646f		48		pha		                PHA             ; begin setdp macro
+.396470		08		php		                PHP
+.396471		c2 20		rep #$20	                REP #$20        ; set A long
+.396473		a9 0c 03	lda #$030c	                LDA #DIVIDEND         ; set DP to page 0
+.396476		5b		tcd		                TCD
+.396477		28		plp		                PLP
+.396478		68		pla		                PLA             ; end setdp macro
+.396479		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39647b		64 08		stz $0314	                    STZ REMAINDER           ; Initialize the remainder
+.39647d		64 0a		stz $0316	                    STZ REMAINDER+2
+.39647f		a2 20 00	ldx #$0020	                    LDX #32                 ; Set the number of bits to process
+.396482		06 00		asl $030c	loop                ASL DIVIDEND
+.396484		26 02		rol $030e	                    ROL DIVIDEND+2
+.396486		26 08		rol $0314	                    ROL REMAINDER
+.396488		26 0a		rol $0316	                    ROL REMAINDER+2
+.39648a		a5 08		lda $0314	                    LDA REMAINDER
+.39648c		38		sec		                    SEC
+.39648d		e5 04		sbc $0310	                    SBC DIVISOR
+.39648f		a8		tay		                    TAY
+.396490		a5 0a		lda $0316	                    LDA REMAINDER+2
+.396492		e5 06		sbc $0312	                    SBC DIVISOR+2
+.396494		90 06		bcc $39649c	                    BCC skip
+.396496		85 0a		sta $0316	                    STA REMAINDER+2
+.396498		84 08		sty $0314	                    STY REMAINDER
+.39649a		e6 00		inc $030c	                    INC DIVIDEND
+.39649c		ca		dex		skip                DEX
+.39649d		d0 e3		bne $396482	                    BNE loop
+.39649f		28		plp		                    PLP
+.3964a0		2b		pld		                    PLD
+.3964a1		7a		ply		                    PLY
+.3964a2		fa		plx		                    PLX
+.3964a3		60		rts		                    RTS
+.3964a4						LBA2CHS
+.3964a4		8b		phb		                    PHB
+.3964a5		0b		phd		                    PHD
+.3964a6		08		php		                    PHP
+.3964a7		48		pha		                PHA             ; begin setdbr macro
+.3964a8		08		php		                PHP
+.3964a9		e2 20		sep #$20	                SEP #$20        ; set A short
+.3964ab		a9 00		lda #$00	                LDA #0
+.3964ad		48		pha		                PHA
+.3964ae		ab		plb		                PLB
+.3964af		28		plp		                PLP
+.3964b0		68		pla		                PLA             ; end setdbr macro
+.3964b1		48		pha		                PHA             ; begin setdp macro
+.3964b2		08		php		                PHP
+.3964b3		c2 20		rep #$20	                REP #$20        ; set A long
+.3964b5		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.3964b8		5b		tcd		                TCD
+.3964b9		28		plp		                PLP
+.3964ba		68		pla		                PLA             ; end setdp macro
+.3964bb		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3964bd		a5 22		lda $0322	                    LDA BIOS_LBA
+.3964bf		85 0c		sta $030c	                    STA DIVIDEND
+.3964c1		a5 24		lda $0324	                    LDA BIOS_LBA+2
+.3964c3		85 0e		sta $030e	                    STA DIVIDEND+2
+.3964c5		a9 24 00	lda #$0024	                    LDA #36
+.3964c8		85 10		sta $0310	                    STA DIVISOR
+.3964ca		64 12		stz $0312	                    STZ DIVISOR+2
+.3964cc		20 6b 64	jsr $39646b	                    JSR DIVIDE32
+.3964cf		e2 20		sep #$20	                SEP #$20        ; set A short
+.3964d1		a5 0c		lda $030c	                    LDA DIVIDEND
+.3964d3		85 02		sta $0302	                    STA FDC_CYLINDER
+.3964d5		c2 20		rep #$20	                REP #$20        ; set A long
+.3964d7		a5 14		lda $0314	                    LDA REMAINDER
+.3964d9		85 0c		sta $030c	                    STA DIVIDEND
+.3964db		a5 16		lda $0316	                    LDA REMAINDER+2
+.3964dd		85 0e		sta $030e	                    STA DIVIDEND+2
+.3964df		a9 12 00	lda #$0012	                    LDA #18
+.3964e2		85 10		sta $0310	                    STA DIVISOR
+.3964e4		64 12		stz $0312	                    STZ DIVISOR+2
+.3964e6		20 6b 64	jsr $39646b	                    JSR DIVIDE32
+.3964e9		e2 20		sep #$20	                SEP #$20        ; set A short
+.3964eb		a5 0c		lda $030c	                    LDA DIVIDEND
+.3964ed		29 01		and #$01	                    AND #$01
+.3964ef		85 01		sta $0301	                    STA FDC_HEAD
+.3964f1		a5 14		lda $0314	                    LDA REMAINDER
+.3964f3		1a		inc a		                    INC A
+.3964f4		85 03		sta $0303	                    STA FDC_SECTOR
+.3964f6		28		plp		                    PLP
+.3964f7		2b		pld		                    PLD
+.3964f8		ab		plb		                    PLB
+.3964f9		6b		rtl		                    RTL
+.3964fa						FDC_GETBLOCK
+.3964fa		8b		phb		                    PHB
+.3964fb		0b		phd		                    PHD
+.3964fc		08		php		                    PHP
+.3964fd		48		pha		                PHA             ; begin setdbr macro
+.3964fe		08		php		                PHP
+.3964ff		e2 20		sep #$20	                SEP #$20        ; set A short
+.396501		a9 00		lda #$00	                LDA #0
+.396503		48		pha		                PHA
+.396504		ab		plb		                PLB
+.396505		28		plp		                PLP
+.396506		68		pla		                PLA             ; end setdbr macro
+.396507		48		pha		                PHA             ; begin setdp macro
+.396508		08		php		                PHP
+.396509		c2 20		rep #$20	                REP #$20        ; set A long
+.39650b		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.39650e		5b		tcd		                TCD
+.39650f		28		plp		                PLP
+.396510		68		pla		                PLA             ; end setdp macro
+.396511		e2 20		sep #$20	                SEP #$20        ; set A short
+.396513		a9 03		lda #$03	                    LDA #3                      ; We can retry 3 times
+.396515		8d 34 05	sta $0534	                    STA FDC_CMD_RETRY
+.396518		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39651a		22 a4 64 39	jsl $3964a4	                    JSL LBA2CHS                 ; Convert the LBA to CHS
+.39651e		e2 20		sep #$20	                SEP #$20        ; set A short
+.396520		a5 03		lda $0303	                    LDA FDC_SECTOR              ; Just make sure the sector is ok
+.396522		f0 29		beq $39654d	                    BEQ read_failure
+.396524						try_read
+.396524		c2 20		rep #$20	                REP #$20        ; set A long
+.396526		22 41 63 39	jsl $396341	                    JSL FDC_Read_Sector         ; Read the sector
+.39652a		90 14		bcc $396540	                    BCC retry
+.39652c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39652e		a5 06		lda $0306	                    LDA FDC_ST0
+.396530		29 d0		and #$d0	                    AND #%11010000              ; Check the error bits
+.396532		d0 19		bne $39654d	                    BNE read_failure
+.396534						ret_success
+.396534		e2 20		sep #$20	                SEP #$20        ; set A short
+.396536		a9 00		lda #$00	                    LDA #0
+.396538		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
+.39653b		28		plp		                    PLP
+.39653c		2b		pld		                    PLD
+.39653d		ab		plb		                    PLB
+.39653e		38		sec		                    SEC
+.39653f		6b		rtl		                    RTL
+.396540						retry
+.396540		e2 20		sep #$20	                SEP #$20        ; set A short
+.396542		ce 34 05	dec $0534	                    DEC FDC_CMD_RETRY           ; Decrement the retry counter
+.396545		30 13		bmi $39655a	                    BMI pass_failure            ; If it's gone negative, we should quit with an error
+.396547		22 39 60 39	jsl $396039	                    JSL FDC_INIT                ; Otherwise, reinitialize the FDC
+.39654b		80 d7		bra $396524	                    BRA try_read                ; And try the read again
+.39654d						read_failure
+.39654d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39654f		a9 82		lda #$82	                    LDA #BIOS_ERR_READ
+.396551		80 04		bra $396557	                    BRA ret_failure
+.396553						seek_failure
+.396553		e2 20		sep #$20	                SEP #$20        ; set A short
+.396555		a9 84		lda #$84	                    LDA #BIOS_ERR_TRACK
+.396557		8d 20 03	sta $0320	ret_failure         STA @w BIOS_STATUS
+.39655a		28		plp		pass_failure        PLP
+.39655b		2b		pld		                    PLD
+.39655c		ab		plb		                    PLB
+.39655d		18		clc		                    CLC
+.39655e		6b		rtl		                    RTL
+.39655f						FDC_PUTBLOCK
+.39655f		8b		phb		                    PHB
+.396560		0b		phd		                    PHD
+.396561		08		php		                    PHP
+.396562		48		pha		                PHA             ; begin setdbr macro
+.396563		08		php		                PHP
+.396564		e2 20		sep #$20	                SEP #$20        ; set A short
+.396566		a9 00		lda #$00	                LDA #0
+.396568		48		pha		                PHA
+.396569		ab		plb		                PLB
+.39656a		28		plp		                PLP
+.39656b		68		pla		                PLA             ; end setdbr macro
+.39656c		48		pha		                PHA             ; begin setdp macro
+.39656d		08		php		                PHP
+.39656e		c2 20		rep #$20	                REP #$20        ; set A long
+.396570		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.396573		5b		tcd		                TCD
+.396574		28		plp		                PLP
+.396575		68		pla		                PLA             ; end setdp macro
+.396576		e2 20		sep #$20	                SEP #$20        ; set A short
+.396578		a9 03		lda #$03	                    LDA #3                      ; Set the number of retries we're willing to do
+.39657a		8d 34 05	sta $0534	                    STA @w FDC_CMD_RETRY
+.39657d		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39657f		22 a4 64 39	jsl $3964a4	                    JSL LBA2CHS                 ; Convert the LBA to CHS
+.396583		22 d6 63 39	jsl $3963d6	retry               JSL FDC_Write_Sector        ; Write the sector
+.396587		b0 03		bcs $39658c	                    BCS chk_st0
+.396589		82 28 00	brl $3965b4	                    BRL attempt_retry
+.39658c						chk_st0
+.39658c		e2 20		sep #$20	                SEP #$20        ; set A short
+.39658e		a5 06		lda $0306	                    LDA FDC_ST0
+.396590		29 d0		and #$d0	                    AND #%11010000              ; Check the error bits
+.396592		d0 0c		bne $3965a0	                    BNE write_failure
+.396594						ret_success
+.396594		e2 20		sep #$20	                SEP #$20        ; set A short
+.396596		a9 00		lda #$00	                    LDA #0
+.396598		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
+.39659b		28		plp		                    PLP
+.39659c		2b		pld		                    PLD
+.39659d		ab		plb		                    PLB
+.39659e		38		sec		                    SEC
+.39659f		6b		rtl		                    RTL
+.3965a0						write_failure
+.3965a0		e2 20		sep #$20	                SEP #$20        ; set A short
+.3965a2		a5 07		lda $0307	                    LDA FDC_ST1                         ; Check ST1 for write protect
+.3965a4		89 02		bit #$02	                    BIT #FDC_ST1_NW
+.3965a6		f0 04		beq $3965ac	                    BEQ generic_err
+.3965a8		a9 86		lda #$86	                    LDA #BIOS_ERR_WRITEPROT             ; Yes: return a write-protect error
+.3965aa		80 17		bra $3965c3	                    BRA ret_failure
+.3965ac		89 10		bit #$10	generic_err         BIT #FDC_ST1_OR                     ; TODO: properly handle over/under run errors
+.3965ae		d0 e4		bne $396594	                    BNE ret_success
+.3965b0		89 80		bit #$80	                    BIT #FDC_ST1_EN                     ; TODO: properly handle end-of-track
+.3965b2		d0 e0		bne $396594	                    BNE ret_success
+.3965b4						attempt_retry
+.3965b4		e2 20		sep #$20	                SEP #$20        ; set A short
+.3965b6		ce 34 05	dec $0534	                    DEC @w FDC_CMD_RETRY                ; Count down the retries
+.3965b9		d0 c8		bne $396583	                    BNE retry                           ; And retry unless we have none left
+.3965bb		a9 83		lda #$83	                    LDA #BIOS_ERR_WRITE                 ; Otherwise: return a generic write error
+.3965bd		80 04		bra $3965c3	                    BRA ret_failure
+.3965bf						seek_failure
+.3965bf		e2 20		sep #$20	                SEP #$20        ; set A short
+.3965c1		a9 84		lda #$84	                    LDA #BIOS_ERR_TRACK
+.3965c3						ret_failure
+.3965c3		8d 20 03	sta $0320	                    STA @w BIOS_STATUS
+.3965c6		28		plp		pass_failure        PLP
+.3965c7		2b		pld		                    PLD
+.3965c8		ab		plb		                    PLB
+.3965c9		18		clc		                    CLC
+.3965ca		6b		rtl		                    RTL
+.3965cb						FDC_MOUNT
+.3965cb		8b		phb		                    PHB
+.3965cc		0b		phd		                    PHD
+.3965cd		08		php		                    PHP
+.3965ce		48		pha		                PHA             ; begin setdbr macro
+.3965cf		08		php		                PHP
+.3965d0		e2 20		sep #$20	                SEP #$20        ; set A short
+.3965d2		a9 00		lda #$00	                LDA #0
+.3965d4		48		pha		                PHA
+.3965d5		ab		plb		                PLB
+.3965d6		28		plp		                PLP
+.3965d7		68		pla		                PLA             ; end setdbr macro
+.3965d8		48		pha		                PHA             ; begin setdp macro
+.3965d9		08		php		                PHP
+.3965da		c2 20		rep #$20	                REP #$20        ; set A long
+.3965dc		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.3965df		5b		tcd		                TCD
+.3965e0		28		plp		                PLP
+.3965e1		68		pla		                PLA             ; end setdp macro
+.3965e2		22 39 60 39	jsl $396039	                    JSL FDC_INIT
+.3965e6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3965e8		c2 10		rep #$10	                REP #$10        ; set X long
+.3965ea		a9 00		lda #$00	                    LDA #0
+.3965ec		a2 00 00	ldx #$0000	                    LDX #0
+.3965ef		9f 00 a3 38	sta $38a300,x	zero_loop           STA DOS_SECTOR,X
+.3965f3		e8		inx		                    INX
+.3965f4		e0 00 02	cpx #$0200	                    CPX #512
+.3965f7		d0 f6		bne $3965ef	                    BNE zero_loop
+.3965f9		a9 00		lda #$00	                    LDA #0                                  ; We only support drive 0
+.3965fb		85 00		sta $0300	                    STA FDC_DRIVE
+.3965fd		22 b5 60 39	jsl $3960b5	                    JSL FDC_Motor_On                        ; Turn the motor on
+.396601		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396603		a9 00 00	lda #$0000	                    LDA #0                                  ; We want sector 0
+.396606		85 22		sta $0322	                    STA BIOS_LBA
+.396608		85 24		sta $0324	                    STA BIOS_LBA+2
+.39660a		a9 00 a3	lda #$a300	                    LDA #<>DOS_SECTOR                       ; And load it into DOS_SECTOR
+.39660d		85 26		sta $0326	                    STA BIOS_BUFF_PTR
+.39660f		a9 38 00	lda #$0038	                    LDA #`DOS_SECTOR
+.396612		85 28		sta $0328	                    STA BIOS_BUFF_PTR+2
+.396614		22 fa 64 39	jsl $3964fa	                    JSL FDC_GETBLOCK                        ; Attempt to read the data
+.396618		b0 03		bcs $39661d	                    BCS parse_boot                          ; If ok: start parsing the boot record
+.39661a		82 d3 00	brl $3966f0	                    BRL pass_failure                        ; Pass the error up the chain
+.39661d						parse_boot
+.39661d		e2 20		sep #$20	                SEP #$20        ; set A short
+.39661f		a9 00		lda #$00	                    LDA #PART_TYPE_FAT12                    ; Set the file system to FAT12
+.396621		8f 01 a0 38	sta $38a001	                    STA @l FILE_SYSTEM
+.396625		a9 00		lda #$00	                    LDA #0                                  ; There are no partitions on the disk
+.396627		8f 02 a0 38	sta $38a002	                    STA @l PARTITION
+.39662b		e2 20		sep #$20	                SEP #$20        ; set A short
+.39662d		af 0d a3 38	lda $38a30d	                    LDA DOS_SECTOR+BPB_SECPERCLUS12_OFF     ; Get the # of sectors per cluster (usually 1)
+.396631		8f 03 a0 38	sta $38a003	                    STA @l SECTORS_PER_CLUSTER
+.396635		c2 20		rep #$20	                REP #$20        ; set A long
+.396637		a9 00 00	lda #$0000	                    LDA #0                                  ; First sector of the "partition" is 0
+.39663a		8f 04 a0 38	sta $38a004	                    STA @l FIRSTSECTOR
+.39663e		8f 06 a0 38	sta $38a006	                    STA @l FIRSTSECTOR+2
+.396642		af 16 a3 38	lda $38a316	                    LDA DOS_SECTOR+BPB_SECPERFAT12_OFF      ; Get the number of sectors per FAT
+.396646		8f 10 a0 38	sta $38a010	                    STA @l SEC_PER_FAT
+.39664a		a9 00 00	lda #$0000	                    LDA #0
+.39664d		8f 12 a0 38	sta $38a012	                    STA @l SEC_PER_FAT+2
+.396651		a9 01 00	lda #$0001	                    LDA #1                                  ; FAT#1 begins at sector 1
+.396654		8f 14 a0 38	sta $38a014	                    STA @l FAT_BEGIN_LBA
+.396658		18		clc		                    CLC
+.396659		6f 10 a0 38	adc $38a010	                    ADC @l SEC_PER_FAT
+.39665d		8f 18 a0 38	sta $38a018	                    STA @l FAT2_BEGIN_LBA                   ; FAT#2 begins SEC_PER_FAT sectors later
+.396661		a9 00 00	lda #$0000	                    LDA #0
+.396664		8f 16 a0 38	sta $38a016	                    STA @l FAT_BEGIN_LBA+2
+.396668		8f 1a a0 38	sta $38a01a	                    STA @L FAT2_BEGIN_LBA+2
+.39666c		18		clc		                    CLC                                     ; Calculate the root directory's starting sector
+.39666d		af 18 a0 38	lda $38a018	                    LDA @l FAT2_BEGIN_LBA
+.396671		6f 10 a0 38	adc $38a010	                    ADC @l SEC_PER_FAT
+.396675		8f 20 a0 38	sta $38a020	                    STA @l ROOT_DIR_FIRST_CLUSTER           ; ROOT_DIR_FIRST_CLUSTER will be a sector LBA for FAT12!
+.396679		a9 00 00	lda #$0000	                    LDA #0
+.39667c		8f 22 a0 38	sta $38a022	                    STA @l ROOT_DIR_FIRST_CLUSTER+2
+.396680		af 11 a3 38	lda $38a311	                    LDA DOS_SECTOR+BPB_ROOT_MAX_ENTRY12_OFF ; Get the maximum number of directory entries for the root dir
+.396684		8f 24 a0 38	sta $38a024	                    STA @l ROOT_DIR_MAX_ENTRY
+.396688		4a		lsr a		                    LSR A                                   ; 16 entries per sector
+.396689		4a		lsr a		                    LSR A
+.39668a		4a		lsr a		                    LSR A
+.39668b		4a		lsr a		                    LSR A                                   ; So now A is the number of sectors in the root directory
+.39668c		18		clc		                    CLC
+.39668d		6f 20 a0 38	adc $38a020	                    ADC @L ROOT_DIR_FIRST_CLUSTER           ; Add that to the first sector LBA for the root directory
+.396691		8f 1c a0 38	sta $38a01c	                    STA @l CLUSTER_BEGIN_LBA                ; And that is the LBA for the first cluster
+.396695		a9 00 00	lda #$0000	                    LDA #0
+.396698		8f 1e a0 38	sta $38a01e	                    STA @l CLUSTER_BEGIN_LBA+2
+.39669c		af 13 a3 38	lda $38a313	                    LDA DOS_SECTOR+BPB_TOTAL_SECTORS        ; Set the sector limit
+.3966a0		8f 08 a0 38	sta $38a008	                    STA @l SECTORCOUNT
+.3966a4		a9 00 00	lda #$0000	                    LDA #0
+.3966a7		8f 0a a0 38	sta $38a00a	                    STA @l SECTORCOUNT+2
+.3966ab		af 0e a3 38	lda $38a30e	                    LDA DOS_SECTOR+BPB_RSRVCLUS_OFF         ; Get the number of reserved clusters
+.3966af		8f 0c a0 38	sta $38a00c	                    STA @l NUM_RSRV_SEC
+.3966b3		a9 00 02	lda #$0200	                    LDA #DOS_SECTOR_SIZE                    ; Set the size of a FAT12 cluster
+.3966b6		8f 0e a0 38	sta $38a00e	                    STA @l CLUSTER_SIZE
+.3966ba		e2 20		sep #$20	                SEP #$20        ; set A short
+.3966bc		af 26 a3 38	lda $38a326	                    LDA DOS_SECTOR+BPB_SIGNATUREB           ; Is signature B $29?
+.3966c0		c9 29		cmp #$29	                    CMP #BPB_EXTENDED_RECORD
+.3966c2		80 14		bra $3966d8	                    BRA no_volume_id                        ; No: there is no volume ID
+.3966c4						is_extended
+.3966c4		c2 20		rep #$20	                REP #$20        ; set A long
+.3966c6		af 27 a3 38	lda $38a327	                    LDA DOS_SECTOR+BPB_VOLUMEID             ; Yes: set the volume ID
+.3966ca		8f 26 a0 38	sta $38a026	                    STA @l VOLUME_ID
+.3966ce		af 29 a3 38	lda $38a329	                    LDA DOS_SECTOR+BPB_VOLUMEID+2
+.3966d2		8f 28 a0 38	sta $38a028	                    STA @l VOLUME_ID+2
+.3966d6		80 0d		bra $3966e5	                    BRA ret_success
+.3966d8						no_volume_id
+.3966d8		c2 20		rep #$20	                REP #$20        ; set A long
+.3966da		a9 00 00	lda #$0000	                    LDA #0                                  ; No: blank the Volume ID
+.3966dd		8f 26 a0 38	sta $38a026	                    STA @l VOLUME_ID
+.3966e1		8f 28 a0 38	sta $38a028	                    STA @L VOLUME_ID+2
+.3966e5						ret_success
+.3966e5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3966e7		a9 00		lda #$00	                    LDA #0
+.3966e9		85 20		sta $0320	                    STA BIOS_STATUS
+.3966eb		28		plp		                    PLP
+.3966ec		2b		pld		                    PLD
+.3966ed		ab		plb		                    PLB
+.3966ee		38		sec		                    SEC
+.3966ef		6b		rtl		                    RTL
+.3966f0		28		plp		pass_failure        PLP
+.3966f1		2b		pld		                    PLD
+.3966f2		ab		plb		                    PLB
+.3966f3		18		clc		                    CLC
+.3966f4		6b		rtl		                    RTL
+.3966f5						FDC_CMDBLOCK
+.3966f5		8b		phb		                    PHB
+.3966f6		0b		phd		                    PHD
+.3966f7		08		php		                    PHP
+.3966f8		48		pha		                PHA             ; begin setdbr macro
+.3966f9		08		php		                PHP
+.3966fa		e2 20		sep #$20	                SEP #$20        ; set A short
+.3966fc		a9 00		lda #$00	                LDA #0
+.3966fe		48		pha		                PHA
+.3966ff		ab		plb		                PLB
+.396700		28		plp		                PLP
+.396701		68		pla		                PLA             ; end setdbr macro
+.396702		48		pha		                PHA             ; begin setdp macro
+.396703		08		php		                PHP
+.396704		c2 20		rep #$20	                REP #$20        ; set A long
+.396706		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.396709		5b		tcd		                TCD
+.39670a		28		plp		                PLP
+.39670b		68		pla		                PLA             ; end setdp macro
+.39670c		e2 30		sep #$30	                SEP #$30        ; set A&X short
+.39670e		e0 01		cpx #$01	                    CPX #FDC_DEVCMD_MOTOR_ON
+.396710		f0 0f		beq $396721	                    BEQ motor_on
+.396712		e0 02		cpx #$02	                    CPX #FDC_DEVCMD_MOTOR_OFF
+.396714		f0 11		beq $396727	                    BEQ motor_off
+.396716		e0 03		cpx #$03	                    CPX #FDC_DEVCMD_RECAL
+.396718		f0 13		beq $39672d	                    BEQ recalibrate
+.39671a		64 20		stz $0320	ret_success         STZ BIOS_STATUS
+.39671c		28		plp		                    PLP
+.39671d		2b		pld		                    PLD
+.39671e		ab		plb		                    PLB
+.39671f		38		sec		                    SEC
+.396720		6b		rtl		                    RTL
+.396721		22 b5 60 39	jsl $3960b5	motor_on            JSL FDC_Motor_On
+.396725		80 f3		bra $39671a	                    BRA ret_success
+.396727		22 e9 60 39	jsl $3960e9	motor_off           JSL FDC_Motor_Off
+.39672b		80 ed		bra $39671a	                    BRA ret_success
+.39672d		22 14 61 39	jsl $396114	recalibrate         JSL FDC_Recalibrate_Command
+.396731		b0 e7		bcs $39671a	                    BCS ret_success
+.396733		28		plp		pass_failure        PLP
+.396734		2b		pld		                    PLD
+.396735		ab		plb		                    PLB
+.396736		18		clc		                    CLC
+.396737		6b		rtl		                    RTL
+.396738						FDC_CHK_MEDIA
+.396738		0b		phd		                    PHD
+.396739		08		php		                    PHP
+.39673a		48		pha		                PHA             ; begin setdp macro
+.39673b		08		php		                PHP
+.39673c		c2 20		rep #$20	                REP #$20        ; set A long
+.39673e		a9 00 03	lda #$0300	                LDA #FDC_DRIVE         ; set DP to page 0
+.396741		5b		tcd		                TCD
+.396742		28		plp		                PLP
+.396743		68		pla		                PLA             ; end setdp macro
+.396744		22 b5 60 39	jsl $3960b5	                    JSL FDC_Motor_On                ; Turn on the motor
+.396748		e2 20		sep #$20	                SEP #$20        ; set A short
+.39674a		af f7 13 af	lda $af13f7	                    LDA @l SIO_FDC_DIR              ; Check if the DSKCHG bit is set
+.39674e		89 80		bit #$80	                    BIT #FDC_DIR_DSKCHG
+.396750		f0 42		beq $396794	                    BEQ ret_true                    ; If not: assume the disk is present
+.396752		a9 00		lda #$00	                    LDA #0
+.396754		85 00		sta $0300	                    STA FDC_DRIVE
+.396756		a9 00		lda #$00	                    LDA #0
+.396758		85 01		sta $0301	                    STA FDC_HEAD
+.39675a		a9 50		lda #$50	                    LDA #80
+.39675c		85 02		sta $0302	                    STA FDC_CYLINDER
+.39675e		22 f4 62 39	jsl $3962f4	                    JSL FDC_Seek_Track              ; Attempt to seek to track 80
+.396762		90 34		bcc $396798	                    BCC ret_false                   ; If fail: return false
+.396764		c2 10		rep #$10	                REP #$10        ; set X long
+.396766		a2 1e 8b	ldx #$8b1e	                    LDX #<>FDC_MOTOR_TIME       ; Wait a suitable time for the motor to spin up
+.396769		a0 41 00	ldy #$0041	                    LDY #`FDC_MOTOR_TIME
+.39676c		22 3c 14 39	jsl $39143c	                    JSL IDELAY
+.396770		22 49 61 39	jsl $396149	                    JSL FDC_Sense_Int_Status
+.396774		a5 06		lda $0306	                    LDA FDC_ST0
+.396776		29 d0		and #$d0	                    AND #%11010000
+.396778		d0 1e		bne $396798	                    BNE ret_false
+.39677a		22 14 61 39	jsl $396114	                    JSL FDC_Recalibrate_Command     ; Attempt to recalibrate
+.39677e		90 18		bcc $396798	                    BCC ret_false                   ; If fail: return false
+.396780		a2 1e 8b	ldx #$8b1e	                    LDX #<>FDC_MOTOR_TIME       ; Wait a suitable time for the motor to spin up
+.396783		a0 41 00	ldy #$0041	                    LDY #`FDC_MOTOR_TIME
+.396786		22 3c 14 39	jsl $39143c	                    JSL IDELAY
+.39678a		22 49 61 39	jsl $396149	                    JSL FDC_Sense_Int_Status
+.39678e		a5 06		lda $0306	                    LDA FDC_ST0
+.396790		29 d0		and #$d0	                    AND #%11010000
+.396792		d0 04		bne $396798	                    BNE ret_false
+.396794						ret_true
+.396794		28		plp		                    PLP
+.396795		2b		pld		                    PLD
+.396796		38		sec		                    SEC
+.396797		6b		rtl		                    RTL
+.396798						ret_false
+.396798		28		plp		                    PLP
+.396799		2b		pld		                    PLD
+.39679a		18		clc		                    CLC
+.39679b		6b		rtl		                    RTL
+.39679c						FDC_WRITEVBR
+.39679c		8b		phb		                    PHB
+.39679d		0b		phd		                    PHD
+.39679e		08		php		                    PHP
+.39679f		48		pha		                PHA             ; begin setdbr macro
+.3967a0		08		php		                PHP
+.3967a1		e2 20		sep #$20	                SEP #$20        ; set A short
+.3967a3		a9 00		lda #$00	                LDA #0
+.3967a5		48		pha		                PHA
+.3967a6		ab		plb		                PLB
+.3967a7		28		plp		                PLP
+.3967a8		68		pla		                PLA             ; end setdbr macro
+.3967a9		48		pha		                PHA             ; begin setdp macro
+.3967aa		08		php		                PHP
+.3967ab		c2 20		rep #$20	                REP #$20        ; set A long
+.3967ad		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.3967b0		5b		tcd		                TCD
+.3967b1		28		plp		                PLP
+.3967b2		68		pla		                PLA             ; end setdp macro
+.3967b3		22 cb 65 39	jsl $3965cb	                    JSL FDC_MOUNT               ; Mount the floppy disk
+.3967b7		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3967b9		a9 00 00	lda #$0000	                    LDA #0                      ; Clear the sector buffer
+.3967bc		a2 00 00	ldx #$0000	                    LDX #0
+.3967bf		9f 00 a3 38	sta $38a300,x	clr_loop            STA DOS_SECTOR,X
+.3967c3		e8		inx		                    INX
+.3967c4		e8		inx		                    INX
+.3967c5		e0 00 02	cpx #$0200	                    CPX #512
+.3967c8		d0 f5		bne $3967bf	                    BNE clr_loop
+.3967ca		e2 20		sep #$20	                SEP #$20        ; set A short
+.3967cc		a2 00 00	ldx #$0000	                    LDX #0                      ; Copy the prototype VBR to the sector buffer
+.3967cf		bf 84 68 39	lda $396884,x	copy_loop           LDA FDC_VBR_BEGIN,X
+.3967d3		9f 00 a3 38	sta $38a300,x	                    STA DOS_SECTOR,X
+.3967d7		e8		inx		                    INX
+.3967d8		e0 c9 00	cpx #$00c9	                    CPX #<>(FDC_VBR_END - FDC_VBR_BEGIN + 1)
+.3967db		d0 f2		bne $3967cf	                    BNE copy_loop
+.3967dd		a0 00 00	ldy #$0000	                    LDY #0                      ; Copy the boot binary path to the VBR
+.3967e0		a2 40 00	ldx #$0040	                    LDX #FDC_VBR_PATH
+.3967e3		b7 3c		lda [$035c],y	path_copy_loop      LDA [DOS_RUN_PTR],Y
+.3967e5		9f 00 a3 38	sta $38a300,x	                    STA DOS_SECTOR,X
+.3967e9		f0 07		beq $3967f2	                    BEQ path_copy_done
+.3967eb		e8		inx		                    INX
+.3967ec		c8		iny		                    INY
+.3967ed		c0 80 00	cpy #$0080	                    CPY #128
+.3967f0		d0 f1		bne $3967e3	                    BNE path_copy_loop
+.3967f2						path_copy_done
+.3967f2		c2 20		rep #$20	                REP #$20        ; set A long
+.3967f4		a9 55 aa	lda #$aa55	                    LDA #$AA55                  ; Set the VBR signature bytes at the end
+.3967f7		8f fe a4 38	sta $38a4fe	                    STA DOS_SECTOR+BPB_SIGNATURE
+.3967fb		c2 20		rep #$20	                REP #$20        ; set A long
+.3967fd		a9 00 a3	lda #$a300	                    LDA #<>DOS_SECTOR           ; Point to the BIOS buffer
+.396800		85 06		sta $0326	                    STA BIOS_BUFF_PTR
+.396802		a9 38 00	lda #$0038	                    LDA #`DOS_SECTOR
+.396805		85 08		sta $0328	                    STA BIOS_BUFF_PTR+2
+.396807		a9 00 00	lda #$0000	                    LDA #0                      ; Set the sector to #0 (boot record)
+.39680a		85 02		sta $0322	                    STA BIOS_LBA
+.39680c		85 04		sta $0324	                    STA BIOS_LBA+2
+.39680e		e2 20		sep #$20	                SEP #$20        ; set A short
+.396810		a9 00		lda #$00	                    LDA #BIOS_DEV_FDC
+.396812		85 01		sta $0321	                    STA BIOS_DEV
+.396814		22 24 10 00	jsl $001024	                    JSL PUTBLOCK                ; Attempt to write the boot record
+.396818		b0 09		bcs $396823	                    BCS ret_success
+.39681a		22 e9 60 39	jsl $3960e9	                    JSL FDC_Motor_Off
+.39681e		28		plp		                    PLP                         ; Return the failure
+.39681f		2b		pld		                    PLD
+.396820		ab		plb		                    PLB
+.396821		18		clc		                    CLC
+.396822		6b		rtl		                    RTL
+.396823		22 e9 60 39	jsl $3960e9	ret_success         JSL FDC_Motor_Off
+.396827		e2 20		sep #$20	                SEP #$20        ; set A short
+.396829		a9 00		lda #$00	                    LDA #0
+.39682b		85 00		sta $0320	                    STA BIOS_STATUS
+.39682d		28		plp		                    PLP
+.39682e		2b		pld		                    PLD
+.39682f		ab		plb		                    PLB
+.396830		38		sec		                    SEC
+.396831		6b		rtl		                    RTL
+.396832						FDC_TIME_HANDLE
+.396832		08		php		                    PHP
+.396833		e2 20		sep #$20	                SEP #$20        ; set A short
+.396835		af 4e a0 38	lda $38a04e	                    LDA @l FDC_MOTOR_TIMER          ; Check the FDC motor count-down timer
+.396839		d0 06		bne $396841	                    BNE dec_motor                   ; If not zero: decrement the timer
+.39683b		af 4f a0 38	lda $38a04f	                    LDA @l FDC_MOTOR_TIMER+1        ; Check the high byte
+.39683f		f0 28		beq $396869	                    BEQ sof_timeout                 ; If zero: move on to the next timer
+.396841		af 4e a0 38	lda $38a04e	dec_motor           LDA @l FDC_MOTOR_TIMER          ; Decrement the low byte
+.396845		3a		dec a		                    DEC A
+.396846		8f 4e a0 38	sta $38a04e	                    STA @l FDC_MOTOR_TIMER
+.39684a		c9 ff		cmp #$ff	                    CMP #$FF                        ; Did it roll over?
+.39684c		d0 0b		bne $396859	                    BNE chk_motor_end               ; No: check to see if we're a the end
+.39684e		af 4f a0 38	lda $38a04f	                    LDA @l FDC_MOTOR_TIMER+1        ; Decrement the high byte
+.396852		3a		dec a		                    DEC A
+.396853		8f 4f a0 38	sta $38a04f	                    STA @l FDC_MOTOR_TIMER+1
+.396857		80 10		bra $396869	                    BRA sof_timeout                 ; And move on to the next timer
+.396859		af 4e a0 38	lda $38a04e	chk_motor_end       LDA @l FDC_MOTOR_TIMER          ; Check timer
+.39685d		d0 0a		bne $396869	                    BNE sof_timeout                 ; if it's <>0, move on to the next timer
+.39685f		af 4f a0 38	lda $38a04f	                    LDA @l FDC_MOTOR_TIMER+1
+.396863		d0 04		bne $396869	                    BNE sof_timeout
+.396865		22 e9 60 39	jsl $3960e9	                    JSL FDC_Motor_Off               ; Otherwise, turn off the motor
+.396869						sof_timeout
+.396869		e2 20		sep #$20	                SEP #$20        ; set A short
+.39686b		af 2d 03 00	lda $00032d	                    LDA @l BIOS_TIMER               ; Check the BIOS_TIMER
+.39686f		f0 11		beq $396882	                    BEQ sof_int_done                ; If it's 0, we don't do anything
+.396871		3a		dec a		                    DEC A                           ; Count down one tick
+.396872		8f 2d 03 00	sta $00032d	                    STA @l BIOS_TIMER
+.396876		d0 0a		bne $396882	                    BNE sof_int_done                ; If not 0, we're done
+.396878		af 2c 03 00	lda $00032c	                    LDA @l BIOS_FLAGS               ; Otherwise: flag a time out event
+.39687c		09 80		ora #$80	                    ORA #BIOS_TIMEOUT
+.39687e		8f 2c 03 00	sta $00032c	                    STA @l BIOS_FLAGS
+.396882		28		plp		sof_int_done        PLP
+.396883		6b		rtl		                    RTL
+=62						FDC_BOOT_START = 62                         ; Entry point to the boot code
+=64						FDC_VBR_PATH = 64                           ; Offset to the path in the VBR
+.396884						FDC_VBR_BEGIN
+>396884		eb 00 90			start               .byte $EB, $00, $90     ; Entry point
+>396887		43 32 35 36 44 4f 53 20		magic               .text "C256DOS "        ; OEM name / magic text for booting
+>39688f		00 02				bytes_per_sec       .word 512               ; How many bytes per sector
+>396891		01				sec_per_cluster     .byte 1                 ; How many sectors per cluster
+>396892		01 00				rsrv_sectors        .word 1                 ; Number of reserved sectors
+>396894		02				num_fat             .byte 2                 ; Number of FATs
+>396895		e0 00				max_dir_entry       .word (32-18)*16        ; Total number of root dir entries
+>396897		40 0b				total_sectors       .word 2880              ; Total sectors
+>396899		f0				media_descriptor    .byte $F0               ; 3.5" 1.44 MB floppy 80 tracks, 18 tracks per sector
+>39689a		09 00				sec_per_fat         .word 9                 ; Sectors per FAT
+>39689c		12 00				sec_per_track       .word 18                ; Sectors per track
+>39689e		02 00				num_head            .word 2                 ; Number of heads
+>3968a0		00 00 00 00			ignore2             .dword 0
+>3968a4		00 00 00 00			fat32_sector        .dword 0                ; # of sectors in FAT32
+>3968a8		00 00				ignore3             .word 0
+>3968aa		29				boot_signature      .byte $29
+>3968ab		78 56 34 12			volume_id           .dword $12345678        ; Replaced by code
+>3968af		55 4e 54 49 54 4c 45 44		volume_name         .text "UNTITLED   "     ; Replace by code
+>3968b7		20 20 20
+>3968ba		46 41 54 31 32 20 20 20		fs_type             .text "FAT12   "
+.3968c2		80 40		bra $396904	                    BRA vbr_start
+>3968c4						file_path           .fill 64                ; Reserve 64 bytes for a path and any options
+.396904						vbr_start
+.396904		c2 20		rep #$20	                REP #$20        ; set A long
+.396906		a9 40 a3	lda #$a340	                    LDA #<>(DOS_SECTOR + (file_path - FDC_VBR_BEGIN))
+.396909		8f 60 03 00	sta $000360	                    STA @l DOS_RUN_PARAM
+.39690d		a9 38 00	lda #$0038	                    LDA #`(DOS_SECTOR + (file_path - FDC_VBR_BEGIN))
+.396910		8f 62 03 00	sta $000362	                    STA @l DOS_RUN_PARAM+2
+.396914		22 a3 57 39	jsl $3957a3	                    JSL IF_RUN              ; And try to execute the binary file
+.396918		b0 0c		bcs $396926	                    BCS lock                ; If it returned success... lock up... I guess?
+.39691a						error
+.39691a		e2 20		sep #$20	                SEP #$20        ; set A short
+.39691c		4b		phk		                    PHK                     ; Otherwise, print an error message
+.39691d		ab		plb		                    PLB
+.39691e		62 08 00	per $396929	                    PER message
+.396921		fa		plx		                    PLX
+.396922		22 1c 10 00	jsl $00101c	                    JSL PUTS
+.396926		ea		nop		lock                NOP                     ; And lock up
+.396927		80 fd		bra $396926	                    BRA lock
+>396929		43 6f 75 6c 64 20 6e 6f		message             .null "Could not find a bootable binary.",13
+>396931		74 20 66 69 6e 64 20 61 20 62 6f 6f 74 61 62 6c
+>396941		65 20 62 69 6e 61 72 79 2e 0d 00
+.39694c						FDC_VBR_END
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Libraries/ide_library.asm
+
+.0000						IDE_ID
+>0000		00 00				General_Config        .word $0000
+>0002		00 00				Obsolete0             .word $0000
+>0004		00 00				Specific_Config       .word $0000
+>0006		00 00				Obsolete1             .word $0000
+>0008		00 00				Retired0              .word $0000
+>000a		00 00				Retired1              .word $0000
+>000c		00 00				Obsolete2             .word $0000
+>000e		00 00				Reserved_CFlash0      .word $0000
+>0010		00 00				Reserved_CFlash1      .word $0000
+>0012		00 00				Retired2              .word $0000
+>0014		00 00 00 00 00 00 00 00		Serial_Number_String  .byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>001c		00 00 00 00 00 00 00 00 00 00 00 00
+>0028		00 00 00 00			Retired3              .word $0000, $0000
+>002c		00 00				Obsolete3             .word $0000
+>002e		00 00 00 00 00 00 00 00		Firmware_Rev_String   .byte $00, $00, $00, $00, $00, $00, $00, $00
+>0036		00 00 00 00 00 00 00 00		Model_Number_String   .byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>003e		00 00 00 00 00 00 00 00
+>0046		00 00 00 00 00 00 00 00		                      .byte $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>004e		00 00 00 00 00 00 00 00
+>0056		00 00 00 00 00 00 00 00		                      .byte $00, $00, $00, $00, $00, $00, $00, $00
+>005e		00 00				Max_Number_Logic_Sec  .word $0000
+>0060		00 00				Trusted_Comp_Feature  .word $0000
+>0062		00 00 00 00			Capabilities          .word $0000, $0000
+>0066		00 00 00 00			Obsolete4             .word $0000, $0000
+>006a		00 00				Free_Fall_Control     .word $0000
+>006c		00 00 00 00 00 00 00 00		Obsolete5             .word $0000, $0000, $0000, $0000, $0000
+>0074		00 00
+>0076		00 00				Reserved0             .word $0000
+>0078		00 00 00 00			Total_Addy_Logic_Sec  .word $0000, $0000
+>007c		00 00				Obsolete6             .word $0000
+>007e		00 00 00 00			Reserved1             .word $0000, $0000
+>0082		00 00				Min_Multiword_DMA_Trf .word $0000
+>0084		00 00				Manu_Recommended_Mult .word $0000
+>0086		00 00				Min_PIO_Trf           .word $0000      ; Word 67
+>0088		00 00				Min_PIO_Trf_with_IORD .word $0000      ; Word 68
+>008a		00 00 00 00			Reserved2             .word $0000, $0000
+>008e		00 00 00 00 00 00 00 00		Reserved3             .word $0000, $0000, $0000, $0000
+>0096		00 00				Queue_Dept            .word $0000
+>0098		00 00				SATA_Capabilities     .word $0000
+>009a		00 00				Reserved_SATA         .word $0000
+>009c		00 00				Sup_Feat_SATA         .word $0000
+>009e		00 00				Sup_Feat_SATA_Enabled .word $0000    ; Word 79
+>00a0		00 00				Major_Version_Number  .word $0000    ; Word 80
+>00a2		00 00				Minor_Version_Number  .word $0000    ; Word 81
+>00a4		00 00 00 00 00 00 00 00		Cmd_And_Features_Sup  .word $0000, $0000, $0000, $0000, $0000, $0000
+>00ac		00 00 00 00
+>00b0		00 00				UDMA_Modes            .word $0000
+>00b2		00 00 00 00			Reserved4             .word $0000, $0000 ; Word 89
+>00b6		00 00				Current_APM_Level     .word $0000
+>00b8		00 00				Master_Password_Ident .word $0000
+>00ba		00 00				Hardware_Reset_Result .word $0000
+>00bc		00 00				Current_AAM_Value     .word $0000  ; Word 94
+>00be		00 00				Stream_Min_Req_Size   .word $0000  ; Word 95
+>00c0		00 00				Stream_Trf_Time_DMA   .word $0000  ; Word 96
+>00c2		00 00				Stream_Access_Lat     .word $0000
+>00c4		00 00 00 00			Streaming_Perf_Gran   .word $0000, $0000
+>00c8		00 00 00 00 00 00 00 00		Tot_Num_Add_Logic_Sec .word $0000, $0000, $0000, $0000
+>00d0		00 00				Streaming_Trf_Time    .word $0000 ; Word 104
+>00d2		00 00				Reserved5             .word $0000 ; Word 105
+.39694c						IDE_TEST
+.39694c		08		php		                PHP
+.39694d		c2 20		rep #$20	                REP #$20        ; set A long
+.39694f		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR
+.396952		8f 26 03 00	sta $000326	                STA @l BIOS_BUFF_PTR
+.396956		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
+.396959		8f 28 03 00	sta $000328	                STA @l BIOS_BUFF_PTR+2
+.39695d		22 80 6a 39	jsl $396a80	                JSL IDE_IDENTIFY
+.396961		b0 03		bcs $396966	                BCS id_ok
+.396963		82 ab 00	brl $396a11	                BRL done
+.396966						id_ok
+.396966		c2 10		rep #$10	                REP #$10        ; set X long
+.396968		e2 20		sep #$20	                SEP #$20        ; set A short
+.39696a		a0 28 00	ldy #$0028	                LDY #40
+.39696d		a2 36 00	ldx #$0036	                LDX #27*2
+.396970		bf 01 a3 38	lda $38a301,x	pr_model        LDA DOS_SECTOR+1,X
+.396974		22 18 10 00	jsl $001018	                JSL PUTC
+.396978		bf 00 a3 38	lda $38a300,x	                LDA DOS_SECTOR,X
+.39697c		22 18 10 00	jsl $001018	                JSL PUTC
+.396980		e8		inx		                INX
+.396981		e8		inx		                INX
+.396982		88		dey		                DEY
+.396983		88		dey		                DEY
+.396984		d0 ea		bne $396970	                BNE pr_model
+.396986		c2 10		rep #$10	                REP #$10        ; set X long
+.396988		e2 20		sep #$20	                SEP #$20        ; set A short
+.39698a		a0 14 00	ldy #$0014	                LDY #20
+.39698d		a2 14 00	ldx #$0014	                LDX #10*2
+.396990		bf 01 a3 38	lda $38a301,x	pr_serial       LDA DOS_SECTOR+1,X
+.396994		22 18 10 00	jsl $001018	                JSL PUTC
+.396998		bf 00 a3 38	lda $38a300,x	                LDA DOS_SECTOR,X
+.39699c		22 18 10 00	jsl $001018	                JSL PUTC
+.3969a0		e8		inx		                INX
+.3969a1		e8		inx		                INX
+.3969a2		88		dey		                DEY
+.3969a3		88		dey		                DEY
+.3969a4		d0 ea		bne $396990	                BNE pr_serial
+.3969a6		22 6c 10 00	jsl $00106c	                JSL PRINTCR
+.3969aa		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3969ac		a9 01 00	lda #$0001	                LDA #1                 ; Set LBA = 1
+.3969af		8f 22 03 00	sta $000322	                STA @l BIOS_LBA
+.3969b3		a9 00 00	lda #$0000	                LDA #0
+.3969b6		8f 24 03 00	sta $000324	                STA @l BIOS_LBA+2
+.3969ba		a9 00 a3	lda #$a300	                LDA #<>DOS_SECTOR
+.3969bd		8f 26 03 00	sta $000326	                STA @l BIOS_BUFF_PTR
+.3969c1		a9 38 00	lda #$0038	                LDA #`DOS_SECTOR
+.3969c4		8f 28 03 00	sta $000328	                STA @l BIOS_BUFF_PTR+2
+.3969c8		a2 00 00	ldx #$0000	                LDX #0                  ; Initialize the block to some recognizable data
+.3969cb		a9 a5 5a	lda #$5aa5	                LDA #$5AA5
+.3969ce		9f 00 a3 38	sta $38a300,x	init_loop       STA DOS_SECTOR,X
+.3969d2		e8		inx		                INX
+.3969d3		e8		inx		                INX
+.3969d4		e0 00 02	cpx #$0200	                CPX #512
+.3969d7		d0 f5		bne $3969ce	                BNE init_loop
+.3969d9		22 9f 6b 39	jsl $396b9f	                JSL IDE_PUTBLOCK        ; Attempt to write the block
+.3969dd		b0 06		bcs $3969e5	                BCS read_sect1
+.3969df		22 6c 10 00	jsl $00106c	                JSL PRINTCR
+.3969e3		80 2c		bra $396a11	                BRA done
+.3969e5		a9 01 00	lda #$0001	read_sect1      LDA #1                 ; Set LBA = 1
+.3969e8		8f 22 03 00	sta $000322	                STA @l BIOS_LBA
+.3969ec		a9 00 00	lda #$0000	                LDA #0
+.3969ef		8f 24 03 00	sta $000324	                STA @l BIOS_LBA+2
+.3969f3		a9 00 a5	lda #$a500	                LDA #<>DOS_FAT_SECTORS
+.3969f6		8f 26 03 00	sta $000326	                STA @l BIOS_BUFF_PTR
+.3969fa		a9 38 00	lda #$0038	                LDA #`DOS_FAT_SECTORS
+.3969fd		8f 28 03 00	sta $000328	                STA @l BIOS_BUFF_PTR+2
+.396a01		22 0e 6b 39	jsl $396b0e	                JSL IDE_GETBLOCK        ; Attempt to read the block
+.396a05		b0 06		bcs $396a0d	                BCS all_ok
+.396a07		22 6c 10 00	jsl $00106c	                JSL PRINTCR
+.396a0b		80 04		bra $396a11	                BRA done
+.396a0d						all_ok
+.396a0d		22 6c 10 00	jsl $00106c	                JSL PRINTCR
+.396a11		28		plp		done            PLP
+.396a12		6b		rtl		                RTL
+.396a13						IDE_INIT
+.396a13		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a15		a9 00		lda #$00	              LDA #$00
+.396a17		8f 37 e8 af	sta $afe837	              STA IDE_CMD_STAT
+.396a1b		20 3c 6a	jsr $396a3c	              JSR IDE_DRIVE_BSY ; Check to see if drive is busy
+.396a1e		a9 e0		lda #$e0	              LDA #$E0 ; HEAD 0 - Select Master Drive
+.396a20		8f 36 e8 af	sta $afe836	              STA IDE_HEAD
+.396a24		a9 01		lda #$01	              LDA #$01
+.396a26		8f 32 e8 af	sta $afe832	              STA IDE_SECT_CNT
+.396a2a		a9 00		lda #$00	              LDA #$00
+.396a2c		8f 33 e8 af	sta $afe833	              STA IDE_SECT_SRT
+.396a30		8f 34 e8 af	sta $afe834	              STA IDE_CLDR_LO
+.396a34		8f 35 e8 af	sta $afe835	              STA IDE_CLDR_HI
+.396a38		20 5a 6a	jsr $396a5a	              JSR IDE_DRV_READY_NOTBUSY
+.396a3b		6b		rtl		              RTL
+.396a3c						IDE_DRIVE_BSY
+.396a3c		08		php		                PHP
+.396a3d		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a3f		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT
+.396a43		29 80		and #$80	                AND #IDE_STAT_BSY         ; Check for RDY Bit, this needs to be 1'b1
+.396a45		c9 80		cmp #$80	                CMP #IDE_STAT_BSY         ; If not go read again
+.396a47		f0 f6		beq $396a3f	                BEQ loop
+.396a49		28		plp		                PLP
+.396a4a		60		rts		                RTS
+.396a4b						IDE_DRIVE_READY
+.396a4b		08		php		                PHP
+.396a4c		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a4e		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT
+.396a52		29 40		and #$40	                AND #IDE_STAT_DRDY          ; Check to see if the Busy Signal is Cleared
+.396a54		c9 40		cmp #$40	                CMP #IDE_STAT_DRDY          ; if it is still one, then go back to read again.
+.396a56		d0 f6		bne $396a4e	                BNE loop
+.396a58		28		plp		                PLP
+.396a59		60		rts		                RTS
+.396a5a						IDE_DRV_READY_NOTBUSY
+.396a5a		08		php		                PHP
+.396a5b		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a5d		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT                 ; Check the status
+.396a61		29 c0		and #$c0	                AND #IDE_STAT_BSY | IDE_STAT_DRDY
+.396a63		c9 40		cmp #$40	                CMP #IDE_STAT_DRDY                  ; Is it READY but not BUSY?
+.396a65		d0 f6		bne $396a5d	                BNE loop                            ; No: keep waiting
+.396a67		28		plp		ret_success     PLP                                 ; Return success
+.396a68		38		sec		                SEC
+.396a69		60		rts		                RTS
+.396a6a		8f 07 03 00	sta $000307	ret_failure     STA @l FDC_ST1                      ; Save the status code to FDC_ST1
+.396a6e		28		plp		                PLP                                 ; Return failure
+.396a6f		18		clc		                CLC
+.396a70		60		rts		                RTS
+.396a71						IDE_NOT_DRQ
+.396a71		08		php		                PHP
+.396a72		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a74		af 37 e8 af	lda $afe837	loop            LDA @l IDE_CMD_STAT     ; Get the status
+.396a78		29 08		and #$08	                AND #IDE_STAT_DRQ
+.396a7a		c9 08		cmp #$08	                CMP #IDE_STAT_DRQ       ; Is the DRQ bit set?
+.396a7c		d0 f6		bne $396a74	                BNE loop                ; No: keep waiting
+.396a7e		28		plp		                PLP
+.396a7f		60		rts		                RTS
+.396a80						IDE_IDENTIFY
+.396a80		5a		phy		                PHY
+.396a81		8b		phb		                PHB
+.396a82		0b		phd		                PHD
+.396a83		08		php		                PHP
+.396a84		48		pha		                PHA             ; begin setdbr macro
+.396a85		08		php		                PHP
+.396a86		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a88		a9 00		lda #$00	                LDA #0
+.396a8a		48		pha		                PHA
+.396a8b		ab		plb		                PLB
+.396a8c		28		plp		                PLP
+.396a8d		68		pla		                PLA             ; end setdbr macro
+.396a8e		48		pha		                PHA             ; begin setdp macro
+.396a8f		08		php		                PHP
+.396a90		c2 20		rep #$20	                REP #$20        ; set A long
+.396a92		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.396a95		5b		tcd		                TCD
+.396a96		28		plp		                PLP
+.396a97		68		pla		                PLA             ; end setdp macro
+.396a98		e2 20		sep #$20	                SEP #$20        ; set A short
+.396a9a		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait until the IDE is clear to accept commands
+.396a9d		a5 05		lda $0325	                LDA BIOS_LBA+3                  ; Get the high bits of the LBA
+.396a9f		29 07		and #$07	                AND #$07
+.396aa1		09 a0		ora #$a0	                ORA #%10100000                  ; Select DEV=0 and LBA mode = 1
+.396aa3		8f 36 e8 af	sta $afe836	                STA @l IDE_HEAD                 ; Ensure master is selected
+.396aa7		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; And wait for it to take effect
+.396aaa		e2 20		sep #$20	                SEP #$20        ; set A short
+.396aac		a9 00		lda #$00	                LDA #0                          ; Clear sector count and LBA
+.396aae		8f 32 e8 af	sta $afe832	                STA @l IDE_SECT_CNT
+.396ab2		8f 33 e8 af	sta $afe833	                STA @l IDE_SECT_SRT
+.396ab6		8f 34 e8 af	sta $afe834	                STA @l IDE_CLDR_LO
+.396aba		8f 35 e8 af	sta $afe835	                STA @l IDE_CLDR_HI
+.396abe		a9 ec		lda #$ec	                LDA #IDE_CMD_IDENTIFY           ; The IDENTIFY command
+.396ac0		8f 37 e8 af	sta $afe837	                STA @l IDE_CMD_STAT             ; Check the status
+.396ac4		f0 29		beq $396aef	                BEQ no_media                    ; If 0: there is no drive
+.396ac6		20 3c 6a	jsr $396a3c	                JSR IDE_DRIVE_BSY               ; Othewise: wait for drive to not be busy
+.396ac9		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
+.396acc		90 2d		bcc $396afb	                BCC ret_failure                 ; If an error occurred, return it
+.396ace		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396ad0		a0 00 00	ldy #$0000	                LDY #0
+.396ad3		af 38 e8 af	lda $afe838	read_loop       LDA @l IDE_DATA_LO              ; Get the word of data from the device
+.396ad7		97 06		sta [$0326],y	                STA [BIOS_BUFF_PTR],Y           ; Save it to the buffer
+.396ad9		c8		iny		                INY                             ; Move to the next position
+.396ada		c8		iny		                INY
+.396adb		c0 00 02	cpy #$0200	                CPY #512
+.396ade		d0 f3		bne $396ad3	                BNE read_loop
+.396ae0						ret_success
+.396ae0		e2 20		sep #$20	                SEP #$20        ; set A short
+.396ae2		a9 00		lda #$00	                LDA #0
+.396ae4		85 00		sta $0320	                STA BIOS_STATUS
+.396ae6		8d 06 03	sta $0306	                STA @w FDC_ST0
+.396ae9		28		plp		                PLP                             ; Return success
+.396aea		2b		pld		                PLD
+.396aeb		ab		plb		                PLB
+.396aec		7a		ply		                PLY
+.396aed		38		sec		                SEC
+.396aee		6b		rtl		                RTL
+.396aef						no_media
+.396aef		e2 20		sep #$20	                SEP #$20        ; set A short
+.396af1		a9 87		lda #$87	                LDA #BIOS_ERR_NOMEDIA
+.396af3		80 0a		bra $396aff	                BRA pass_failure
+.396af5						not_ata
+.396af5		e2 20		sep #$20	                SEP #$20        ; set A short
+.396af7		a9 8a		lda #$8a	                LDA #BIOS_ERR_NOTATA
+.396af9		80 04		bra $396aff	                BRA pass_failure
+.396afb						ret_failure
+.396afb		e2 20		sep #$20	                SEP #$20        ; set A short
+.396afd		a9 82		lda #$82	                LDA #BIOS_ERR_READ
+.396aff		85 00		sta $0320	pass_failure    STA BIOS_STATUS
+.396b01		af 31 e8 af	lda $afe831	                LDA @l IDE_ERROR
+.396b05		8d 06 03	sta $0306	                STA @w FDC_ST0
+.396b08		28		plp		                PLP
+.396b09		2b		pld		                PLD
+.396b0a		ab		plb		                PLB
+.396b0b		7a		ply		                PLY
+.396b0c		18		clc		                CLC
+.396b0d		6b		rtl		                RTL
+.396b0e						IDE_GETBLOCK
+.396b0e		5a		phy		                PHY
+.396b0f		8b		phb		                PHB
+.396b10		0b		phd		                PHD
+.396b11		08		php		                PHP
+.396b12		48		pha		                PHA             ; begin setdbr macro
+.396b13		08		php		                PHP
+.396b14		e2 20		sep #$20	                SEP #$20        ; set A short
+.396b16		a9 00		lda #$00	                LDA #0
+.396b18		48		pha		                PHA
+.396b19		ab		plb		                PLB
+.396b1a		28		plp		                PLP
+.396b1b		68		pla		                PLA             ; end setdbr macro
+.396b1c		48		pha		                PHA             ; begin setdp macro
+.396b1d		08		php		                PHP
+.396b1e		c2 20		rep #$20	                REP #$20        ; set A long
+.396b20		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.396b23		5b		tcd		                TCD
+.396b24		28		plp		                PLP
+.396b25		68		pla		                PLA             ; end setdp macro
+.396b26		e2 20		sep #$20	                SEP #$20        ; set A short
+.396b28		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait until the IDE is clear to accept commands
+.396b2b		a5 05		lda $0325	                LDA BIOS_LBA+3                  ; Get the high bits of the LBA
+.396b2d		29 07		and #$07	                AND #$07
+.396b2f		09 e0		ora #$e0	                ORA #%11100000                  ; Select DEV=0 and LBA mode = 1
+.396b31		8f 36 e8 af	sta $afe836	                STA @l IDE_HEAD                 ; Ensure master is selected
+.396b35		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; And wait for it to take effect
+.396b38		e2 20		sep #$20	                SEP #$20        ; set A short
+.396b3a		a9 01		lda #$01	                LDA #1                          ; Set that we want one sector
+.396b3c		8f 32 e8 af	sta $afe832	                STA @l IDE_SECT_CNT
+.396b40		a5 02		lda $0322	                LDA BIOS_LBA                    ; Set the lower bits of the LBA
+.396b42		8f 33 e8 af	sta $afe833	                STA @l IDE_SECT_SRT
+.396b46		a5 03		lda $0323	                LDA BIOS_LBA+1
+.396b48		8f 34 e8 af	sta $afe834	                STA @l IDE_CLDR_LO
+.396b4c		a5 04		lda $0324	                LDA BIOS_LBA+2
+.396b4e		8f 35 e8 af	sta $afe835	                STA @l IDE_CLDR_HI
+.396b52		a9 21		lda #$21	                LDA #IDE_CMD_READ_SECTOR        ; The READ SECTOR command
+.396b54		8f 37 e8 af	sta $afe837	                STA @l IDE_CMD_STAT
+.396b58		ea		nop		                NOP                             ; Wait about 500ns
+.396b59		ea		nop		                NOP
+.396b5a		ea		nop		                NOP
+.396b5b		ea		nop		                NOP
+.396b5c		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
+.396b5f		90 2b		bcc $396b8c	                BCC ret_failure                 ; If an error occurred, return it
+.396b61		e2 20		sep #$20	                SEP #$20        ; set A short
+.396b63		af 30 e8 af	lda $afe830	                LDA @l IDE_DATA                 ; Read and toss out one byte from the 8-bit interface
+.396b67		a0 00 00	ldy #$0000	                LDY #0
+.396b6a		c2 20		rep #$20	                REP #$20        ; set A long
+.396b6c		af 38 e8 af	lda $afe838	read_loop       LDA @l IDE_DATA_LO              ; Get the word of data from the device
+.396b70		97 06		sta [$0326],y	                STA [BIOS_BUFF_PTR],Y           ; Save it to the buffer
+.396b72		c8		iny		                INY                             ; Move to the next position
+.396b73		c8		iny		                INY
+.396b74		c0 00 02	cpy #$0200	                CPY #512
+.396b77		d0 f3		bne $396b6c	                BNE read_loop
+.396b79		ea		nop		                NOP                             ; Wait about 500ns
+.396b7a		ea		nop		                NOP
+.396b7b		ea		nop		                NOP
+.396b7c		ea		nop		                NOP
+.396b7d						ret_success
+.396b7d		e2 20		sep #$20	                SEP #$20        ; set A short
+.396b7f		a9 00		lda #$00	                LDA #0
+.396b81		85 00		sta $0320	                STA BIOS_STATUS
+.396b83		8d 06 03	sta $0306	                STA @w FDC_ST0
+.396b86		28		plp		                PLP                             ; Return success
+.396b87		2b		pld		                PLD
+.396b88		ab		plb		                PLB
+.396b89		7a		ply		                PLY
+.396b8a		38		sec		                SEC
+.396b8b		6b		rtl		                RTL
+.396b8c						ret_failure
+.396b8c		e2 20		sep #$20	                SEP #$20        ; set A short
+.396b8e		af 31 e8 af	lda $afe831	                LDA @l IDE_ERROR
+.396b92		8d 06 03	sta $0306	                STA @w FDC_ST0
+.396b95		a9 82		lda #$82	                LDA #BIOS_ERR_READ
+.396b97		85 00		sta $0320	                STA BIOS_STATUS
+.396b99		28		plp		                PLP
+.396b9a		2b		pld		                PLD
+.396b9b		ab		plb		                PLB
+.396b9c		7a		ply		                PLY
+.396b9d		18		clc		                CLC
+.396b9e		6b		rtl		                RTL
+.396b9f						IDE_PUTBLOCK
+.396b9f		5a		phy		                PHY
+.396ba0		8b		phb		                PHB
+.396ba1		0b		phd		                PHD
+.396ba2		08		php		                PHP
+.396ba3		48		pha		                PHA             ; begin setdbr macro
+.396ba4		08		php		                PHP
+.396ba5		e2 20		sep #$20	                SEP #$20        ; set A short
+.396ba7		a9 00		lda #$00	                LDA #0
+.396ba9		48		pha		                PHA
+.396baa		ab		plb		                PLB
+.396bab		28		plp		                PLP
+.396bac		68		pla		                PLA             ; end setdbr macro
+.396bad		48		pha		                PHA             ; begin setdp macro
+.396bae		08		php		                PHP
+.396baf		c2 20		rep #$20	                REP #$20        ; set A long
+.396bb1		a9 20 03	lda #$0320	                LDA #SDOS_VARIABLES         ; set DP to page 0
+.396bb4		5b		tcd		                TCD
+.396bb5		28		plp		                PLP
+.396bb6		68		pla		                PLA             ; end setdp macro
+.396bb7		e2 20		sep #$20	                SEP #$20        ; set A short
+.396bb9		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait until the IDE is clear to accept commands
+.396bbc		a5 05		lda $0325	                LDA BIOS_LBA+3                  ; Get the high bits of the LBA
+.396bbe		29 07		and #$07	                AND #$07
+.396bc0		09 e0		ora #$e0	                ORA #%11100000                  ; Select DEV=0 and LBA mode = 1
+.396bc2		8f 36 e8 af	sta $afe836	                STA @l IDE_HEAD                 ; Ensure master is selected
+.396bc6		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; And wait for it to take effect
+.396bc9		e2 20		sep #$20	                SEP #$20        ; set A short
+.396bcb		a9 01		lda #$01	                LDA #1                          ; Set that we want one sector
+.396bcd		8f 32 e8 af	sta $afe832	                STA @l IDE_SECT_CNT
+.396bd1		a5 02		lda $0322	                LDA BIOS_LBA                    ; Set the lower bits of the LBA
+.396bd3		8f 33 e8 af	sta $afe833	                STA @l IDE_SECT_SRT
+.396bd7		a5 03		lda $0323	                LDA BIOS_LBA+1
+.396bd9		8f 34 e8 af	sta $afe834	                STA @l IDE_CLDR_LO
+.396bdd		a5 04		lda $0324	                LDA BIOS_LBA+2
+.396bdf		8f 35 e8 af	sta $afe835	                STA @l IDE_CLDR_HI
+.396be3		a9 30		lda #$30	                LDA #IDE_CMD_WRITE_SECTOR       ; The READ SECTOR command
+.396be5		8f 37 e8 af	sta $afe837	                STA @l IDE_CMD_STAT
+.396be9		ea		nop		                NOP                             ; Wait about 500ns
+.396bea		ea		nop		                NOP
+.396beb		ea		nop		                NOP
+.396bec		ea		nop		                NOP
+.396bed		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
+.396bf0		90 33		bcc $396c25	                BCC ret_failure                 ; If an error occurred, return it
+.396bf2		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396bf4		a0 00 00	ldy #$0000	                LDY #0
+.396bf7		b7 06		lda [$0326],y	read_loop       LDA [BIOS_BUFF_PTR],Y           ; Get the word from the buffer
+.396bf9		8f 38 e8 af	sta $afe838	                STA @l IDE_DATA_LO              ; Save the word to the device
+.396bfd		c8		iny		                INY                             ; Move to the next position
+.396bfe		c8		iny		                INY
+.396bff		c0 00 02	cpy #$0200	                CPY #512
+.396c02		d0 f3		bne $396bf7	                BNE read_loop
+.396c04		ea		nop		                NOP                             ; Wait about 500ns
+.396c05		ea		nop		                NOP
+.396c06		ea		nop		                NOP
+.396c07		ea		nop		                NOP
+.396c08		20 5a 6a	jsr $396a5a	                JSR IDE_DRV_READY_NOTBUSY       ; Wait for the device to be ready
+.396c0b		90 18		bcc $396c25	                BCC ret_failure                 ; If an error occurred, return it
+.396c0d		af 37 e8 af	lda $afe837	                LDA @l IDE_CMD_STAT             ; Check the status
+.396c11		89 21 00	bit #$0021	                BIT #IDE_STAT_ERR | IDE_STAT_DF
+.396c14		d0 0f		bne $396c25	                BNE ret_failure                 ; If error: return failure
+.396c16						ret_success
+.396c16		e2 20		sep #$20	                SEP #$20        ; set A short
+.396c18		a9 00		lda #$00	                LDA #0
+.396c1a		85 00		sta $0320	                STA BIOS_STATUS
+.396c1c		8d 06 03	sta $0306	                STA @w FDC_ST0
+.396c1f		28		plp		                PLP                             ; Return success
+.396c20		2b		pld		                PLD
+.396c21		ab		plb		                PLB
+.396c22		7a		ply		                PLY
+.396c23		38		sec		                SEC
+.396c24		6b		rtl		                RTL
+.396c25						ret_failure
+.396c25		e2 20		sep #$20	                SEP #$20        ; set A short
+.396c27		af 31 e8 af	lda $afe831	                LDA @l IDE_ERROR
+.396c2b		8d 06 03	sta $0306	                STA @w FDC_ST0
+.396c2e		a9 82		lda #$82	                LDA #BIOS_ERR_READ
+.396c30		85 00		sta $0320	                STA BIOS_STATUS
+.396c32		28		plp		                PLP
+.396c33		2b		pld		                PLD
+.396c34		ab		plb		                PLB
+.396c35		7a		ply		                PLY
+.396c36		18		clc		                CLC
+.396c37		6b		rtl		                RTL
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Libraries/Ethernet_Init_library.asm
+
+.396c38						SIMPLE_INIT_ETHERNET_CTRL
+.396c38						WaitforittobeReady:
+.396c38		af 84 e0 ae	lda $aee084	                LDA @l ESID_ETHERNET_REG + $84
+.396c3c		29 01 00	and #$0001	                AND #$0001
+.396c3f		c9 01 00	cmp #$0001	                CMP #$0001 ; This is to check that the Controller is ready to roll
+.396c42		d0 f4		bne $396c38	                BNE WaitforittobeReady
+.396c44		af 52 e0 ae	lda $aee052	                LDA @l ESID_ETHERNET_REG + $52 ;Chip ID (0x9221)
+.396c48		af 50 e0 ae	lda $aee050	                LDA @l ESID_ETHERNET_REG + $50 ;Chip Revision
+.396c4c		af 64 e0 ae	lda $aee064	                LDA @l ESID_ETHERNET_REG + $64
+.396c50		af 66 e0 ae	lda $aee066	                LDA @l ESID_ETHERNET_REG + $66
+.396c54		a9 00 00	lda #$0000	                LDA #$0000
+.396c57		8f 88 e0 ae	sta $aee088	                STA @l ESID_ETHERNET_REG + $88
+.396c5b		a9 00 70	lda #$7000	                LDA #$7000
+.396c5e		8f 8a e0 ae	sta $aee08a	                STA @l ESID_ETHERNET_REG + $8A
+.396c62		a9 02 00	lda #$0002	                LDA #$0002 ; Accessing CSR INDEX 2 MAC Address (High)
+.396c65		8f a4 e0 ae	sta $aee0a4	                STA @l ESID_ETHERNET_REG + $A4
+.396c69		a9 0b 00	lda #$000b	                LDA #$000B
+.396c6c		8f a8 e0 ae	sta $aee0a8	                STA @l ESID_ETHERNET_REG + $A8
+.396c70		a9 00 00	lda #$0000	                LDA #$0000
+.396c73		8f aa e0 ae	sta $aee0aa	                STA @l ESID_ETHERNET_REG + $AA
+.396c77		20 ab 6c	jsr $396cab	                JSR MAC_ACCESS_WAIT_FOR_COMPLETION
+.396c7a		a9 03 00	lda #$0003	                LDA #$0003 ; Accessing CSR INDEX 3 MAC Address (low)
+.396c7d		8f a4 e0 ae	sta $aee0a4	                STA @l ESID_ETHERNET_REG + $A4
+.396c81		a9 7f dc	lda #$dc7f	                LDA #$DC7F
+.396c84		8f a8 e0 ae	sta $aee0a8	                STA @l ESID_ETHERNET_REG + $A8
+.396c88		a9 d7 ab	lda #$abd7	                LDA #$ABD7
+.396c8b		8f aa e0 ae	sta $aee0aa	                STA @l ESID_ETHERNET_REG + $AA
+.396c8f		20 ab 6c	jsr $396cab	                JSR MAC_ACCESS_WAIT_FOR_COMPLETION
+.396c92		a9 01 00	lda #$0001	                LDA #$0001 ; Accessing CSR INDEX 2 MAC Address (High)
+.396c95		8f a4 e0 ae	sta $aee0a4	                STA @l ESID_ETHERNET_REG + $A4
+.396c99		a9 0c 00	lda #$000c	                LDA #$000C
+.396c9c		8f a8 e0 ae	sta $aee0a8	                STA @l ESID_ETHERNET_REG + $A8
+.396ca0		a9 04 00	lda #$0004	                LDA #$0004
+.396ca3		8f aa e0 ae	sta $aee0aa	                STA @l ESID_ETHERNET_REG + $AA
+.396ca7		20 ab 6c	jsr $396cab	                JSR MAC_ACCESS_WAIT_FOR_COMPLETION
+.396caa		6b		rtl		                RTL
+.396cab						MAC_ACCESS_WAIT_FOR_COMPLETION
+.396cab		a9 00 80	lda #$8000	                LDA #$8000 ; CsR busy bit is a status but also the Command Execution bit
+.396cae		8f a6 e0 ae	sta $aee0a6	                STA @l ESID_ETHERNET_REG + $A6
+.396cb2						WaitForCompletion:
+.396cb2		af a6 e0 ae	lda $aee0a6	                LDA @l ESID_ETHERNET_REG + $A6
+.396cb6		29 00 80	and #$8000	                AND #$8000
+.396cb9		c9 00 80	cmp #$8000	                CMP #$8000
+.396cbc		f0 f4		beq $396cb2	                BEQ WaitForCompletion
+.396cbe		60		rts		                RTS
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\Libraries/EXP-C200_EVID_Library.asm
+
+=$000060					EVID_SCREENBEGIN      = $000060 ;3 Bytes Start of screen in video RAM. This is the upper-left corrner of the current video page being written to. This may not be what's being displayed by VICKY. Update this if you change VICKY's display page.
+=$000064					EVID_COLS_VISIBLE     = $000064 ;2 Bytes Columns visible per screen line. A virtual line can be longer than displayed, up to COLS_PER_LINE long. Default = 80
+=$000066					EVID_COLS_PER_LINE    = $000066 ;2 Bytes Columns in memory per screen line. A virtual line can be this long. Default=128
+=$000068					EVID_LINES_VISIBLE    = $000068 ;2 Bytes The number of rows visible on the screen. Default=25
+=$00006a					EVID_LINES_MAX        = $00006A ;2 Bytes The number of rows in memory for the screen. Default=64
+=$00006c					EVID_CURSORPOS        = $00006C ;3 Bytes The next character written to the screen will be written in this location.
+=$000070					EVID_CURSORX          = $000070 ;2 Bytes This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
+=$000072					EVID_CURSORY          = $000072 ;2 Bytes This is where the blinking cursor sits. Do not edit this direectly. Call LOCATE to update the location and handle moving the cursor correctly.
+=$000074					EVID_CURCOLOR         = $000074 ;1 Byte Color of next character to be printed to the screen.
+=$000075					EVID_COLORPOS         = $000075 ;3 Byte address of cursor's position in the color matrix
+=$000076					EVID_TMPPTR1          = $000076 ; 4 byte temporary pointer
+=$ae2000					EVID_SCREEN_PAGE      = $AE2000 ;8192 Bytes First page of display RAM. This is used at boot time to display the welcome screen and the BASIC or MONITOR command screens.
+.396cbf						EVID_IPRINT
+.396cbf		22 c8 6c 39	jsl $396cc8	                JSL EVID_IPUTS
+.396cc3		22 3a 6e 39	jsl $396e3a	                JSL EVID_IPRINTCR
+.396cc7		6b		rtl		                RTL
+.396cc8						EVID_IPUTS
+.396cc8		48		pha		                PHA
+.396cc9		08		php		                PHP
+.396cca		e2 20		sep #$20	                SEP #$20        ; set A short
+.396ccc		c2 10		rep #$10	                REP #$10        ; set X long
+.396cce		bd 00 00	lda $0000,x	iputs1          LDA $0,b,x      ; read from the string
+.396cd1		f0 08		beq $396cdb	                BEQ iputs_done
+.396cd3		22 df 6c 39	jsl $396cdf	iputs2          JSL EVID_IPUTC
+.396cd7		e8		inx		iputs3          INX
+.396cd8		4c ce 6c	jmp $396cce	                JMP iputs1
+.396cdb		e8		inx		iputs_done      INX
+.396cdc		28		plp		                PLP
+.396cdd		68		pla		                PLA
+.396cde		6b		rtl		                RTL
+.396cdf						EVID_IPUTC
+.396cdf		da		phx		                PHX
+.396ce0		5a		phy		                PHY
+.396ce1		0b		phd		                PHD
+.396ce2		8b		phb		                PHB
+.396ce3		08		php		                PHP                 ; stash the flags (we'll be changing M)
+.396ce4		48		pha		                PHA             ; begin setdp macro
+.396ce5		08		php		                PHP
+.396ce6		c2 20		rep #$20	                REP #$20        ; set A long
+.396ce8		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.396ceb		5b		tcd		                TCD
+.396cec		28		plp		                PLP
+.396ced		68		pla		                PLA             ; end setdp macro
+.396cee		48		pha		                PHA             ; begin setdbr macro
+.396cef		08		php		                PHP
+.396cf0		e2 20		sep #$20	                SEP #$20        ; set A short
+.396cf2		a9 00		lda #$00	                LDA #0
+.396cf4		48		pha		                PHA
+.396cf5		ab		plb		                PLB
+.396cf6		28		plp		                PLP
+.396cf7		68		pla		                PLA             ; end setdbr macro
+.396cf8		e2 20		sep #$20	                SEP #$20        ; set A short
+.396cfa		c2 10		rep #$10	                REP #$10        ; set X long
+.396cfc		c9 0a		cmp #$0a	                CMP #CHAR_LF        ; Linefeed moves cursor down one line
+.396cfe		f0 69		beq $396d69	                BEQ go_down
+.396d00		c9 20		cmp #$20	                CMP #$20
+.396d02		90 19		bcc $396d1d	                BCC check_ctrl0     ; [$00..$1F]: check for arrows
+.396d04		c9 7f		cmp #$7f	                CMP #$7F
+.396d06		f0 45		beq $396d4d	                BEQ do_del
+.396d08		b0 02		bcs $396d0c	                BCS check_A0        ; [$20..$7E]: print it
+.396d0a		80 31		bra $396d3d	                BRA printc
+.396d0c		c9 a0		cmp #$a0	check_A0        CMP #$A0
+.396d0e		90 02		bcc $396d12	                BCC check_ctrl1
+.396d10		80 2b		bra $396d3d	                BRA printc          ; [$A0..$FF]: print it
+.396d12		c9 91		cmp #$91	check_ctrl1     CMP #CHAR_DOWN      ; If the down arrow key was pressed
+.396d14		f0 53		beq $396d69	                BEQ go_down         ; ... move the cursor down one row
+.396d16		c9 9d		cmp #$9d	                CMP #CHAR_LEFT      ; If the left arrow key was pressed
+.396d18		f0 61		beq $396d7b	                BEQ go_left         ; ... move the cursor left one column
+.396d1a		4c 47 6d	jmp $396d47	                JMP done
+.396d1d		c9 09		cmp #$09	check_ctrl0     CMP #CHAR_TAB       ; If it's a TAB...
+.396d1f		f0 69		beq $396d8a	                BEQ do_TAB          ; ... move to the next TAB stop
+.396d21		c9 08		cmp #$08	                CMP #CHAR_BS        ; If it's a backspace...
+.396d23		f0 34		beq $396d59	                BEQ backspace       ; ... move the cursor back and replace with a space
+.396d25		c9 0d		cmp #$0d	                CMP #CHAR_CR        ; If the carriage return was pressed
+.396d27		f0 3a		beq $396d63	                BEQ do_cr           ; ... move cursor down and to the first column
+.396d29		c9 11		cmp #$11	                CMP #CHAR_UP        ; If the up arrow key was pressed
+.396d2b		f0 42		beq $396d6f	                BEQ go_up           ; ... move the cursor up one row
+.396d2d		c9 1d		cmp #$1d	                CMP #CHAR_RIGHT     ; If the right arrow key was pressed
+.396d2f		f0 44		beq $396d75	                BEQ go_right        ; ... move the cursor right one column
+.396d31		c9 0f		cmp #$0f	                CMP #CHAR_INS       ; If the insert key was pressed
+.396d33		f0 1e		beq $396d53	                BEQ do_ins          ; ... insert a space
+.396d35		c9 01		cmp #$01	                CMP #CHAR_CTRL_A    ; Check for CTRL-A (start of line)
+.396d37		f0 48		beq $396d81	                BEQ go_sol          ; ... move the cursor to the start of the line
+.396d39		c9 05		cmp #$05	                CMP #CHAR_CTRL_E    ; Check for CTRL-E (end of line)
+.396d3b		f0 74		beq $396db1	                BEQ go_eol          ; ... move the cursor to the end of the line
+.396d3d		87 6c		sta [$6c]	printc          STA [EVID_CURSORPOS]     ; Save the character on the screen
+.396d3f		a5 74		lda $74		                LDA EVID_CURCOLOR        ; Set the color based on CURCOLOR
+.396d41		87 75		sta [$75]	                STA [EVID_COLORPOS]
+.396d43		22 78 6e 39	jsl $396e78	                JSL EVID_ICSRRIGHT       ; And advance the cursor
+.396d47		28		plp		done            PLP
+.396d48		ab		plb		                PLB
+.396d49		2b		pld		                PLD
+.396d4a		7a		ply		                PLY
+.396d4b		fa		plx		                PLX
+.396d4c		6b		rtl		                RTL
+.396d4d		22 de 6d 39	jsl $396dde	do_del          JSL EVID_SCRSHIFTLL      ; Shift the current line left one space into the cursor
+.396d51		80 f4		bra $396d47	                BRA done
+.396d53		22 02 6e 39	jsl $396e02	do_ins          JSL EVID_SCRSHIFTLR      ; Shift the current line right one space from the cursor
+.396d57		80 ee		bra $396d47	                BRA done
+.396d59		22 ab 6e 39	jsl $396eab	backspace       JSL EVID_ICSRLEFT
+.396d5d		22 de 6d 39	jsl $396dde	                JSL EVID_SCRSHIFTLL      ; Shift the current line left one space into the cursor
+.396d61		80 e4		bra $396d47	                BRA done
+.396d63		22 3a 6e 39	jsl $396e3a	do_cr           JSL EVID_IPRINTCR        ; Move the cursor to the beginning of the next line
+.396d67		80 de		bra $396d47	                BRA done
+.396d69		22 f7 6e 39	jsl $396ef7	go_down         JSL EVID_ICSRDOWN        ; Move the cursor down one row (might force a scroll)
+.396d6d		80 d8		bra $396d47	                BRA done
+.396d6f		22 d1 6e 39	jsl $396ed1	go_up           JSL EVID_ICSRUP          ; Move the cursor up one line
+.396d73		80 d2		bra $396d47	                BRA done
+.396d75		22 78 6e 39	jsl $396e78	go_right        JSL EVID_ICSRRIGHT       ; Move the cursor right one column
+.396d79		80 cc		bra $396d47	                BRA done
+.396d7b		22 ab 6e 39	jsl $396eab	go_left         JSL EVID_ICSRLEFT        ; Move the cursor left one column
+.396d7f		80 c6		bra $396d47	                BRA done
+.396d81						go_sol
+.396d81		c2 20		rep #$20	                REP #$20        ; set A long
+.396d83		a2 00 00	ldx #$0000	                LDX #0
+.396d86		a4 72		ldy $72		                LDY EVID_CURSORY
+.396d88		80 21		bra $396dab	                BRA do_locate
+.396d8a						do_TAB
+.396d8a		c2 20		rep #$20	                REP #$20        ; set A long
+.396d8c		a5 70		lda $70		                LDA EVID_CURSORX         ; Get the current column
+.396d8e		29 f8 ff	and #$fff8	                AND #$FFF8          ; See which group of 8 it's in
+.396d91		18		clc		                CLC
+.396d92		69 08 00	adc #$0008	                ADC #$0008          ; And move it to the next one
+.396d95		aa		tax		                TAX
+.396d96		a4 72		ldy $72		                LDY EVID_CURSORY
+.396d98		e2 20		sep #$20	                SEP #$20        ; set A short
+.396d9a		e4 64		cpx $64		set_xy          CPX EVID_COLS_VISIBLE    ; Check if we're still on screen horizontally
+.396d9c		90 04		bcc $396da2	                BCC check_row       ; Yes: check the row
+.396d9e		a2 00 00	ldx #$0000	                LDX #0              ; No: move to the first column...
+.396da1		c8		iny		                INY                 ; ... and the next row
+.396da2		c4 68		cpy $68		check_row       CPY EVID_LINES_VISIBLE   ; Check if we're still on the screen vertically
+.396da4		90 05		bcc $396dab	                BCC do_locate       ; Yes: reposition the cursor
+.396da6		22 68 6f 39	jsl $396f68	                JSL EVID_ISCROLLUP       ; No: scroll the screen
+.396daa		88		dey		                DEY                 ; And set the row to the last one
+.396dab		22 1c 6f 39	jsl $396f1c	do_locate       JSL EVID_ILOCATE         ; Set the cursor position
+.396daf		80 96		bra $396d47	                BRA done
+.396db1		a6 64		ldx $64		go_eol          LDX EVID_COLS_VISIBLE    ; Move the cursor to the right most column
+.396db3		ca		dex		                DEX
+.396db4		a4 72		ldy $72		                LDY EVID_CURSORY
+.396db6		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE
+.396dba		e2 20		sep #$20	                SEP #$20        ; set A short
+.396dbc		a7 6c		lda [$6c]	eol_loop        LDA [EVID_CURSORPOS]     ; Get the character under the cursor
+.396dbe		c9 20		cmp #$20	                CMP #CHAR_SP        ; Is it blank?
+.396dc0		d0 0b		bne $396dcd	                BNE eol_done        ; No: exit the loop
+.396dc2		22 ab 6e 39	jsl $396eab	                JSL EVID_ICSRLEFT        ; Yes: move to the left
+.396dc6		a6 70		ldx $70		                LDX EVID_CURSORX         ; Are we at column 0?
+.396dc8		d0 f2		bne $396dbc	                BNE eol_loop        ; No: try again
+.396dca		82 7a ff	brl $396d47	                BRL done            ; Yes: we're done
+.396dcd		a6 70		ldx $70		eol_done        LDX EVID_CURSORX         ; Check the column
+.396dcf		e8		inx		                INX
+.396dd0		e4 64		cpx $64		                CPX EVID_COLS_VISIBLE    ; Is it the right most?
+.396dd2		d0 03		bne $396dd7	                BNE eol_right
+.396dd4		82 70 ff	brl $396d47	                BRL done            ; Yes: we're done
+.396dd7		22 78 6e 39	jsl $396e78	eol_right       JSL EVID_ICSRRIGHT       ; No: move right one column
+.396ddb		82 69 ff	brl $396d47	                BRL done
+.396dde						EVID_SCRSHIFTLL
+.396dde		da		phx		                PHX
+.396ddf		5a		phy		                PHY
+.396de0		48		pha		                PHA
+.396de1		0b		phd		                PHD
+.396de2		08		php		                PHP
+.396de3		48		pha		                PHA             ; begin setdp macro
+.396de4		08		php		                PHP
+.396de5		c2 20		rep #$20	                REP #$20        ; set A long
+.396de7		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.396dea		5b		tcd		                TCD
+.396deb		28		plp		                PLP
+.396dec		68		pla		                PLA             ; end setdp macro
+.396ded		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396def		a5 6c		lda $6c		                LDA EVID_CURSORPOS       ; Get the current cursor position
+.396df1		a8		tay		                TAY                 ; Set it as the destination
+.396df2		aa		tax		                TAX
+.396df3		e8		inx		                INX                 ; And set the next cell as the source
+.396df4		18		clc		                CLC                 ; Calculate the length of the block to move
+.396df5		a5 64		lda $64		                LDA EVID_COLS_VISIBLE    ; as columns visible - X
+.396df7		e5 70		sbc $70		                SBC EVID_CURSORX
+.396df9		54 ae ae	mvn $ae,$ae	                MVN $AE, $AE        ; And move the block
+.396dfc		28		plp		                PLP
+.396dfd		2b		pld		                PLD
+.396dfe		68		pla		                PLA
+.396dff		7a		ply		                PLY
+.396e00		fa		plx		                PLX
+.396e01		6b		rtl		                RTL
+.396e02						EVID_SCRSHIFTLR
+.396e02		da		phx		                PHX
+.396e03		48		pha		                PHA
+.396e04		0b		phd		                PHD
+.396e05		08		php		                PHP
+.396e06		48		pha		                PHA             ; begin setdp macro
+.396e07		08		php		                PHP
+.396e08		c2 20		rep #$20	                REP #$20        ; set A long
+.396e0a		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.396e0d		5b		tcd		                TCD
+.396e0e		28		plp		                PLP
+.396e0f		68		pla		                PLA             ; end setdp macro
+.396e10		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396e12		a5 70		lda $70		                LDA EVID_CURSORX         ; What column are we on
+.396e14		1a		inc a		                INC A
+.396e15		c5 64		cmp $64		                CMP EVID_COLS_VISIBLE    ; >= the # visible?
+.396e17		b0 1b		bcs $396e34	                BGE done            ; Yes: just skip the whole thing
+.396e19		38		sec		                SEC                 ; Calculate the length of the block to move
+.396e1a		a5 64		lda $64		                LDA EVID_COLS_VISIBLE
+.396e1c		e5 70		sbc $70		                SBC EVID_CURSORX
+.396e1e		1a		inc a		                INC A
+.396e1f		18		clc		                CLC
+.396e20		65 6c		adc $6c		                ADC EVID_CURSORPOS       ; Add the current cursor position
+.396e22		3a		dec a		                DEC A
+.396e23		a8		tay		                TAY                 ; Make it the destination
+.396e24		3a		dec a		                DEC A               ; Move to the previous column
+.396e25		aa		tax		                TAX                 ; Make it the source
+.396e26		38		sec		                SEC                 ; Calculate the length of the block to move
+.396e27		a5 64		lda $64		                LDA EVID_COLS_VISIBLE    ; as columns visible - X
+.396e29		e5 70		sbc $70		                SBC EVID_CURSORX
+.396e2b		44 ae ae	mvp $ae,$ae	                MVP $AE, $AE        ; And move the block
+.396e2e		e2 20		sep #$20	                SEP #$20        ; set A short
+.396e30		a9 20		lda #$20	                LDA #CHAR_SP        ; Put a blank space at the cursor position
+.396e32		87 6c		sta [$6c]	                STA [EVID_CURSORPOS]
+.396e34		28		plp		done            PLP
+.396e35		2b		pld		                PLD
+.396e36		68		pla		                PLA
+.396e37		fa		plx		                PLX
+.396e38		6b		rtl		                RTL
+.396e39						EVID_IPUTB
+.396e39		6b		rtl		                RTL
+.396e3a						EVID_IPRINTCR
+.396e3a		da		phx		                PHX
+.396e3b		5a		phy		                PHY
+.396e3c		8b		phb		                PHB
+.396e3d		0b		phd		                PHD
+.396e3e		08		php		                PHP
+.396e3f		48		pha		                PHA             ; begin setdbr macro
+.396e40		08		php		                PHP
+.396e41		e2 20		sep #$20	                SEP #$20        ; set A short
+.396e43		a9 00		lda #$00	                LDA #0
+.396e45		48		pha		                PHA
+.396e46		ab		plb		                PLB
+.396e47		28		plp		                PLP
+.396e48		68		pla		                PLA             ; end setdbr macro
+.396e49		48		pha		                PHA             ; begin setdp macro
+.396e4a		08		php		                PHP
+.396e4b		c2 20		rep #$20	                REP #$20        ; set A long
+.396e4d		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.396e50		5b		tcd		                TCD
+.396e51		28		plp		                PLP
+.396e52		68		pla		                PLA             ; end setdp macro
+.396e53		e2 20		sep #$20	                SEP #$20        ; set A short
+.396e55		c2 10		rep #$10	                REP #$10        ; set X long
+.396e57		a2 00 00	ldx #$0000	scr_printcr     LDX #0
+.396e5a		a4 72		ldy $72		                LDY EVID_CURSORY
+.396e5c		c8		iny		                INY
+.396e5d		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE
+.396e61		28		plp		done            PLP
+.396e62		2b		pld		                PLD
+.396e63		ab		plb		                PLB
+.396e64		7a		ply		                PLY
+.396e65		fa		plx		                PLX
+.396e66		6b		rtl		                RTL
+.396e67						EVID_ICSRHOME
+.396e67		da		phx		                PHX
+.396e68		5a		phy		                PHY
+.396e69		08		php		                PHP
+.396e6a		a2 00 00	ldx #$0000	                LDX #0
+.396e6d		a0 00 00	ldy #$0000	                LDY #0
+.396e70		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE
+.396e74		28		plp		                PLP
+.396e75		7a		ply		                PLY
+.396e76		fa		plx		                PLX
+.396e77		6b		rtl		                RTL
+.396e78						EVID_ICSRRIGHT
+.396e78		da		phx		                PHX
+.396e79		5a		phy		                PHY
+.396e7a		48		pha		                PHA
+.396e7b		0b		phd		                PHD
+.396e7c		08		php		                PHP
+.396e7d		c2 20		rep #$20	                REP #$20        ; set A long
+.396e7f		c2 10		rep #$10	                REP #$10        ; set X long
+.396e81		48		pha		                PHA             ; begin setdp macro
+.396e82		08		php		                PHP
+.396e83		c2 20		rep #$20	                REP #$20        ; set A long
+.396e85		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.396e88		5b		tcd		                TCD
+.396e89		28		plp		                PLP
+.396e8a		68		pla		                PLA             ; end setdp macro
+.396e8b		a6 70		ldx $70		                LDX EVID_CURSORX           ; Get the new column
+.396e8d		e8		inx		                INX
+.396e8e		a4 72		ldy $72		                LDY EVID_CURSORY           ; Get the current row
+.396e90		e4 64		cpx $64		                CPX EVID_COLS_VISIBLE      ; Are we off screen?
+.396e92		90 0d		bcc $396ea1	                BCC icsrright_nowrap  ; No: just set the position
+.396e94		a2 00 00	ldx #$0000	                LDX #0                ; Yes: move to the first column
+.396e97		c8		iny		                INY                   ; And move to the next row
+.396e98		c4 68		cpy $68		                CPY EVID_LINES_VISIBLE     ; Are we still off screen?
+.396e9a		90 05		bcc $396ea1	                BCC icsrright_nowrap  ; No: just set the position
+.396e9c		88		dey		                DEY                   ; Yes: lock to the last row
+.396e9d		22 68 6f 39	jsl $396f68	                JSL EVID_ISCROLLUP         ; But scroll the screen up
+.396ea1						icsrright_nowrap
+.396ea1		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE           ; Set the cursor position
+.396ea5		28		plp		                PLP
+.396ea6		2b		pld		                PLD
+.396ea7		68		pla		                PLA
+.396ea8		7a		ply		                PLY
+.396ea9		fa		plx		                PLX
+.396eaa		6b		rtl		                RTL
+.396eab						EVID_ICSRLEFT
+.396eab		da		phx		                PHX
+.396eac		5a		phy		                PHY
+.396ead		48		pha		                PHA
+.396eae		0b		phd		                PHD
+.396eaf		08		php		                PHP
+.396eb0		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396eb2		48		pha		                PHA             ; begin setdp macro
+.396eb3		08		php		                PHP
+.396eb4		c2 20		rep #$20	                REP #$20        ; set A long
+.396eb6		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.396eb9		5b		tcd		                TCD
+.396eba		28		plp		                PLP
+.396ebb		68		pla		                PLA             ; end setdp macro
+.396ebc		a5 70		lda $70		                LDA EVID_CURSORX
+.396ebe		f0 0b		beq $396ecb	                BEQ icsrleft_done_already_zero ; Check that we are not already @ Zero
+.396ec0		a6 70		ldx $70		                LDX EVID_CURSORX
+.396ec2		ca		dex		                DEX
+.396ec3		86 70		stx $70		                STX EVID_CURSORX
+.396ec5		a4 72		ldy $72		                LDY EVID_CURSORY
+.396ec7		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE
+.396ecb						icsrleft_done_already_zero
+.396ecb		28		plp		                PLP
+.396ecc		2b		pld		                PLD
+.396ecd		68		pla		                PLA
+.396ece		7a		ply		                PLY
+.396ecf		fa		plx		                PLX
+.396ed0		6b		rtl		                RTL
+.396ed1						EVID_ICSRUP
+.396ed1		da		phx		                PHX
+.396ed2		5a		phy		                PHY
+.396ed3		48		pha		                PHA
+.396ed4		0b		phd		                PHD
+.396ed5		08		php		                PHP
+.396ed6		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396ed8		48		pha		                PHA             ; begin setdp macro
+.396ed9		08		php		                PHP
+.396eda		c2 20		rep #$20	                REP #$20        ; set A long
+.396edc		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.396edf		5b		tcd		                TCD
+.396ee0		28		plp		                PLP
+.396ee1		68		pla		                PLA             ; end setdp macro
+.396ee2		a5 72		lda $72		                LDA EVID_CURSORY
+.396ee4		f0 0b		beq $396ef1	                BEQ isrup_done_already_zero ; Check if we are not already @ Zero
+.396ee6		a4 72		ldy $72		                LDY EVID_CURSORY
+.396ee8		88		dey		                DEY
+.396ee9		84 72		sty $72		                STY EVID_CURSORY
+.396eeb		a6 70		ldx $70		                LDX EVID_CURSORX
+.396eed		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE
+.396ef1						isrup_done_already_zero
+.396ef1		28		plp		                PLP
+.396ef2		2b		pld		                PLD
+.396ef3		68		pla		                PLA
+.396ef4		7a		ply		                PLY
+.396ef5		fa		plx		                PLX
+.396ef6		6b		rtl		                RTL
+.396ef7						EVID_ICSRDOWN
+.396ef7		da		phx		                PHX
+.396ef8		5a		phy		                PHY
+.396ef9		0b		phd		                PHD
+.396efa		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396efc		48		pha		                PHA             ; begin setdp macro
+.396efd		08		php		                PHP
+.396efe		c2 20		rep #$20	                REP #$20        ; set A long
+.396f00		a9 00 00	lda #$0000	                LDA #$0         ; set DP to page 0
+.396f03		5b		tcd		                TCD
+.396f04		28		plp		                PLP
+.396f05		68		pla		                PLA             ; end setdp macro
+.396f06		a6 70		ldx $70		                LDX EVID_CURSORX                 ; Get the current column
+.396f08		a4 72		ldy $72		                LDY EVID_CURSORY                 ; Get the new row
+.396f0a		c8		iny		                INY
+.396f0b		c4 68		cpy $68		                CPY EVID_LINES_VISIBLE           ; Check to see if we're off screen
+.396f0d		90 05		bcc $396f14	                BCC icsrdown_noscroll       ; No: go ahead and set the position
+.396f0f		88		dey		                DEY                         ; Yes: go back to the last row
+.396f10		22 68 6f 39	jsl $396f68	                JSL EVID_ISCROLLUP               ; But scroll the screen up
+.396f14						icsrdown_noscroll
+.396f14		22 1c 6f 39	jsl $396f1c	                JSL EVID_ILOCATE                 ; And set the cursor position
+.396f18		2b		pld		                PLD
+.396f19		7a		ply		                PLY
+.396f1a		fa		plx		                PLX
+.396f1b		6b		rtl		                RTL
+.396f1c						EVID_ILOCATE
+.396f1c		48		pha		                PHA
+.396f1d		0b		phd		                PHD
+.396f1e		08		php		                PHP
+.396f1f		48		pha		                PHA             ; begin setdp macro
+.396f20		08		php		                PHP
+.396f21		c2 20		rep #$20	                REP #$20        ; set A long
+.396f23		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.396f26		5b		tcd		                TCD
+.396f27		28		plp		                PLP
+.396f28		68		pla		                PLA             ; end setdp macro
+.396f29		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396f2b						ilocate_scroll
+.396f2b		c4 68		cpy $68		                CPY EVID_LINES_VISIBLE
+.396f2d		90 07		bcc $396f36	                BCC ilocate_scrolldone
+.396f2f		22 68 6f 39	jsl $396f68	                JSL EVID_ISCROLLUP
+.396f33		88		dey		                DEY
+.396f34		80 f5		bra $396f2b	                BRA ilocate_scroll
+.396f36						ilocate_scrolldone
+.396f36		86 70		stx $70		                STX EVID_CURSORX
+.396f38		84 72		sty $72		                STY EVID_CURSORY
+.396f3a		a5 60		lda $60		                LDA EVID_SCREENBEGIN
+.396f3c						ilocate_row
+.396f3c		c0 00 00	cpy #$0000	                CPY #$0
+.396f3f		f0 08		beq $396f49	                BEQ ilocate_right
+.396f41		18		clc		ilocate_down    CLC
+.396f42		65 66		adc $66		                ADC EVID_COLS_PER_LINE
+.396f44		88		dey		                DEY
+.396f45		f0 02		beq $396f49	                BEQ ilocate_right
+.396f47		80 f8		bra $396f41	                BRA ilocate_down
+.396f49		18		clc		ilocate_right   CLC
+.396f4a		65 70		adc $70		                ADC EVID_CURSORX             ; move the cursor right X columns
+.396f4c		85 6c		sta $6c		                STA EVID_CURSORPOS
+.396f4e		a4 72		ldy $72		                LDY EVID_CURSORY
+.396f50		98		tya		                TYA
+.396f51		8f 16 1e ae	sta $ae1e16	                STA @lEVID_TXT_CURSOR_Y_REG_L  ;Store in Vicky's registers
+.396f55		8a		txa		                TXA
+.396f56		8f 14 1e ae	sta $ae1e14	                STA @lEVID_TXT_CURSOR_X_REG_L  ;Store in Vicky's register
+.396f5a		c2 20		rep #$20	                REP #$20        ; set A long
+.396f5c		18		clc		                CLC
+.396f5d		a5 6c		lda $6c		                LDA EVID_CURSORPOS
+.396f5f		69 00 20	adc #$2000	                ADC #<>(EVID_COLOR_MEM - EVID_TEXT_MEM)
+.396f62		85 75		sta $75		                STA EVID_COLORPOS
+.396f64		28		plp		ilocate_done    PLP
+.396f65		2b		pld		                PLD
+.396f66		68		pla		                PLA
+.396f67		6b		rtl		                RTL
+.396f68						EVID_ISCROLLUP
+.396f68		48		pha		                PHA
+.396f69		da		phx		                PHX
+.396f6a		5a		phy		                PHY
+.396f6b		8b		phb		                PHB
+.396f6c		0b		phd		                PHD
+.396f6d		08		php		                PHP
+.396f6e		48		pha		                PHA             ; begin setdp macro
+.396f6f		08		php		                PHP
+.396f70		c2 20		rep #$20	                REP #$20        ; set A long
+.396f72		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.396f75		5b		tcd		                TCD
+.396f76		28		plp		                PLP
+.396f77		68		pla		                PLA             ; end setdp macro
+.396f78		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396f7a		a5 66		lda $66		                LDA EVID_COLS_PER_LINE
+.396f7c		8f 00 01 00	sta $000100	                STA @l UNSIGNED_MULT_A_LO
+.396f80		a5 68		lda $68		                LDA EVID_LINES_VISIBLE
+.396f82		8f 02 01 00	sta $000102	                STA @l UNSIGNED_MULT_B_LO
+.396f86		af 04 01 00	lda $000104	                LDA @l UNSIGNED_MULT_AL_LO
+.396f8a		85 76		sta $76		                STA EVID_TMPPTR1
+.396f8c		18		clc		                CLC
+.396f8d		a9 00 20	lda #$2000	                LDA #$2000
+.396f90		a8		tay		                TAY
+.396f91		65 66		adc $66		                ADC EVID_COLS_PER_LINE
+.396f93		aa		tax		                TAX
+.396f94		a5 76		lda $76		                LDA EVID_TMPPTR1
+.396f96		54 ae ae	mvn $ae,$ae	                MVN $AE,$AE
+.396f99		c2 30		rep #$30	                REP #$30        ; set A&X long
+.396f9b		18		clc		                CLC
+.396f9c		a9 00 40	lda #$4000	                LDA #$4000
+.396f9f		a8		tay		                TAY
+.396fa0		65 66		adc $66		                ADC EVID_COLS_PER_LINE
+.396fa2		aa		tax		                TAX
+.396fa3		a5 76		lda $76		                LDA EVID_TMPPTR1
+.396fa5		54 ae ae	mvn $ae,$ae	                MVN $AE,$AE
+.396fa8		a5 76		lda $76		                LDA EVID_TMPPTR1
+.396faa		48		pha		                PHA
+.396fab		18		clc		                CLC
+.396fac		69 00 20	adc #$2000	                ADC #<>EVID_TEXT_MEM
+.396faf		85 76		sta $76		                STA EVID_TMPPTR1
+.396fb1		a0 00 00	ldy #$0000	                LDY #0
+.396fb4		a9 20 00	lda #$0020	                LDA #' '
+.396fb7		97 76		sta [$76],y	clr_text        STA [EVID_TMPPTR1],Y
+.396fb9		c8		iny		                INY
+.396fba		c4 64		cpy $64		                CPY EVID_COLS_VISIBLE
+.396fbc		d0 f9		bne $396fb7	                BNE clr_text
+.396fbe		68		pla		                PLA
+.396fbf		18		clc		                CLC
+.396fc0		69 00 40	adc #$4000	                ADC #<>EVID_COLOR_MEM
+.396fc3		85 76		sta $76		                STA EVID_TMPPTR1
+.396fc5		a0 00 00	ldy #$0000	                LDY #0
+.396fc8		a5 74		lda $74		                LDA EVID_CURCOLOR
+.396fca		97 76		sta [$76],y	clr_color       STA [EVID_TMPPTR1],Y
+.396fcc		c8		iny		                INY
+.396fcd		c4 64		cpy $64		                CPY EVID_COLS_VISIBLE
+.396fcf		d0 f9		bne $396fca	                BNE clr_color
+.396fd1		28		plp		                PLP
+.396fd2		2b		pld		                PLD
+.396fd3		ab		plb		                PLB
+.396fd4		7a		ply		                PLY
+.396fd5		fa		plx		                PLX
+.396fd6		68		pla		                PLA
+.396fd7		6b		rtl		                RTL
+.396fd8						EVID_IPRINTH
+.396fd8		08		php		                PHP
+.396fd9		48		pha		                PHA
+.396fda						iprinth1
+.396fda		e2 20		sep #$20	                SEP #$20        ; set A short
+.396fdc		bd 00 00	lda $0000,x	                LDA #0,b,x      ; Read the value to be printed
+.396fdf		4a		lsr a		                LSR
+.396fe0		4a		lsr a		                LSR
+.396fe1		4a		lsr a		                LSR
+.396fe2		4a		lsr a		                LSR
+.396fe3		22 32 70 39	jsl $397032	                JSL EVID_iprint_digit
+.396fe7		bd 00 00	lda $0000,x	                LDA #0,b,x
+.396fea		22 32 70 39	jsl $397032	                JSL EVID_iprint_digit
+.396fee		ca		dex		                DEX
+.396fef		88		dey		                DEY
+.396ff0		d0 e8		bne $396fda	                BNE iprinth1
+.396ff2		68		pla		                PLA
+.396ff3		28		plp		                PLP
+.396ff4		6b		rtl		                RTL
+.396ff5						EVID_IPRINTAH
+.396ff5		48		pha		                PHA
+.396ff6		08		php		                PHP
+.396ff7		8f 44 02 00	sta $000244	                STA @lCPUA            ; Save A where we can use it multiple times
+.396ffb		08		php		                PHP                   ; Get the processor status into A
+.396ffc		e2 20		sep #$20	                SEP #$20        ; set A short
+.396ffe		c2 10		rep #$10	                REP #$10        ; set X long
+.397000		68		pla		                PLA
+.397001		29 20		and #$20	                AND #%00100000        ; Is M = 1?
+.397003		c9 20		cmp #$20	                CMP #%00100000
+.397005		f0 14		beq $39701b	                BEQ eight_bit
+.397007		af 46 02 00	lda $000246	                LDA @lCPUA+2          ; Get nibble [15..12]
+.39700b		4a		lsr a		                LSR A
+.39700c		4a		lsr a		                LSR A
+.39700d		4a		lsr a		                LSR A
+.39700e		4a		lsr a		                LSR A
+.39700f		22 32 70 39	jsl $397032	                JSL EVID_iprint_digit      ; And print it
+.397013		af 46 02 00	lda $000246	                LDA @lCPUA+2          ; Get nibble [11..8]
+.397017		22 32 70 39	jsl $397032	                JSL EVID_iprint_digit      ; And print it
+.39701b		af 44 02 00	lda $000244	eight_bit       LDA @lCPUA            ; Get nibble [7..4]
+.39701f		4a		lsr a		                LSR A
+.397020		4a		lsr a		                LSR A
+.397021		4a		lsr a		                LSR A
+.397022		4a		lsr a		                LSR A
+.397023		22 32 70 39	jsl $397032	                JSL EVID_iprint_digit      ; And print it
+.397027		af 44 02 00	lda $000244	                LDA @lCPUA            ; Get nibble [3..0]
+.39702b		22 32 70 39	jsl $397032	                JSL EVID_iprint_digit      ; And print it
+.39702f		28		plp		                PLP
+.397030		68		pla		                PLA
+.397031		6b		rtl		                RTL
+.397032						EVID_iprint_digit
+.397032		da		phx		                PHX
+.397033		c2 20		rep #$20	                REP #$20        ; set A long
+.397035		29 0f 00	and #$000f	                AND #$0F
+.397038		aa		tax		                TAX
+.397039		bf 48 76 39	lda $397648,x	                LDA hex_digits,X
+.39703d		22 df 6c 39	jsl $396cdf	                JSL EVID_IPUTC       ; Print the digit
+.397041		fa		plx		                PLX
+.397042		6b		rtl		                RTL
+.397043						INIT_EVID_VID_MODE
+.397043		e2 20		sep #$20	                SEP #$20        ; set A short
+.397045		a9 01		lda #$01	                LDA #EVID_800x600ModeEnable          ; 0 - 80x60, 1- 100x75
+.397047		8f 01 1e ae	sta $ae1e01	                STA @l EVID_MSTR_CTRL_REG_H
+.39704b		a9 01		lda #$01	                LDA #EVID_Border_Ctrl_Enable           ; Enable the Border
+.39704d		8f 04 1e ae	sta $ae1e04	                STA EVID_BORDER_CTRL_REG
+.397051		a9 08		lda #$08	                LDA #8                           ; Set the border to the standard 8 pixels
+.397053		8f 08 1e ae	sta $ae1e08	                STA EVID_BORDER_X_SIZE          ; Let's use maximum space
+.397057		8f 09 1e ae	sta $ae1e09	                STA EVID_BORDER_Y_SIZE
+.39705b		a9 20		lda #$20	                LDA #$20
+.39705d		8f 07 1e ae	sta $ae1e07	                STA EVID_BORDER_COLOR_R        ; R
+.397061		a9 00		lda #$00	                LDA #$00
+.397063		8f 06 1e ae	sta $ae1e06	                STA EVID_BORDER_COLOR_G        ; G
+.397067		a9 20		lda #$20	                LDA #$20
+.397069		8f 05 1e ae	sta $ae1e05	                STA EVID_BORDER_COLOR_B        ; B
+.39706d		22 3f 71 39	jsl $39713f	                JSL INIT_EVID_EVID_LUT
+.397071		22 28 71 39	jsl $397128	                JSL INIT_EVID_EVID_FONTSET
+.397075		22 63 71 39	jsl $397163	                JSL INIT_EVID_EVID_CURSOR
+.397079		c2 30		rep #$30	                REP #$30        ; set A&X long
+.39707b		a2 62 00	ldx #$0062	                LDX #(100-2)
+.39707e		86 64		stx $64		                STX EVID_COLS_VISIBLE
+.397080		a0 49 00	ldy #$0049	                LDY #(75-2)
+.397083		84 68		sty $68		                STY EVID_LINES_VISIBLE
+.397085		a2 64 00	ldx #$0064	                LDX #100
+.397088		86 66		stx $66		                STX EVID_COLS_PER_LINE
+.39708a		a0 4b 00	ldy #$004b	                LDY #75
+.39708d		84 6a		sty $6a		                STY EVID_LINES_MAX
+.39708f		a9 f0 00	lda #$00f0	                LDA #$F0                  ; Set the default text color to light gray on dark gray
+.397092		85 74		sta $74		                STA EVID_CURCOLOR
+.397094		c2 30		rep #$30	                REP #$30        ; set A&X long
+.397096		a9 00 20	lda #$2000	                LDA #<>EVID_TEXT_MEM      ; store the initial screen buffer location
+.397099		85 60		sta $60		                STA EVID_SCREENBEGIN
+.39709b		85 6c		sta $6c		                STA EVID_CURSORPOS
+.39709d		a9 00 40	lda #$4000	                LDA #<>EVID_COLOR_MEM   ; Set the initial COLOR cursor position
+.3970a0		85 75		sta $75		                STA EVID_COLORPOS
+.3970a2		e2 20		sep #$20	                SEP #$20        ; set A short
+.3970a4		a9 ae		lda #$ae	                LDA #`EVID_TEXT_MEM
+.3970a6		85 0e		sta $0e		                STA SCREENBEGIN + 2
+.3970a8		85 6e		sta $6e		                STA EVID_CURSORPOS+2
+.3970aa		a9 ae		lda #$ae	                LDA #`EVID_COLOR_MEM    ; Set the initial COLOR cursor position
+.3970ac		85 77		sta $77		                STA EVID_COLORPOS + 2
+.3970ae		22 81 71 39	jsl $397181	                JSL INIT_EVID_EVID_CLRSCREEN
+.3970b2		c2 10		rep #$10	                REP #$10        ; set X long
+.3970b4		0b		phd		                PHD
+.3970b5		48		pha		                PHA             ; begin setdbr macro
+.3970b6		08		php		                PHP
+.3970b7		e2 20		sep #$20	                SEP #$20        ; set A short
+.3970b9		a9 39		lda #$39	                LDA #`EVID_DEV_RDY0
+.3970bb		48		pha		                PHA
+.3970bc		ab		plb		                PLB
+.3970bd		28		plp		                PLP
+.3970be		68		pla		                PLA             ; end setdbr macro
+.3970bf		a2 e0 70	ldx #$70e0	                LDX #<>EVID_DEV_RDY0
+.3970c2		22 bf 6c 39	jsl $396cbf	                JSL EVID_IPRINT
+.3970c6		a2 10 71	ldx #$7110	                LDX #<>EVID_DEV_RDY1
+.3970c9		22 bf 6c 39	jsl $396cbf	                JSL EVID_IPRINT
+.3970cd		2b		pld		                PLD
+.3970ce		a2 00 00	ldx #$0000	                LDX #$0000
+.3970d1						LifeIsFullOfColors:
+.3970d1		bf 06 71 39	lda $397106,x	                LDA @l EVID_DEV_RDY0_CLR, X
+.3970d5		9f 00 40 ae	sta $ae4000,x	                STA @l EVID_COLOR_MEM, X
+.3970d9		e8		inx		                INX
+.3970da		e0 0a 00	cpx #$000a	                CPX #10
+.3970dd		d0 f2		bne $3970d1	                BNE LifeIsFullOfColors
+.3970df		6b		rtl		                RTL
+>3970e0		0b 0c 0b 0c 0b 0c 0b 0c		EVID_DEV_RDY0  .null $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "C256 Foenix EXP-C200-EVID", $0D
+>3970e8		0b 0c 20 43 32 35 36 20 46 6f 65 6e 69 78 20 45
+>3970f8		58 50 2d 43 32 30 30 2d 45 56 49 44 0d 00
+>397106		1d 1d 8d 8d 4d 4d 2d 2d		EVID_DEV_RDY0_CLR .text $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D
+>39710e		5d 5d
+>397110		59 6f 75 72 20 44 65 76		EVID_DEV_RDY1  .null "Your Device is Ready..."
+>397118		69 63 65 20 69 73 20 52 65 61 64 79 2e 2e 2e 00
+=100						TXTLINESIZE = 100
+.397128						INIT_EVID_EVID_FONTSET
+.397128		e2 20		sep #$20	                SEP #$20        ; set A short
+.39712a		c2 10		rep #$10	                REP #$10        ; set X long
+.39712c		a2 00 00	ldx #$0000	                LDX #$0000
+.39712f						initFontsetbranch0
+.39712f		bf 00 00 3f	lda $3f0000,x	                LDA @lFONT_4_BANK0,X    ; RAM Content
+.397133		9f 00 10 ae	sta $ae1000,x	                STA @lEVID_FONT_MEM,X ; Vicky FONT RAM Bank
+.397137		e8		inx		                INX
+.397138		e0 00 08	cpx #$0800	                CPX #$0800
+.39713b		d0 f2		bne $39712f	                BNE initFontsetbranch0
+.39713d		ea		nop		                NOP
+.39713e		6b		rtl		                RTL
+.39713f						INIT_EVID_EVID_LUT
+.39713f		e2 20		sep #$20	                SEP #$20        ; set A short
+.397141		e2 10		sep #$10	                SEP #$10        ; set X short
+.397143		a2 00		ldx #$00					        LDX	#$00
+.397145		bf 77 73 39	lda $397377,x	lutinitloop0	LDA @lfg_color_lut,x		; get Local Data c64_character_Color_LUT_4_Txt
+.397149		9f 00 1b ae	sta $ae1b00,x	                STA @lEVID_FG_LUT,x	; Write in LUT Memory
+.39714d		e8		inx		                inx
+.39714e		e0 40		cpx #$40	                cpx #$40
+.397150		d0 f3		bne $397145	                bne lutinitloop0
+.397152		a2 00		ldx #$00	                LDX	#$00
+.397154		bf b7 73 39	lda $3973b7,x	lutinitloop1	LDA @lbg_color_lut,x		; get Local Data
+.397158		9f 40 1b ae	sta $ae1b40,x	                STA @lEVID_BG_LUT,x	; Write in LUT Memory
+.39715c		e8		inx		                INX
+.39715d		e0 40		cpx #$40	                CPX #$40
+.39715f		d0 f3		bne $397154	                bne lutinitloop1
+.397161		ea		nop		                NOP
+.397162		6b		rtl		                RTL
+.397163						INIT_EVID_EVID_CURSOR
+.397163		e2 20		sep #$20	                SEP #$20        ; set A short
+.397165		a9 b1		lda #$b1	                LDA #$B1      ;The Cursor Character will be a Fully Filled Block
+.397167		8f 12 1e ae	sta $ae1e12	                STA @lEVID_TXT_CURSOR_CHAR_REG
+.39716b		a9 03		lda #$03	                LDA #(EVID_Cursor_Enable | EVID_Cursor_Flash_Rate0)      ;Set Cursor Enable And Flash Rate @1Hz
+.39716d		8f 10 1e ae	sta $ae1e10	                STA @lEVID_TXT_CURSOR_CTRL_REG ;
+.397171		c2 30		rep #$30	                REP #$30        ; set A&X long
+.397173		a9 00 00	lda #$0000	                LDA #$0000;
+.397176		8f 14 1e ae	sta $ae1e14	                STA @lEVID_TXT_CURSOR_X_REG_L ;; // Set the X to Position 1
+.39717a		8f 16 1e ae	sta $ae1e16	                STA @lEVID_TXT_CURSOR_Y_REG_L ; // Set the Y to Position 6 (Below)
+.39717e		e2 20		sep #$20	                SEP #$20        ; set A short
+.397180		6b		rtl		                RTL
+.397181						INIT_EVID_EVID_CLRSCREEN
+.397181		e2 20		sep #$20	                SEP #$20        ; set A short
+.397183		c2 10		rep #$10	                REP #$10        ; set X long
+.397185		a2 00 00	ldx #$0000	                LDX #$0000		; Only Use One Pointer
+.397188		a9 20		lda #$20	                LDA #$20		; Fill the Entire Screen with Space
+.39718a		9f 00 20 ae	sta $ae2000,x	iclearloop0	    STA EVID_TEXT_MEM, x	;
+.39718e		e8		inx		                inx
+.39718f		e0 00 20	cpx #$2000	                cpx #$2000
+.397192		d0 f6		bne $39718a	                bne iclearloop0
+.397194		a2 00 00	ldx #$0000	                LDX	#$0000		; Only Use One Pointer
+.397197		a9 f0		lda #$f0	                LDA #$F0		; Fill the Color Memory with Foreground: 75% Purple, Background 12.5% White
+.397199		9f 00 40 ae	sta $ae4000,x	iclearloop1	    STA EVID_COLOR_MEM, x	;
+.39719d		e8		inx		                inx
+.39719e		e0 00 20	cpx #$2000	                cpx #$2000
+.3971a1		d0 f6		bne $397199	                bne iclearloop1
+.3971a3		6b		rtl		                RTL
+
+;******  Return to file: src\kernel.asm
+
+.3971a4						    KERNEL_DATA
+>3971a4		20 20 20 20 0b 0c 0b 0c		    greet_msg   .text $20, $20, $20, $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, " UU    UU   +" ,$0D
+>3971ac		0b 0c 0b 0c 0b 0c 20 55 55 20 20 20 20 55 55 20
+>3971bc		20 20 2b 0d
+>3971c0		20 20 20 0b 0c 0b 0c 0b		                .text $20, $20, $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "UU    UU   +",$0D
+>3971c8		0c 0b 0c 0b 0c 20 55 55 20 20 20 20 55 55 20 20
+>3971d8		20 2b 0d
+>3971db		20 20 0b 0c 0b 0c 0b 0c		                .text $20, $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "UU    UU +++++",$0D
+>3971e3		0b 0c 0b 0c 20 55 55 20 20 20 20 55 55 20 2b 2b
+>3971f3		2b 2b 2b 0d
+>3971f7		20 0b 0c 0b 0c 0b 0c 0b		                .text $20, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "UU    UU   +",$0D
+>3971ff		0c 0b 0c 20 55 55 20 20 20 20 55 55 20 20 20 2b
+>39720f		0d
+>397210		0b 0c 0b 0c 0b 0c 0b 0c		                .text $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $0B, $0C, $20, "UUUUUUUU   +",$0D
+>397218		0b 0c 20 55 55 55 55 55 55 55 55 20 20 20 2b 0d
+>397228		0d 43 32 35 36 20 46 4f		                .text $0D, "C256 FOENIX U+ -- 3,670,016 Bytes Free", $0D
+>397230		45 4e 49 58 20 55 2b 20 2d 2d 20 33 2c 36 37 30
+>397240		2c 30 31 36 20 42 79 74 65 73 20 46 72 65 65 0d
+>397250		77 77 77 2e 63 32 35 36		                .text "www.c256foenix.com - Kernel Date: February 2nd, 2021",$0D
+>397258		66 6f 65 6e 69 78 2e 63 6f 6d 20 2d 20 4b 65 72
+>397268		6e 65 6c 20 44 61 74 65 3a 20 46 65 62 72 75 61
+>397278		72 79 20 32 6e 64 2c 20 32 30 32 31 0d
+
+;******  Processing file: src\version.asm
+
+>397285		76 30 2e 33 2e 30 2d 61		.text "v0.3.0-alpha+1369 (2021-02-08)"
+>39728d		6c 70 68 61 2b 31 33 36 39 20 28 32 30 32 31 2d
+>39729d		30 32 2d 30 38 29
+
+;******  Return to file: src\kernel.asm
+
+>3972a3		0d 00				                .text $0D,$00
+>3972a5		1d 1d 1d 1d 1d 1d 8d 8d		  greet_clr_line1 .text $1D, $1D, $1D, $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
+>3972ad		4d 4d 2d 2d 5d 5d fd fd fd fd fd fd fd fd fd fd
+>3972bd		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
+>3972cd		fd fd
+>3972cf		1d 1d 1d 1d 1d 8d 8d 4d		  greet_clr_line2 .text $1D, $1D, $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
+>3972d7		4d 2d 2d 5d 5d fd fd fd fd fd fd fd fd fd fd fd
+>3972e7		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
+>3972f7		fd fd
+>3972f9		1d 1d 1d 1d 8d 8d 4d 4d		  greet_clr_line3 .text $1D, $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
+>397301		2d 2d 5d 5d fd fd fd fd fd fd fd fd fd fd fd fd
+>397311		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
+>397321		fd fd
+>397323		1d 1d 1d 8d 8d 4d 4d 2d		  greet_clr_line4 .text $1D, $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
+>39732b		2d 5d 5d fd fd fd fd fd fd fd fd fd fd fd fd fd
+>39733b		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
+>39734b		fd fd
+>39734d		1d 1d 8d 8d 4d 4d 2d 2d		  greet_clr_line5 .text $1D, $1D, $8D, $8D, $4D, $4D, $2D, $2D, $5D, $5D, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD, $FD
+>397355		5d 5d fd fd fd fd fd fd fd fd fd fd fd fd fd fd
+>397365		fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd fd
+>397375		fd fd
+>397377		00 00 00 ff			fg_color_lut	  .text $00, $00, $00, $FF
+>39737b		00 00 80 ff			                .text $00, $00, $80, $FF
+>39737f		00 80 00 ff			                .text $00, $80, $00, $FF
+>397383		80 00 00 ff			                .text $80, $00, $00, $FF
+>397387		00 80 80 ff			                .text $00, $80, $80, $FF
+>39738b		80 80 00 ff			                .text $80, $80, $00, $FF
+>39738f		80 00 80 ff			                .text $80, $00, $80, $FF
+>397393		80 80 80 ff			                .text $80, $80, $80, $FF
+>397397		00 45 ff ff			                .text $00, $45, $FF, $FF
+>39739b		13 45 8b ff			                .text $13, $45, $8B, $FF
+>39739f		00 00 20 ff			                .text $00, $00, $20, $FF
+>3973a3		00 20 00 ff			                .text $00, $20, $00, $FF
+>3973a7		20 00 00 ff			                .text $20, $00, $00, $FF
+>3973ab		20 20 20 ff			                .text $20, $20, $20, $FF
+>3973af		40 40 40 ff			                .text $40, $40, $40, $FF
+>3973b3		ff ff ff ff			                .text $FF, $FF, $FF, $FF
+>3973b7		00 00 00 ff			bg_color_lut	  .text $00, $00, $00, $FF
+>3973bb		00 00 80 ff			                .text $00, $00, $80, $FF
+>3973bf		00 80 00 ff			                .text $00, $80, $00, $FF
+>3973c3		80 00 00 ff			                .text $80, $00, $00, $FF
+>3973c7		00 20 20 ff			                .text $00, $20, $20, $FF
+>3973cb		20 20 00 ff			                .text $20, $20, $00, $FF
+>3973cf		20 00 20 ff			                .text $20, $00, $20, $FF
+>3973d3		20 20 20 ff			                .text $20, $20, $20, $FF
+>3973d7		1e 69 d2 ff			                .text $1E, $69, $D2, $FF
+>3973db		13 45 8b ff			                .text $13, $45, $8B, $FF
+>3973df		00 00 20 ff			                .text $00, $00, $20, $FF
+>3973e3		00 20 00 ff			                .text $00, $20, $00, $FF
+>3973e7		40 00 00 ff			                .text $40, $00, $00, $FF
+>3973eb		10 10 10 ff			                .text $10, $10, $10, $FF
+>3973ef		40 40 40 ff			                .text $40, $40, $40, $FF
+>3973f3		ff ff ff ff			                .text $FF, $FF, $FF, $FF
+>3973f7		43 6d 64 20 30 78 41 41		pass_tst0xAAmsg .text "Cmd 0xAA Test passed...", $0D, $00
+>3973ff		20 54 65 73 74 20 70 61 73 73 65 64 2e 2e 2e 0d
+>39740f		00
+>397410		43 6d 64 20 30 78 41 42		pass_tst0xABmsg .text "Cmd 0xAB Test passed...", $0D, $00
+>397418		20 54 65 73 74 20 70 61 73 73 65 64 2e 2e 2e 0d
+>397428		00
+>397429		43 6d 64 20 30 78 36 30		pass_cmd0x60msg .text "Cmd 0x60 Executed.", $0D, $00
+>397431		20 45 78 65 63 75 74 65 64 2e 0d 00
+>39743d		43 6d 64 20 30 78 46 46		pass_cmd0xFFmsg .text "Cmd 0xFF (Reset) Done.", $0D, $00
+>397445		20 28 52 65 73 65 74 29 20 44 6f 6e 65 2e 0d 00
+>397455		43 6d 64 20 30 78 45 45		pass_cmd0xEEmsg .text "Cmd 0xEE Echo Test passed...", $0D, $00
+>39745d		20 45 63 68 6f 20 54 65 73 74 20 70 61 73 73 65
+>39746d		64 2e 2e 2e 0d 00
+>397473		4b 65 79 62 6f 61 72 64		Success_kb_init .text "Keyboard Present", $0D, $00
+>39747b		20 50 72 65 73 65 6e 74 0d 00
+>397485		4d 6f 75 73 65 20 50 72		Success_ms_init .text "Mouse Present", $0D, $00
+>39748d		65 73 65 6e 74 0d 00
+>397494		4e 6f 20 4b 65 79 62 6f		Failed_kb_init  .text "No Keyboard Attached or Failed Init...", $0D, $00
+>39749c		61 72 64 20 41 74 74 61 63 68 65 64 20 6f 72 20
+>3974ac		46 61 69 6c 65 64 20 49 6e 69 74 2e 2e 2e 0d 00
+>3974bc		4e 6f 20 4d 6f 75 73 65		Failed_ms_init  .text "No Mouse Attached or Failed Init...", $0D, $00
+>3974c4		20 41 74 74 61 63 68 65 64 20 6f 72 20 46 61 69
+>3974d4		6c 65 64 20 49 6e 69 74 2e 2e 2e 0d 00
+>3974e1		49 20 61 6d 20 73 74 75		IamStuckHeremsg .text "I am stuck here...", $0D, $00
+>3974e9		63 6b 20 68 65 72 65 2e 2e 2e 0d 00
+>3974f5		4e 4f 20 53 49 47 4e 41		bmp_parser_err0 .text "NO SIGNATURE FOUND.", $00
+>3974fd		54 55 52 45 20 46 4f 55 4e 44 2e 00
+>397509		42 4d 50 20 4c 4f 41 44		bmp_parser_msg0 .text "BMP LOADED.", $00
+>397511		45 44 2e 00
+>397515		45 58 45 43 55 54 49 4e		bmp_parser_msg1 .text "EXECUTING BMP PARSER", $00
+>39751d		47 20 42 4d 50 20 50 41 52 53 45 52 00
+>39752a		49 44 45 20 48 44 44 20		IDE_HDD_Present_msg0 .text "IDE HDD Present:", $00
+>397532		50 72 65 73 65 6e 74 3a 00
+>39753b		42 6f 6f 74 20 44 49 50		boot_invalid    .null "Boot DIP switch settings are invalid."
+>397543		20 73 77 69 74 63 68 20 73 65 74 74 69 6e 67 73
+>397553		20 61 72 65 20 69 6e 76 61 6c 69 64 2e 00
+>397561		50 72 65 73 73 20 52 20		boot_retry      .null "Press R to retry, B to go to BASIC.", 13
+>397569		74 6f 20 72 65 74 72 79 2c 20 42 20 74 6f 20 67
+>397579		6f 20 74 6f 20 42 41 53 49 43 2e 0d 00
+>397586		55 6e 61 62 6c 65 20 74		sdc_err_boot    .null "Unable to read the SD card."
+>39758e		6f 20 72 65 61 64 20 74 68 65 20 53 44 20 63 61
+>39759e		72 64 2e 00
+>3975a2		55 6e 61 62 6c 65 20 74		ide_err_boot    .null "Unable to read from the IDE drive."
+>3975aa		6f 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20
+>3975ba		49 44 45 20 64 72 69 76 65 2e 00
+>3975c5		55 6e 61 62 6c 65 20 74		fdc_err_boot    .null "Unable to read from the floppy drive."
+>3975cd		6f 20 72 65 61 64 20 66 72 6f 6d 20 74 68 65 20
+>3975dd		66 6c 6f 70 70 79 20 64 72 69 76 65 2e 00
+>3975eb		42 6f 6f 74 69 6e 67 20		fdc_boot        .null "Booting from floppy..."
+>3975f3		66 72 6f 6d 20 66 6c 6f 70 70 79 2e 2e 2e 00
+>397602		42 6f 6f 74 69 6e 67 20		sdc_boot        .null "Booting from SDCard..."
+>39760a		66 72 6f 6d 20 53 44 43 61 72 64 2e 2e 2e 00
+>397619		42 6f 6f 74 69 6e 67 20		ide_boot        .null "Booting from Hard Drive..."
+>397621		66 72 6f 6d 20 48 61 72 64 20 44 72 69 76 65 2e
+>397631		2e 2e 00
+>397634		0d 52 45 41 44 59 2e 00		ready_msg       .null $0D,"READY."
+>39763c		41 42 4f 52 54 20 45 52		error_01        .null "ABORT ERROR"
+>397644		52 4f 52 00
+>397648		30 31 32 33 34 35 36 37		hex_digits      .text "0123456789ABCDEF",0
+>397650		38 39 41 42 43 44 45 46 00
+>397659						.align 256
+>397700		00 1b 31 32 33 34 35 36		ScanCode_Press_Set1   .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
+>397708		37 38 39 30 2d 3d 08 09
+>397710		71 77 65 72 74 79 75 69		                      .text $71, $77, $65, $72, $74, $79, $75, $69, $6F, $70, $5B, $5D, $0D, $00, $61, $73    ; $10
+>397718		6f 70 5b 5d 0d 00 61 73
+>397720		64 66 67 68 6a 6b 6c 3b		                      .text $64, $66, $67, $68, $6A, $6B, $6C, $3B, $27, $60, $00, $5C, $7A, $78, $63, $76    ; $20
+>397728		27 60 00 5c 7a 78 63 76
+>397730		62 6e 6d 2c 2e 2f 00 2a		                      .text $62, $6E, $6D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $81, $82, $83, $84, $85    ; $30
+>397738		00 20 00 81 82 83 84 85
+>397740		86 87 88 89 8a 00 00 00		                      .text $86, $87, $88, $89, $8A, $00, $00, $00, $11, $00, $00, $9D, $00, $1D, $00, $00    ; $40
+>397748		11 00 00 9d 00 1d 00 00
+>397750		91 00 00 00 00 00 00 8b		                      .text $91, $00, $00, $00, $00, $00, $00, $8B, $8C, $00, $00, $00, $00, $00, $00, $00    ; $50
+>397758		8c 00 00 00 00 00 00 00
+>397760		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
+>397768		00 00 00 00 00 00 00 00
+>397770		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
+>397778		00 00 00 00 00 00 00 00
+>397780		00 00 21 40 23 24 25 5e		ScanCode_Shift_Set1   .text $00, $00, $21, $40, $23, $24, $25, $5E, $26, $2A, $28, $29, $5F, $2B, $08, $09    ; $00
+>397788		26 2a 28 29 5f 2b 08 09
+>397790		51 57 45 52 54 59 55 49		                      .text $51, $57, $45, $52, $54, $59, $55, $49, $4F, $50, $7B, $7D, $0D, $00, $41, $53    ; $10
+>397798		4f 50 7b 7d 0d 00 41 53
+>3977a0		44 46 47 48 4a 4b 4c 3a		                      .text $44, $46, $47, $48, $4A, $4B, $4C, $3A, $22, $7E, $00, $7C, $5A, $58, $43, $56    ; $20
+>3977a8		22 7e 00 7c 5a 58 43 56
+>3977b0		42 4e 4d 3c 3e 3f 00 00		                      .text $42, $4E, $4D, $3C, $3E, $3F, $00, $00, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
+>3977b8		00 20 00 00 00 00 00 00
+>3977c0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
+>3977c8		00 00 00 00 00 00 00 00
+>3977d0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
+>3977d8		00 00 00 00 00 00 00 00
+>3977e0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
+>3977e8		00 00 00 00 00 00 00 00
+>3977f0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
+>3977f8		00 00 00 00 00 00 00 00
+>397800		00 1b 31 32 33 34 35 36		ScanCode_Ctrl_Set1    .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
+>397808		37 38 39 30 2d 3d 08 09
+>397810		11 17 05 12 14 19 15 09		                      .text $11, $17, $05, $12, $14, $19, $15, $09, $0F, $10, $5B, $5D, $0D, $00, $01, $13    ; $10
+>397818		0f 10 5b 5d 0d 00 01 13
+>397820		04 06 07 08 0a 0b 0c 3b		                      .text $04, $06, $07, $08, $0A, $0B, $0C, $3B, $27, $00, $00, $5C, $1A, $18, $03, $16    ; $20
+>397828		27 00 00 5c 1a 18 03 16
+>397830		02 0e 0d 2c 2e 2f 00 2a		                      .text $02, $0E, $0D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
+>397838		00 20 00 00 00 00 00 00
+>397840		00 00 00 00 00 18 00 00		                      .text $00, $00, $00, $00, $00, $18, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
+>397848		00 00 00 00 00 00 00 00
+>397850		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
+>397858		00 00 00 00 00 00 00 00
+>397860		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
+>397868		00 00 00 00 00 00 00 00
+>397870		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
+>397878		00 00 00 00 00 00 00 00
+>397880		00 1b 31 32 33 34 35 36		ScanCode_Alt_Set1     .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
+>397888		37 38 39 30 2d 3d 08 09
+>397890		71 77 65 72 74 79 75 69		                      .text $71, $77, $65, $72, $74, $79, $75, $69, $6F, $70, $5B, $5D, $0D, $00, $61, $73    ; $10
+>397898		6f 70 5b 5d 0d 00 61 73
+>3978a0		64 66 67 68 6a 6b 6c 3b		                      .text $64, $66, $67, $68, $6A, $6B, $6C, $3B, $27, $60, $00, $5C, $7A, $78, $63, $76    ; $20
+>3978a8		27 60 00 5c 7a 78 63 76
+>3978b0		62 6e 6d 2c 2e 2f 00 2a		                      .text $62, $6E, $6D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
+>3978b8		00 20 00 00 00 00 00 00
+>3978c0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
+>3978c8		00 00 00 00 00 00 00 00
+>3978d0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
+>3978d8		00 00 00 00 00 00 00 00
+>3978e0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
+>3978e8		00 00 00 00 00 00 00 00
+>3978f0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
+>3978f8		00 00 00 00 00 00 00 00
+>397900		00 1b 31 32 33 34 35 36		ScanCode_NumLock_Set1 .text $00, $1B, $31, $32, $33, $34, $35, $36, $37, $38, $39, $30, $2D, $3D, $08, $09    ; $00
+>397908		37 38 39 30 2d 3d 08 09
+>397910		71 77 65 72 74 79 75 69		                      .text $71, $77, $65, $72, $74, $79, $75, $69, $6F, $70, $5B, $5D, $0D, $00, $61, $73    ; $10
+>397918		6f 70 5b 5d 0d 00 61 73
+>397920		64 66 67 68 6a 6b 6c 3b		                      .text $64, $66, $67, $68, $6A, $6B, $6C, $3B, $27, $60, $00, $5C, $7A, $78, $63, $76    ; $20
+>397928		27 60 00 5c 7a 78 63 76
+>397930		62 6e 6d 2c 2e 2f 00 2a		                      .text $62, $6E, $6D, $2C, $2E, $2F, $00, $2A, $00, $20, $00, $00, $00, $00, $00, $00    ; $30
+>397938		00 20 00 00 00 00 00 00
+>397940		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $40
+>397948		00 00 00 00 00 00 00 00
+>397950		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
+>397958		00 00 00 00 00 00 00 00
+>397960		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
+>397968		00 00 00 00 00 00 00 00
+>397970		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
+>397978		00 00 00 00 00 00 00 00
+>397980		00 00 00 00 00 00 00 00		ScanCode_Prefix_Set1  .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $00
+>397988		00 00 00 00 00 00 00 00
+>397990		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $10
+>397998		00 00 00 00 00 00 00 00
+>3979a0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $20
+>3979a8		00 00 00 00 00 00 00 00
+>3979b0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $30
+>3979b8		00 00 00 00 00 00 00 00
+>3979c0		00 00 00 00 00 00 00 01		                      .text $00, $00, $00, $00, $00, $00, $00, $01, $11, $00, $00, $9D, $00, $1D, $00, $05    ; $40
+>3979c8		11 00 00 9d 00 1d 00 05
+>3979d0		91 00 0f 7f 00 00 00 00		                      .text $91, $00, $0F, $7F, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $50
+>3979d8		00 00 00 00 00 00 00 00
+>3979e0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $60
+>3979e8		00 00 00 00 00 00 00 00
+>3979f0		00 00 00 00 00 00 00 00		                      .text $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00    ; $70
+>3979f8		00 00 00 00 00 00 00 00
+>397a00						.align 256
+>397a00		00 14 1c 21 26 2a 2e 31		GAMMA_2_2_Tbl         .text  $00, $14, $1c, $21, $26, $2a, $2e, $31, $34, $37, $3a, $3d, $3f, $41, $44, $46
+>397a08		34 37 3a 3d 3f 41 44 46
+>397a10		48 4a 4c 4e 50 51 53 55		                      .text  $48, $4a, $4c, $4e, $50, $51, $53, $55, $57, $58, $5a, $5b, $5d, $5e, $60, $61
+>397a18		57 58 5a 5b 5d 5e 60 61
+>397a20		63 64 66 67 68 6a 6b 6c		                      .text  $63, $64, $66, $67, $68, $6a, $6b, $6c, $6d, $6f, $70, $71, $72, $73, $75, $76
+>397a28		6d 6f 70 71 72 73 75 76
+>397a30		77 78 79 7a 7b 7c 7d 7e		                      .text  $77, $78, $79, $7a, $7b, $7c, $7d, $7e, $80, $81, $82, $83, $84, $85, $86, $87
+>397a38		80 81 82 83 84 85 86 87
+>397a40		88 88 89 8a 8b 8c 8d 8e		                      .text  $88, $88, $89, $8a, $8b, $8c, $8d, $8e, $8f, $90, $91, $92, $93, $93, $94, $95
+>397a48		8f 90 91 92 93 93 94 95
+>397a50		96 97 98 99 99 9a 9b 9c		                      .text  $96, $97, $98, $99, $99, $9a, $9b, $9c, $9d, $9e, $9e, $9f, $a0, $a1, $a2, $a2
+>397a58		9d 9e 9e 9f a0 a1 a2 a2
+>397a60		a3 a4 a5 a5 a6 a7 a8 a8		                      .text  $a3, $a4, $a5, $a5, $a6, $a7, $a8, $a8, $a9, $aa, $ab, $ab, $ac, $ad, $ae, $ae
+>397a68		a9 aa ab ab ac ad ae ae
+>397a70		af b0 b0 b1 b2 b2 b3 b4		                      .text  $AF, $b0, $b0, $b1, $b2, $b2, $b3, $b4, $b5, $b5, $b6, $b7, $b7, $b8, $b9, $b9
+>397a78		b5 b5 b6 b7 b7 b8 b9 b9
+>397a80		ba bb bb bc bd bd be be		                      .text  $ba, $bb, $bb, $bc, $bd, $bd, $be, $be, $bf, $c0, $c0, $c1, $c2, $c2, $c3, $c4
+>397a88		bf c0 c0 c1 c2 c2 c3 c4
+>397a90		c4 c5 c5 c6 c7 c7 c8 c8		                      .text  $c4, $c5, $c5, $c6, $c7, $c7, $c8, $c8, $c9, $ca, $ca, $cb, $cb, $cc, $cd, $cd
+>397a98		c9 ca ca cb cb cc cd cd
+>397aa0		ce ce cf d0 d0 d1 d1 d2		                      .text  $ce, $ce, $cf, $d0, $d0, $d1, $d1, $d2, $d2, $d3, $d4, $d4, $d5, $d5, $d6, $d6
+>397aa8		d2 d3 d4 d4 d5 d5 d6 d6
+>397ab0		d7 d8 d8 d9 d9 da da db		                      .text  $d7, $d8, $d8, $d9, $d9, $da, $da, $db, $db, $dc, $dc, $dd, $de, $de, $df, $df
+>397ab8		db dc dc dd de de df df
+>397ac0		e0 e0 e1 e1 e2 e2 e3 e3		                      .text  $e0, $e0, $e1, $e1, $e2, $e2, $e3, $e3, $e4, $e4, $e5, $e5, $e6, $e6, $e7, $e7
+>397ac8		e4 e4 e5 e5 e6 e6 e7 e7
+>397ad0		e8 e8 e9 e9 ea ea eb eb		                      .text  $e8, $e8, $e9, $e9, $ea, $ea, $eb, $eb, $ec, $ec, $ed, $ed, $ee, $ee, $ef, $ef
+>397ad8		ec ec ed ed ee ee ef ef
+>397ae0		f0 f0 f1 f1 f2 f2 f3 f3		                      .text  $f0, $f0, $f1, $f1, $f2, $f2, $f3, $f3, $f4, $f4, $f5, $f5, $f6, $f6, $f7, $f7
+>397ae8		f4 f4 f5 f5 f6 f6 f7 f7
+>397af0		f8 f8 f9 f9 f9 fa fa fb		                      .text  $f8, $f8, $f9, $f9, $f9, $fa, $fa, $fb, $fb, $fc, $fc, $fd, $fd, $fe, $fe, $ff
+>397af8		fb fc fc fd fd fe fe ff
+>397b00						.align 256
+>397b00		00 0b 11 15 19 1c 1f 22		GAMMA_1_8_Tbl         .text  $00, $0b, $11, $15, $19, $1c, $1f, $22, $25, $27, $2a, $2c, $2e, $30, $32, $34
+>397b08		25 27 2a 2c 2e 30 32 34
+>397b10		36 38 3a 3c 3d 3f 41 43		                      .text  $36, $38, $3a, $3c, $3d, $3f, $41, $43, $44, $46, $47, $49, $4a, $4c, $4d, $4f
+>397b18		44 46 47 49 4a 4c 4d 4f
+>397b20		50 51 53 54 55 57 58 59		                      .text  $50, $51, $53, $54, $55, $57, $58, $59, $5b, $5c, $5d, $5e, $60, $61, $62, $63
+>397b28		5b 5c 5d 5e 60 61 62 63
+>397b30		64 65 67 68 69 6a 6b 6c		                      .text  $64, $65, $67, $68, $69, $6a, $6b, $6c, $6d, $6e, $70, $71, $72, $73, $74, $75
+>397b38		6d 6e 70 71 72 73 74 75
+>397b40		76 77 78 79 7a 7b 7c 7d		                      .text  $76, $77, $78, $79, $7a, $7b, $7c, $7d, $7e, $7f, $80, $81, $82, $83, $84, $84
+>397b48		7e 7f 80 81 82 83 84 84
+>397b50		85 86 87 88 89 8a 8b 8c		                      .text  $85, $86, $87, $88, $89, $8a, $8b, $8c, $8d, $8e, $8e, $8f, $90, $91, $92, $93
+>397b58		8d 8e 8e 8f 90 91 92 93
+>397b60		94 95 95 96 97 98 99 9a		                      .text  $94, $95, $95, $96, $97, $98, $99, $9a, $9a, $9b, $9c, $9d, $9e, $9f, $9f, $a0
+>397b68		9a 9b 9c 9d 9e 9f 9f a0
+>397b70		a1 a2 a3 a3 a4 a5 a6 a6		                      .text  $a1, $a2, $a3, $a3, $a4, $a5, $a6, $a6, $a7, $a8, $a9, $aa, $aa, $ab, $ac, $ad
+>397b78		a7 a8 a9 aa aa ab ac ad
+>397b80		ad ae af b0 b0 b1 b2 b3		                      .text  $ad, $ae, $af, $b0, $b0, $b1, $b2, $b3, $b3, $b4, $b5, $b6, $b6, $b7, $b8, $b8
+>397b88		b3 b4 b5 b6 b6 b7 b8 b8
+>397b90		b9 ba bb bb bc bd bd be		                      .text  $b9, $ba, $bb, $bb, $bc, $bd, $bd, $be, $bf, $bf, $c0, $c1, $c2, $c2, $c3, $c4
+>397b98		bf bf c0 c1 c2 c2 c3 c4
+>397ba0		c4 c5 c6 c6 c7 c8 c8 c9		                      .text  $c4, $c5, $c6, $c6, $c7, $c8, $c8, $c9, $ca, $ca, $cb, $cc, $cc, $cd, $ce, $ce
+>397ba8		ca ca cb cc cc cd ce ce
+>397bb0		cf d0 d0 d1 d2 d2 d3 d4		                      .text  $cf, $d0, $d0, $d1, $d2, $d2, $d3, $d4, $d4, $d5, $d6, $d6, $d7, $d7, $d8, $d9
+>397bb8		d4 d5 d6 d6 d7 d7 d8 d9
+>397bc0		d9 da db db dc dc dd de		                      .text  $d9, $da, $db, $db, $dc, $dc, $dd, $de, $de, $df, $e0, $e0, $e1, $e1, $e2, $e3
+>397bc8		de df e0 e0 e1 e1 e2 e3
+>397bd0		e3 e4 e4 e5 e6 e6 e7 e7		                      .text  $e3, $e4, $e4, $e5, $e6, $e6, $e7, $e7, $e8, $e9, $e9, $ea, $ea, $eb, $ec, $ec
+>397bd8		e8 e9 e9 ea ea eb ec ec
+>397be0		ed ed ee ef ef f0 f0 f1		                      .text  $ed, $ed, $ee, $ef, $ef, $f0, $f0, $f1, $f1, $f2, $f3, $f3, $f4, $f4, $f5, $f5
+>397be8		f1 f2 f3 f3 f4 f4 f5 f5
+>397bf0		f6 f7 f7 f8 f8 f9 f9 fa		                      .text  $f6, $f7, $f7, $f8, $f8, $f9, $f9, $fa, $fb, $fb, $fc, $fc, $fd, $fd, $fe, $ff
+>397bf8		fb fb fc fc fd fd fe ff
+>397c00						.align 256
+>397c00		1d c8 a7 ac 10 d6 52 7c		RANDOM_LUT_Tbl		    .text  $1d, $c8, $a7, $ac, $10, $d6, $52, $7c, $83, $dd, $ce, $39, $cd, $c5, $3b, $15
+>397c08		83 dd ce 39 cd c5 3b 15
+>397c10		22 55 3b 94 e0 33 1f 38						              .text  $22, $55, $3b, $94, $e0, $33, $1f, $38, $87, $12, $31, $65, $89, $27, $88, $42
+>397c18		87 12 31 65 89 27 88 42
+>397c20		b2 32 72 84 b2 b2 31 52						              .text  $b2, $32, $72, $84, $b2, $b2, $31, $52, $94, $ce, $56, $ec, $fe, $da, $58, $c9
+>397c28		94 ce 56 ec fe da 58 c9
+>397c30		c8 5b 53 2a 08 3b 19 c1						              .text  $c8, $5b, $53, $2a, $08, $3b, $19, $c1, $d0, $10, $2c, $b2, $4b, $ea, $32, $61
+>397c38		d0 10 2c b2 4b ea 32 61
+>397c40		da 34 33 8f 2b da 49 89						              .text  $da, $34, $33, $8f, $2b, $da, $49, $89, $a1, $e6, $ca, $2d, $b3, $ce, $b0, $79
+>397c48		a1 e6 ca 2d b3 ce b0 79
+>397c50		44 aa 32 82 91 e9 29 16						              .text  $44, $aa, $32, $82, $91, $e9, $29, $16, $5f, $e3, $fb, $bd, $15, $2e, $be, $f5
+>397c58		5f e3 fb bd 15 2e be f5
+>397c60		e9 4a e4 2e 60 24 94 35						              .text  $e9, $4a, $e4, $2e, $60, $24, $94, $35, $8d, $8f, $2c, $80, $0a, $5e, $99, $36
+>397c68		8d 8f 2c 80 0a 5e 99 36
+>397c70		ac ab 21 26 42 7c 5e bc						              .text  $ac, $ab, $21, $26, $42, $7c, $5e, $bc, $13, $52, $44, $2f, $e3, $ef, $44, $a2
+>397c78		13 52 44 2f e3 ef 44 a2
+>397c80		86 c1 9c 47 5f 36 6d 02						              .text  $86, $c1, $9c, $47, $5f, $36, $6d, $02, $be, $23, $02, $58, $0a, $52, $5e, $b4
+>397c88		be 23 02 58 0a 52 5e b4
+>397c90		9f 06 08 c9 97 cb 9e dd						              .text  $9f, $06, $08, $c9, $97, $cb, $9e, $dd, $d5, $cf, $3e, $df, $c4, $9e, $da, $bb
+>397c98		d5 cf 3e df c4 9e da bb
+>397ca0		9b 5d c9 f5 d9 c3 7e 87						              .text  $9b, $5d, $c9, $f5, $d9, $c3, $7e, $87, $77, $7d, $b1, $3b, $4a, $68, $35, $6e
+>397ca8		77 7d b1 3b 4a 68 35 6e
+>397cb0		ee 47 ad 8f fd 73 2e 46						              .text  $ee, $47, $ad, $8f, $fd, $73, $2e, $46, $b5, $8f, $44, $63, $55, $6f, $e1, $50
+>397cb8		b5 8f 44 63 55 6f e1 50
+>397cc0		f4 b6 a3 4f 68 c4 a5 a4						              .text  $f4, $b6, $a3, $4f, $68, $c4, $a5, $a4, $57, $74, $b9, $bd, $05, $14, $50, $eb
+>397cc8		57 74 b9 bd 05 14 50 eb
+>397cd0		a5 5c 57 2f 99 dc 2e 8a						              .text  $a5, $5c, $57, $2f, $99, $dc, $2e, $8a, $44, $bc, $ec, $db, $22, $58, $fc, $be
+>397cd8		44 bc ec db 22 58 fc be
+>397ce0		5f 3f 50 bd 2a 36 ab ae						              .text  $5f, $3f, $50, $bd, $2a, $36, $ab, $ae, $24, $aa, $82, $11, $5c, $9f, $43, $4d
+>397ce8		24 aa 82 11 5c 9f 43 4d
+>397cf0		8f 0c 20 00 91 b6 45 9e						              .text  $8f, $0c, $20, $00, $91, $b6, $45, $9e, $3e, $3d, $66, $7e, $0a, $1c, $6b, $74
+>397cf8		3e 3d 66 7e 0a 1c 6b 74
+>397d00						.align 16
+>397d00		00 01 01 00 00 00 00 00		MOUSE_POINTER_PTR     .text $00,$01,$01,$00,$00,$00,$00,$00,$01,$01,$01,$00,$00,$00,$00,$00
+>397d08		01 01 01 00 00 00 00 00
+>397d10		01 ff ff 01 00 00 01 01		                      .text $01,$FF,$FF,$01,$00,$00,$01,$01,$FF,$FF,$FF,$01,$00,$00,$00,$00
+>397d18		ff ff ff 01 00 00 00 00
+>397d20		01 ff ff ff 01 01 55 ff		                      .text $01,$FF,$FF,$FF,$01,$01,$55,$FF,$01,$55,$FF,$FF,$01,$00,$00,$00
+>397d28		01 55 ff ff 01 00 00 00
+>397d30		01 55 ff ff ff ff 01 55		                      .text $01,$55,$FF,$FF,$FF,$FF,$01,$55,$FF,$FF,$FF,$FF,$01,$00,$00,$00
+>397d38		ff ff ff ff 01 00 00 00
+>397d40		00 01 55 ff ff ff ff ff		                      .text $00,$01,$55,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$01,$FF,$FF,$01,$00,$00
+>397d48		ff ff 01 ff ff 01 00 00
+>397d50		00 00 01 55 ff ff ff ff		                      .text $00,$00,$01,$55,$FF,$FF,$FF,$FF,$01,$FF,$FF,$01,$FF,$01,$00,$00
+>397d58		01 ff ff 01 ff 01 00 00
+>397d60		00 00 01 01 55 ff ff ff		                      .text $00,$00,$01,$01,$55,$FF,$FF,$FF,$FF,$01,$FF,$FF,$FF,$01,$00,$00
+>397d68		ff 01 ff ff ff 01 00 00
+>397d70		00 00 01 55 01 55 ff ff		                      .text $00,$00,$01,$55,$01,$55,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$01,$01,$00
+>397d78		ff ff ff ff ff 01 01 00
+>397d80		00 00 01 55 55 55 ff ff		                      .text $00,$00,$01,$55,$55,$55,$FF,$FF,$FF,$FF,$FF,$FF,$01,$FF,$FF,$01
+>397d88		ff ff ff ff 01 ff ff 01
+>397d90		00 00 00 01 55 55 55 ff		                      .text $00,$00,$00,$01,$55,$55,$55,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$FF,$01
+>397d98		ff ff ff ff ff ff ff 01
+>397da0		00 00 00 00 01 55 55 55		                      .text $00,$00,$00,$00,$01,$55,$55,$55,$55,$55,$01,$FF,$FF,$55,$01,$00
+>397da8		55 55 01 ff ff 55 01 00
+>397db0		00 00 00 00 00 01 01 01		                      .text $00,$00,$00,$00,$00,$01,$01,$01,$01,$01,$55,$FF,$55,$01,$00,$00
+>397db8		01 01 55 ff 55 01 00 00
+>397dc0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$01,$55,$55,$55,$01,$00,$00,$00
+>397dc8		01 55 55 55 01 00 00 00
+>397dd0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$01,$55,$55,$01,$00,$00,$00,$00
+>397dd8		01 55 55 01 00 00 00 00
+>397de0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$00,$01,$01,$00,$00,$00,$00,$00
+>397de8		00 01 01 00 00 00 00 00
+>397df0		00 00 00 00 00 00 00 00		                      .text $00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00,$00
+>397df8		00 00 00 00 00 00 00 00
+>3a0000		5c f9 7a 3a 5c d2 60 3a		        .binary "binaries/basic816_3A0000.bin"
+>3a0008		5c cb 24 3a 5c c0 01 3a 5c d8 00 3a 5c 56 01 3a
+>3a0018		5c 57 03 3a 5c 64 01 3a 5c 7f 01 3a 5c 86 01 3a
+>3a0028		da 08 c2 10 a2 00 00 e2 20 20 59 00 90 11 f0 0f
+>3a0038		c9 0d f0 0b c9 0a f0 07 9f 00 4f 00 e8 80 ea a9
+>3a0048		00 9f 00 4f 00 28 fa 60 c2 10 ae b0 08 ec ae 08
+>3a0058		60 5a 08 08 c2 20 48 a9 00 08 5b 68 28 e2 20 c2
+>3a0068		10 a4 b0 c4 ae 10 0d b7 ab c2 20 29 ff 00 e6 b0
+>3a0078		28 7a 38 60 28 7a 18 60 0b 08 08 c2 20 48 a9 00
+>3a0088		08 5b 68 28 e2 20 85 b3 c2 20 a5 a4 d0 06 e2 20
+>3a0098		a5 a6 f0 11 c2 10 a4 a9 c4 a7 f0 09 e2 20 a5 b3
+>3a00a8		97 a4 c8 84 a9 28 2b 60 08 e2 20 a9 00 20 80 00
+>3a00b8		a5 b2 29 df 85 b2 28 60 08 c2 30 48 da e2 20 bd
+>3a00c8		00 00 f0 06 20 80 00 e8 80 f5 c2 30 fa 68 28 60
+>3a00d8		08 c2 10 e2 20 a9 01 20 1c 00 a2 00 00 a9 00 9f
+>3a00e8		00 4c 00 e8 e0 00 01 d0 f6 a2 00 00 20 14 00 c9
+>3a00f8		0d d0 03 4c 4f 01 c9 9d d0 08 e0 00 00 f0 ed ca
+>3a0108		80 39 c9 1d d0 0e bf 00 4c 00 f0 e0 e0 4f 00 f0
+>3a0118		db e8 80 27 c9 08 d0 1a e0 00 00 f0 cf da bf 01
+>3a0128		4c 00 9f 00 4c 00 f0 06 e8 e0 ff 00 d0 f0 fa ca
+>3a0138		80 0e c9 20 90 b6 9f 00 4c 00 e8 20 18 00 80 ac
+>3a0148		a9 08 20 18 00 80 a5 a9 00 20 1c 00 28 60 22 4c
+>3a0158		10 00 60 20 14 00 48 20 18 00 68 60 08 e2 20 c9
+>3a0168		00 f0 08 af 10 00 af 09 01 80 06 af 10 00 af 29
+>3a0178		fe 8f 10 00 af 28 60 08 22 84 10 00 28 60 48 da
+>3a0188		5a 0b 08 e2 20 c2 10 a2 00 00 a9 20 9f 00 a0 af
+>3a0198		af 1e 00 00 9f 00 c0 af e8 e0 00 20 d0 ec 08 c2
+>3a01a8		20 48 a9 00 00 5b 68 28 a2 00 00 a0 00 00 22 84
+>3a01b8		10 00 28 2b 7a fa 68 60 da 5a 0b 08 08 c2 20 48
+>3a01c8		a9 00 08 5b 68 28 c2 30 af 0c 00 00 85 08 e2 20
+>3a01d8		af 0e 00 00 c2 20 29 ff 00 85 0a af 11 00 00 8f
+>3a01e8		08 01 00 af 1c 00 00 3a 8f 0a 01 00 18 a5 08 6f
+>3a01f8		0c 01 00 85 08 a5 0a 69 00 00 85 0a e2 20 af 0f
+>3a0208		00 00 85 8d a0 00 00 a2 00 00 b7 08 9f 00 4f 00
+>3a0218		e8 c8 c4 8d d0 f4 ca bf 00 4f 00 c9 20 d0 09 a9
+>3a0228		00 9f 00 4f 00 ca 10 ef 28 2b 7a fa 60 e2 20 a9
+>3a0238		48 8f 0f 00 00 a9 34 8f 13 00 00 a9 20 8f 08 00
+>3a0248		af 8f 09 00 af a2 00 00 a9 00 9f 18 f0 3a e8 e0
+>3a0258		40 00 d0 f6 a9 80 8f b2 08 00 e2 20 a9 00 8f 89
+>3a0268		0f 00 a9 00 8f 00 02 af 8f 0c 02 af 8f 18 02 af
+>3a0278		8f 24 02 af 60 08 e2 20 af 0e 08 af 09 08 8f 0e
+>3a0288		08 af af 00 08 af 8d 21 08 af 02 08 af 8d 22 08
+>3a0298		af 04 08 af 8d 23 08 9c 24 08 af 0e 08 af 29 f7
+>3a02a8		8f 0e 08 af a9 00 8d 25 08 28 60 08 e2 20 af 0e
+>3a02b8		08 af 09 08 8f 0e 08 af af 0a 08 af 8d 21 08 af
+>3a02c8		09 08 af 8d 22 08 af 06 08 af 8d 23 08 9c 24 08
+>3a02d8		af 0e 08 af 29 f7 8f 0e 08 af a9 00 8d 25 08 28
+>3a02e8		60 08 e2 20 48 48 a9 00 22 3c 10 00 68 22 18 10
+>3a02f8		00 af 89 0f 00 29 01 d0 f8 68 28 60 08 e2 20 48
+>3a0308		48 a9 01 22 3c 10 00 68 22 18 10 00 af 89 0f 00
+>3a0318		29 01 d0 f8 68 28 60 08 c2 20 48 e2 20 a9 0d 20
+>3a0328		18 00 c2 20 68 28 60 08 22 78 10 00 28 60 08 0b
+>3a0338		08 c2 20 48 a9 00 08 5b 68 28 e2 20 a5 b4 1a 85
+>3a0348		b4 cf 13 00 00 90 05 20 14 00 64 b4 2b 28 60 da
+>3a0358		5a 0b 08 08 c2 20 48 a9 00 08 5b 68 28 e2 20 c2
+>3a0368		10 8f b3 08 00 af b2 08 00 29 20 f0 07 af b3 08
+>3a0378		00 20 80 00 af b2 08 00 29 80 f0 07 af b3 08 00
+>3a0388		20 e9 02 af b2 08 00 29 40 f0 14 af b3 08 00 20
+>3a0398		04 03 af b3 08 00 c9 0d d0 05 a9 0a 20 04 03 28
+>3a03a8		2b 7a fa 60 08 e2 20 bd 00 00 f0 06 20 18 00 e8
+>3a03b8		80 f5 28 60 08 c2 20 48 48 4a 4a 4a 4a 4a 4a 4a
+>3a03c8		4a 20 d6 03 68 29 ff 00 20 d6 03 68 28 60 08 c2
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+>3b0000						.align 256
+.3b0000						CREDITS_TEXT
+>3b0000		20 20 20 20 20 20 20 20		                .text "                              CREDITS                                  "
+>3b0008		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0018		20 20 20 20 20 20 43 52 45 44 49 54 53 20 20 20
+>3b0028		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0038		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0047		20 20 20 20 20 20 20 20		                .fill 80 - len("                              CREDITS                                  "), $20
+>3b004f		20
+>3b0050		20 20 20 20 20 20 20 20		                .text "                       The C256 Foenix Project                         "
+>3b0058		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 54
+>3b0068		68 65 20 43 32 35 36 20 46 6f 65 6e 69 78 20 50
+>3b0078		72 6f 6a 65 63 74 20 20 20 20 20 20 20 20 20 20
+>3b0088		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0097		20 20 20 20 20 20 20 20		                .fill 80 - len("                       The C256 Foenix Project                         "), $20
+>3b009f		20
+>3b00a0		20 20 20 20 20 20 20 20		                .text "                                                                       "
+>3b00a8		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b00d8		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b00e7		20 20 20 20 20 20 20 20		                .fill 80 - len("                                                                       "), $20
+>3b00ef		20
+>3b00f0		20 20 20 20 20 20 20 20		                .text "                                                                       "
+>3b00f8		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b0128		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0137		20 20 20 20 20 20 20 20		                .fill 80 - len("                                                                       "), $20
+>3b013f		20
+>3b0140		50 72 6f 6a 65 63 74 20		                .text "Project Creator & Hardware Design: Stefany Allaire"
+>3b0148		43 72 65 61 74 6f 72 20 26 20 48 61 72 64 77 61
+>3b0158		72 65 20 44 65 73 69 67 6e 3a 20 53 74 65 66 61
+>3b0168		6e 79 20 41 6c 6c 61 69 72 65
+>3b0172		20 20 20 20 20 20 20 20		                .fill 80 - len("Project Creator & Hardware Design: Stefany Allaire"), $20
+>3b017a		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b018a		20 20 20 20 20 20
+>3b0190		77 77 77 2e 63 32 35 36		                .text "www.c256foenix.com"
+>3b0198		66 6f 65 6e 69 78 2e 63 6f 6d
+>3b01a2		20 20 20 20 20 20 20 20		                .fill 80 - len("www.c256foenix.com"), $20
+>3b01aa		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b01da		20 20 20 20 20 20
+>3b01e0		20				                .text " "
+>3b01e1		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b01e9		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b0229		20 20 20 20 20 20 20
+>3b0230		20				                .text " "
+>3b0231		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b0239		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b0279		20 20 20 20 20 20 20
+>3b0280		45 41 52 4c 59 20 41 4c		                .text "EARLY ALPHA & KEY PLAYERS:"
+>3b0288		50 48 41 20 26 20 4b 45 59 20 50 4c 41 59 45 52
+>3b0298		53 3a
+>3b029a		20 20 20 20 20 20 20 20		                .fill 80 - len("EARLY ALPHA & KEY PLAYERS:"), $20
+>3b02a2		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b02b2		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b02c2		20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b02d0		20 20 46 6f 65 6e 69 78		                .text "  Foenix IDE Design : Daniel Tremblay"
+>3b02d8		20 49 44 45 20 44 65 73 69 67 6e 20 3a 20 44 61
+>3b02e8		6e 69 65 6c 20 54 72 65 6d 62 6c 61 79
+>3b02f5		20 20 20 20 20 20 20 20		                .fill 80 - len("  Foenix IDE Design : Daniel Tremblay"), $20
+>3b02fd		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b030d		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b031d		20 20 20
+>3b0320		20 20 4b 65 72 6e 65 6c		                .text "  Kernel Design, BASIC816 Creator: Peter J. Weingartner "
+>3b0328		20 44 65 73 69 67 6e 2c 20 42 41 53 49 43 38 31
+>3b0338		36 20 43 72 65 61 74 6f 72 3a 20 50 65 74 65 72
+>3b0348		20 4a 2e 20 57 65 69 6e 67 61 72 74 6e 65 72 20
+>3b0358		20 20 20 20 20 20 20 20		                .fill 80 - len("  Kernel Design, BASIC816 Creator: Peter J. Weingartner "), $20
+>3b0360		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0370		20 20 46 58 2f 4f 53 20		                .text "  FX/OS (GUI Environment) Design: Mike Bush"
+>3b0378		28 47 55 49 20 45 6e 76 69 72 6f 6e 6d 65 6e 74
+>3b0388		29 20 44 65 73 69 67 6e 3a 20 4d 69 6b 65 20 42
+>3b0398		75 73 68
+>3b039b		20 20 20 20 20 20 20 20		                .fill 80 - len("  FX/OS (GUI Environment) Design: Mike Bush"), $20
+>3b03a3		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b03b3		20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b03c0		53 70 65 63 69 61 6c 20		                .text "Special Thanks:"
+>3b03c8		54 68 61 6e 6b 73 3a
+>3b03cf		20 20 20 20 20 20 20 20		                .fill 80 - len("Special Thanks:"), $20
+>3b03d7		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b0407		20 20 20 20 20 20 20 20 20
+>3b0410		20 20 45 61 72 6c 79 20		                .text "  Early Creator for the Foenix IDE & Kernel: Tom Wilson"
+>3b0418		43 72 65 61 74 6f 72 20 66 6f 72 20 74 68 65 20
+>3b0428		46 6f 65 6e 69 78 20 49 44 45 20 26 20 4b 65 72
+>3b0438		6e 65 6c 3a 20 54 6f 6d 20 57 69 6c 73 6f 6e
+>3b0447		20 20 20 20 20 20 20 20		                .fill 80 - len("  Early Creator for the Foenix IDE & Kernel: Tom Wilson"), $20
+>3b044f		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b045f		20
+>3b0460		20				                .text " "
+>3b0461		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b0469		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b04a9		20 20 20 20 20 20 20
+>3b04b0		20				                .text " "
+>3b04b1		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b04b9		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b04f9		20 20 20 20 20 20 20
+>3b0500		46 50 47 41 20 43 4f 52		                .text "FPGA CORES AUTHORS:"
+>3b0508		45 53 20 41 55 54 48 4f 52 53 3a
+>3b0513		20 20 20 20 20 20 20 20		                .fill 80 - len("FPGA CORES AUTHORS:"), $20
+>3b051b		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b054b		20 20 20 20 20
+>3b0550		20 20 4c 50 43 20 43 6f		                .text "  LPC Core: Howard M. Harte, hharte@opencores.org"
+>3b0558		72 65 3a 20 48 6f 77 61 72 64 20 4d 2e 20 48 61
+>3b0568		72 74 65 2c 20 68 68 61 72 74 65 40 6f 70 65 6e
+>3b0578		63 6f 72 65 73 2e 6f 72 67
+>3b0581		20 20 20 20 20 20 20 20		                .fill 80 - len("  LPC Core: Howard M. Harte, hharte@opencores.org"), $20
+>3b0589		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0599		20 20 20 20 20 20 20
+>3b05a0		20 20 53 44 43 61 72 64		                .text "  SDCard Core: Steve Fielding, sfielding@base2designs.com"
+>3b05a8		20 43 6f 72 65 3a 20 53 74 65 76 65 20 46 69 65
+>3b05b8		6c 64 69 6e 67 2c 20 73 66 69 65 6c 64 69 6e 67
+>3b05c8		40 62 61 73 65 32 64 65 73 69 67 6e 73 2e 63 6f
+>3b05d8		6d
+>3b05d9		20 20 20 20 20 20 20 20		                .fill 80 - len("  SDCard Core: Steve Fielding, sfielding@base2designs.com"), $20
+>3b05e1		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b05f0		20 20 50 53 32 20 43 6f		                .text "  PS2 Controller (C256 Foenix U): Miha Dolenc, mihad@opencores.org "
+>3b05f8		6e 74 72 6f 6c 6c 65 72 20 28 43 32 35 36 20 46
+>3b0608		6f 65 6e 69 78 20 55 29 3a 20 4d 69 68 61 20 44
+>3b0618		6f 6c 65 6e 63 2c 20 6d 69 68 61 64 40 6f 70 65
+>3b0628		6e 63 6f 72 65 73 2e 6f 72 67 20
+>3b0633		20 20 20 20 20 20 20 20		                .fill 80 - len("  PS2 Controller (C256 Foenix U): Miha Dolenc, mihad@opencores.org "), $20
+>3b063b		20 20 20 20 20
+>3b0640		20 20 53 4e 37 36 34 38		                .text "  SN76489 (JT89) (C256 Foenix U): Jose Tejada Gomez"
+>3b0648		39 20 28 4a 54 38 39 29 20 28 43 32 35 36 20 46
+>3b0658		6f 65 6e 69 78 20 55 29 3a 20 4a 6f 73 65 20 54
+>3b0668		65 6a 61 64 61 20 47 6f 6d 65 7a
+>3b0673		20 20 20 20 20 20 20 20		                .fill 80 - len("  SN76489 (JT89) (C256 Foenix U): Jose Tejada Gomez"), $20
+>3b067b		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b068b		20 20 20 20 20
+>3b0690		20 20 59 4d 32 36 31 32		                .text "  YM2612 (JT12): Jose Tejada Gomez"
+>3b0698		20 28 4a 54 31 32 29 3a 20 4a 6f 73 65 20 54 65
+>3b06a8		6a 61 64 61 20 47 6f 6d 65 7a
+>3b06b2		20 20 20 20 20 20 20 20		                .fill 80 - len("  YM2612 (JT12): Jose Tejada Gomez"), $20
+>3b06ba		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b06ca		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b06da		20 20 20 20 20 20
+>3b06e0		20 20 59 4d 32 31 35 31		                .text "  YM2151 (JT51) (C256 Foenix U): Jose Tejada Gomez"
+>3b06e8		20 28 4a 54 35 31 29 20 28 43 32 35 36 20 46 6f
+>3b06f8		65 6e 69 78 20 55 29 3a 20 4a 6f 73 65 20 54 65
+>3b0708		6a 61 64 61 20 47 6f 6d 65 7a
+>3b0712		20 20 20 20 20 20 20 20		                .fill 80 - len("  YM2151 (JT51) (C256 Foenix U): Jose Tejada Gomez"), $20
+>3b071a		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b072a		20 20 20 20 20 20
+>3b0730		20 20 53 49 44 20 28 36		                .text "  SID (6581): Gideon Zweijtzer, gideon.zweijtzer@gmail.com"
+>3b0738		35 38 31 29 3a 20 47 69 64 65 6f 6e 20 5a 77 65
+>3b0748		69 6a 74 7a 65 72 2c 20 67 69 64 65 6f 6e 2e 7a
+>3b0758		77 65 69 6a 74 7a 65 72 40 67 6d 61 69 6c 2e 63
+>3b0768		6f 6d
+>3b076a		20 20 20 20 20 20 20 20		                .fill 80 - len("  SID (6581): Gideon Zweijtzer, gideon.zweijtzer@gmail.com"), $20
+>3b0772		20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0780		20 20 55 41 52 54 20 28		                .text "  UART (16550) (C256 Foenix U): TBD"
+>3b0788		31 36 35 35 30 29 20 28 43 32 35 36 20 46 6f 65
+>3b0798		6e 69 78 20 55 29 3a 20 54 42 44
+>3b07a3		20 20 20 20 20 20 20 20		                .fill 80 - len("  UART (16550) (C256 Foenix U): TBD"), $20
+>3b07ab		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b07bb		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b07cb		20 20 20 20 20
+>3b07d0		20				                .text " "
+>3b07d1		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b07d9		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b0819		20 20 20 20 20 20 20
+>3b0820		20				                .text " "
+>3b0821		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b0829		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b0869		20 20 20 20 20 20 20
+>3b0870		53 50 45 43 49 41 4c 20		                .text "SPECIAL THANKS:"
+>3b0878		54 48 41 4e 4b 53 3a
+>3b087f		20 20 20 20 20 20 20 20		                .fill 80 - len("SPECIAL THANKS:"), $20
+>3b0887		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b08b7		20 20 20 20 20 20 20 20 20
+>3b08c0		20 20 4a 6f 65 72 69 20		                .text "  Joeri Vanharen"
+>3b08c8		56 61 6e 68 61 72 65 6e
+>3b08d0		20 20 20 20 20 20 20 20		                .fill 80 - len("  Joeri Vanharen"), $20
+>3b08d8		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b0908		20 20 20 20 20 20 20 20
+>3b0910		20 20 4a 69 6d 20 44 72		                .text "  Jim Drew"
+>3b0918		65 77
+>3b091a		20 20 20 20 20 20 20 20		                .fill 80 - len("  Jim Drew"), $20
+>3b0922		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b0952		20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0960		20 20 41 69 64 61 6e 20		                .text "  Aidan Lawrence (Sound Chip Schematic references)"
+>3b0968		4c 61 77 72 65 6e 63 65 20 28 53 6f 75 6e 64 20
+>3b0978		43 68 69 70 20 53 63 68 65 6d 61 74 69 63 20 72
+>3b0988		65 66 65 72 65 6e 63 65 73 29
+>3b0992		20 20 20 20 20 20 20 20		                .fill 80 - len("  Aidan Lawrence (Sound Chip Schematic references)"), $20
+>3b099a		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b09aa		20 20 20 20 20 20
+>3b09b0		20				                .text " "
+>3b09b1		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b09b9		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b09f9		20 20 20 20 20 20 20
+>3b0a00		20				                .text " "
+>3b0a01		20 20 20 20 20 20 20 20		                .fill 80 - len(" "), $20
+>3b0a09		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 3 times (48 bytes)...
+>3b0a49		20 20 20 20 20 20 20
+>3b0a50		20 20 20 20 20 20 20 20		                .text "                                                                       "
+>3b0a58		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b0a88		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0a97		20 20 20 20 20 20 20 20		                .fill 80 - len("                                                                       "), $20
+>3b0a9f		20
+>3b0aa0		20 20 20 20 20 20 20 20		                .text "                     I would like to say a big thanks               "
+>3b0aa8		20 20 20 20 20 20 20 20 20 20 20 20 20 49 20 77
+>3b0ab8		6f 75 6c 64 20 6c 69 6b 65 20 74 6f 20 73 61 79
+>3b0ac8		20 61 20 62 69 67 20 74 68 61 6e 6b 73 20 20 20
+>3b0ad8		20 20 20 20 20 20 20 20 20 20 20 20
+>3b0ae4		20 20 20 20 20 20 20 20		                .fill 80 - len("                     I would like to say a big thanks               "), $20
+>3b0aec		20 20 20 20
+>3b0af0		20 20 20 20 20 20 20 20		                .text "                  from the bottom of my heart for all of            "
+>3b0af8		20 20 20 20 20 20 20 20 20 20 66 72 6f 6d 20 74
+>3b0b08		68 65 20 62 6f 74 74 6f 6d 20 6f 66 20 6d 79 20
+>3b0b18		68 65 61 72 74 20 66 6f 72 20 61 6c 6c 20 6f 66
+>3b0b28		20 20 20 20 20 20 20 20 20 20 20 20
+>3b0b34		20 20 20 20 20 20 20 20		                .fill 80 - len("                  from the bottom of my heart for all of            "), $20
+>3b0b3c		20 20 20 20
+>3b0b40		20 20 20 20 20 20 20 20		                .text "              those who have believed in this project since          "
+>3b0b48		20 20 20 20 20 20 74 68 6f 73 65 20 77 68 6f 20
+>3b0b58		68 61 76 65 20 62 65 6c 69 65 76 65 64 20 69 6e
+>3b0b68		20 74 68 69 73 20 70 72 6f 6a 65 63 74 20 73 69
+>3b0b78		6e 63 65 20 20 20 20 20 20 20 20 20 20
+>3b0b85		20 20 20 20 20 20 20 20		                .fill 80 - len("              those who have believed in this project since          "), $20
+>3b0b8d		20 20 20
+>3b0b90		20 20 20 20 20 20 20 20		                .text "                the very beginning and have been there to            "
+>3b0b98		20 20 20 20 20 20 20 20 74 68 65 20 76 65 72 79
+>3b0ba8		20 62 65 67 69 6e 6e 69 6e 67 20 61 6e 64 20 68
+>3b0bb8		61 76 65 20 62 65 65 6e 20 74 68 65 72 65 20 74
+>3b0bc8		6f 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0bd5		20 20 20 20 20 20 20 20		                .fill 80 - len("                the very beginning and have been there to            "), $20
+>3b0bdd		20 20 20
+>3b0be0		20 20 20 20 20 20 20 20		                .text "                        make it what it is today!!!                  "
+>3b0be8		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0bf8		6d 61 6b 65 20 69 74 20 77 68 61 74 20 69 74 20
+>3b0c08		69 73 20 74 6f 64 61 79 21 21 21 20 20 20 20 20
+>3b0c18		20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0c25		20 20 20 20 20 20 20 20		                .fill 80 - len("                        make it what it is today!!!                  "), $20
+>3b0c2d		20 20 20
+>3b0c30		20 20 20 20 20 20 20 20		                .text "                                                                       "
+>3b0c38		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 2 times (32 bytes)...
+>3b0c68		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0c77		20 20 20 20 20 20 20 20		                .fill 80 - len("                                                                       "), $20
+>3b0c7f		20
+>3b0c80		20 20 20 20 20 20 20 20		                .text "                        Stefany"
+>3b0c88		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0c98		53 74 65 66 61 6e 79
+>3b0c9f		20 20 20 20 20 20 20 20		                .fill 80 - len("                        Stefany"), $20
+>3b0ca7		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0cb7		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+>3b0cc7		20 20 20 20 20 20 20 20 20
+>3b0cd0		20 20 20 20 20 20 20 20		                .fill 80 * (60 - 26),$20
+>3b0cd8		20 20 20 20 20 20 20 20 20 20 20 20 20 20 20 20
+;		...repeated 168 times (2688 bytes)...
+>3b1768		20 20 20 20 20 20 20 20
+>3b1770						.align 256
+>3b1800		f3 f3 f3 f3 f3 f3 f3 f3		CREDITS_COLOR   .fill 80 * 60, $F3
+>3b1808		f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3 f3
+;		...repeated 298 times (4768 bytes)...
+>3b2ab8		f3 f3 f3 f3 f3 f3 f3 f3
+=$000068					INTERRUPT_STATE  = $000068
+=$000069					INTERRUPT_COUNT  = $000069
+=$00006a					IRQ_COLOR_CHOICE = $00006A
+.3e0000						BOOT_MENU
+.3e0000						SplashScreenMain:
+.3e0000		48		pha		                PHA             ; begin setdp macro
+.3e0001		08		php		                PHP
+.3e0002		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0004		a9 00 00	lda #$0000	                LDA #0         ; set DP to page 0
+.3e0007		5b		tcd		                TCD
+.3e0008		28		plp		                PLP
+.3e0009		68		pla		                PLA             ; end setdp macro
+.3e000a		c2 10		rep #$10	                REP #$10        ; set X long
+.3e000c		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e000e		a9 00		lda #$00	                LDA #$00
+.3e0010		85 68		sta $68		                STA INTERRUPT_STATE
+.3e0012		85 69		sta $69		                STA INTERRUPT_COUNT
+.3e0014		85 6a		sta $6a		                STA IRQ_COLOR_CHOICE
+.3e0016		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0  ; Read the Pending Register &
+.3e001a		29 04		and #$04	                AND #FNX0_INT02_TMR0
+.3e001c		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0  ; Writing it back will clear the Active Bit
+.3e0020		20 e6 00	jsr $3e00e6	                JSR Splash_Get_Machine_ID
+.3e0023		20 19 01	jsr $3e0119	                JSR Splash_Clear_Screen
+.3e0026		20 03 01	jsr $3e0103	                JSR Splash_Load_FontSet
+.3e0029		22 f8 02 3e	jsl $3e02f8	                JSL Splashscreen_BitMapSetup
+.3e002d		20 0b 06	jsr $3e060b	                JSR Model_Update_Info_Field
+.3e0030		20 ec 05	jsr $3e05ec	                JSR Set_Text_Color
+.3e0033		a9 00		lda #$00	                LDA #$00
+.3e0035		85 a6		sta $a6		                STA LINE_INDEX  ; Point to the first line to be displayed
+.3e0037		85 a7		sta $a7		                STA LINE_INDEX + 1
+.3e0039		20 37 08	jsr $3e0837	                JSR Line_Setup_Before_Display   ; Assign and Compute the Pointer
+.3e003c						HAVE_FUN:
+.3e003c		22 33 01 3e	jsl $3e0133	                JSL Splash_Moniker_Color_Rolling  ; Go Move The Colors on the Logo
+.3e0040		a6 a6		ldx $a6		                LDX LINE_INDEX
+.3e0042		e0 17 00	cpx #$0017	                CPX #NumberOfEntry
+.3e0045		f0 08		beq $3e004f	                BEQ ByPassCharDisplay           ; If Equal all Lines have been displayed
+.3e0047		20 74 08	jsr $3e0874	                JSR Line_Display_1_Character    ; Go move the cursor one stop
+.3e004a		90 21		bcc $3e006d	                BCC Still_Displaying_Char
+.3e004c		20 37 08	jsr $3e0837	                JSR Line_Setup_Before_Display   ; Assign and Compute the Pointer
+.3e004f						ByPassCharDisplay:
+.3e004f		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0051		22 48 10 00	jsl $001048	                JSL GETCH               ; Try to get a character
+.3e0055		c9 00		cmp #$00	                CMP #0                  ; Did we get anything
+.3e0057		f0 14		beq $3e006d	                BEQ Still_Displaying_Char            ; No: keep waiting until timeout
+.3e0059		c9 81		cmp #$81	                CMP #CHAR_F1            ; Did the user press F1?
+.3e005b		f0 1f		beq $3e007c	                BEQ return              ; Yes: return it
+.3e005d		c9 82		cmp #$82	                CMP #CHAR_F2            ; Did the user press F2?
+.3e005f		f0 1b		beq $3e007c	                BEQ return              ; Yes: return it
+.3e0061		c9 83		cmp #$83	                CMP #CHAR_F3            ; Did the user press F3?
+.3e0063		f0 17		beq $3e007c	                BEQ return              ; Yes: return it
+.3e0065		c9 0d		cmp #$0d	                CMP #CHAR_CR            ; Did the user press CR?
+.3e0067		f0 13		beq $3e007c	                BEQ return              ; Yes: return it
+.3e0069		c9 20		cmp #$20	                CMP #CHAR_SP            ; Did the user press SPACE?
+.3e006b		f0 0d		beq $3e007a	                BEQ exitshere
+.3e006d						Still_Displaying_Char:
+.3e006d						WaitForNextSOF:
+.3e006d		af 40 01 00	lda $000140	                LDA @l INT_PENDING_REG0
+.3e0071		29 01		and #$01	                AND #FNX0_INT00_SOF
+.3e0073		c9 01		cmp #$01	                CMP #FNX0_INT00_SOF
+.3e0075		d0 f6		bne $3e006d	                BNE WaitForNextSOF;
+.3e0077		4c 3c 00	jmp $3e003c	                JMP HAVE_FUN
+.3e007a						exitshere:
+.3e007a						timeout
+.3e007a		a9 00		lda #$00	                LDA #0                  ; Return 0 for a timeout / SPACE
+.3e007c						return
+.3e007c		8f 08 00 00	sta $000008	                STA @l KRNL_BOOT_MENU_K          ; Store ther Keyboard Value
+.3e0080		a9 00		lda #$00	                LDA #$00
+.3e0082		8f 00 00 af	sta $af0000	                STA @l MASTER_CTRL_REG_L         ; Disable Everything
+.3e0086		22 2c 05 3e	jsl $3e052c	                JSL SS_VDMA_CLEAR_MEMORY_640_480 ; Clear the Bitmap Screen
+.3e008a		20 9f 00	jsr $3e009f	                JSR VickyII_Registers_Clear      ; Reset All Vicky Registers
+.3e008d		22 c0 10 00	jsl $0010c0	                JSL INITFONTSET ; Reload the Official FONT set
+.3e0091		22 bc 10 00	jsl $0010bc	                JSL INITCURSOR ; Reset the Cursor to its origin
+.3e0095		22 ac 10 00	jsl $0010ac	                JSL INITCHLUT ; The Software does change one of the CH LUT, so, let's Init again
+.3e0099		22 cc 10 00	jsl $0010cc	                JSL INITVKYTXTMODE  ; Init VICKY TextMode now contains Hi-Res Dipswitch read and Automatic Text Size Parameter adjust
+.3e009d		ea		nop		                NOP
+.3e009e		6b		rtl		                RTL
+.3e009f						VickyII_Registers_Clear:
+.3e009f		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e00a1		c2 10		rep #$10	                REP #$10        ; set X long
+.3e00a3		a2 00 00	ldx #$0000	                LDX #$0000
+.3e00a6		a9 00		lda #$00	                LDA #$00
+.3e00a8						ClearSpriteRegisters:
+.3e00a8		9f 00 0c af	sta $af0c00,x	                STA @l SP00_CONTROL_REG, X
+.3e00ac		e8		inx		                INX
+.3e00ad		e0 00 02	cpx #$0200	                CPX #$0200
+.3e00b0		d0 f6		bne $3e00a8	                BNE ClearSpriteRegisters
+.3e00b2		a2 00 00	ldx #$0000	                LDX #$0000
+.3e00b5		a9 00		lda #$00	                LDA #$00
+.3e00b7						ClearTiles0Registers:
+.3e00b7		9f 00 02 af	sta $af0200,x	                STA @l TL0_CONTROL_REG, X
+.3e00bb		e8		inx		                INX
+.3e00bc		e0 30 00	cpx #$0030	                CPX #$0030
+.3e00bf		d0 f6		bne $3e00b7	                BNE ClearTiles0Registers
+.3e00c1		ea		nop		                NOP
+.3e00c2		a2 00 00	ldx #$0000	                LDX #$0000
+.3e00c5		a9 00		lda #$00	                LDA #$00
+.3e00c7						ClearTiles1Registers:
+.3e00c7		9f 80 02 af	sta $af0280,x	                STA @l TILESET0_ADDY_L, X
+.3e00cb		e8		inx		                INX
+.3e00cc		e0 20 00	cpx #$0020	                CPX #$0020
+.3e00cf		d0 f6		bne $3e00c7	                BNE ClearTiles1Registers
+.3e00d1		ea		nop		                NOP
+.3e00d2		a2 00 00	ldx #$0000	                LDX #$0000
+.3e00d5		a9 00		lda #$00	                LDA #$00
+.3e00d7						ClearBitmapRegisters:
+.3e00d7		9f 00 01 af	sta $af0100,x	                STA @l BM0_CONTROL_REG, X
+.3e00db		9f 08 01 af	sta $af0108,x	                STA @l BM1_CONTROL_REG, X
+.3e00df		e8		inx		                INX
+.3e00e0		e0 10 00	cpx #$0010	                CPX #$0010
+.3e00e3		d0 f2		bne $3e00d7	                BNE ClearBitmapRegisters
+.3e00e5		60		rts		                RTS
+.3e00e6						Splash_Get_Machine_ID
+.3e00e6		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e00e8		af 87 e8 af	lda $afe887	                LDA @lGABE_SYS_STAT
+.3e00ec		29 03		and #$03	                AND #$03        ; Isolate the first 2 bits to know if it is a U or FMX
+.3e00ee		85 b0		sta $b0		                STA MODEL
+.3e00f0		c9 00		cmp #$00	                CMP #$00
+.3e00f2		f0 0e		beq $3e0102	                BEQ DONE
+.3e00f4		af 87 e8 af	lda $afe887	                LDA @lGABE_SYS_STAT
+.3e00f8		29 04		and #$04	                AND #GABE_SYS_STAT_MID2 ; High 4Meg, Low - 2Megs
+.3e00fa		c9 04		cmp #$04	                CMP #GABE_SYS_STAT_MID2
+.3e00fc		f0 04		beq $3e0102	                BEQ DONE
+.3e00fe		a9 02		lda #$02	                LDA #$02
+.3e0100		85 b0		sta $b0		                STA MODEL       ; In this Scheme 00 - FMX, 01 - U+, 02 - U
+.3e0102						DONE:
+.3e0102		60		rts		                RTS
+.3e0103						Splash_Load_FontSet
+.3e0103		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0105		c2 10		rep #$10	                REP #$10        ; set X long
+.3e0107		a2 00 00	ldx #$0000	                LDX #$0000
+.3e010a						DONE_LOADING_FONT:
+.3e010a		bf 00 08 3f	lda $3f0800,x	                LDA @l FONT_4_SPLASH, X
+.3e010e		9f 00 80 af	sta $af8000,x	                STA @l FONT_MEMORY_BANK0, X
+.3e0112		e8		inx		                INX
+.3e0113		e0 00 08	cpx #$0800	                CPX #2048
+.3e0116		d0 f2		bne $3e010a	                BNE DONE_LOADING_FONT
+.3e0118		60		rts		                RTS
+.3e0119						Splash_Clear_Screen
+.3e0119		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e011b		c2 10		rep #$10	                REP #$10        ; set X long
+.3e011d		a2 00 00	ldx #$0000	                LDX #$0000
+.3e0120						Branch_Clear:
+.3e0120		a9 20		lda #$20	                LDA #$20
+.3e0122		9f 00 a0 af	sta $afa000,x	                STA @l CS_TEXT_MEM_PTR,X
+.3e0126		a9 f0		lda #$f0	                LDA #$F0
+.3e0128		9f 00 c0 af	sta $afc000,x	                STA @l CS_COLOR_MEM_PTR,X
+.3e012c		e8		inx		                INX
+.3e012d		e0 00 20	cpx #$2000	                CPX #$2000
+.3e0130		d0 ee		bne $3e0120	                BNE Branch_Clear
+.3e0132		60		rts		                RTS
+=$00						IRQ_SOF_ST0 = $00
+=$01						IRQ_SOF_ST1 = $01
+=$02						IRQ_SOF_ST2 = $02
+.3e0133						Splash_Moniker_Color_Rolling
+.3e0133		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0135		af 40 01 00	lda $000140	                LDA @lINT_PENDING_REG0
+.3e0139		29 01		and #$01	                AND #FNX0_INT00_SOF
+.3e013b		8f 40 01 00	sta $000140	                STA @lINT_PENDING_REG0
+.3e013f		a5 68		lda $68		                LDA INTERRUPT_STATE
+.3e0141		c9 00		cmp #$00	                CMP #IRQ_SOF_ST0
+.3e0143		f0 0c		beq $3e0151	                BEQ SERVE_STATE0
+.3e0145		c9 01		cmp #$01	                CMP #IRQ_SOF_ST1
+.3e0147		f0 1a		beq $3e0163	                BEQ SERVE_STATE1
+.3e0149		c9 02		cmp #$02	                CMP #IRQ_SOF_ST2
+.3e014b		d0 03		bne $3e0150	                BNE NOT_SERVE_STATE2
+.3e014d		82 39 01	brl $3e0289	                BRL SERVE_STATE2
+.3e0150						NOT_SERVE_STATE2
+.3e0150		6b		rtl		                RTL
+.3e0151						SERVE_STATE0
+.3e0151		a5 69		lda $69		                LDA INTERRUPT_COUNT
+.3e0153		c9 04		cmp #$04	                CMP #$04
+.3e0155		f0 03		beq $3e015a	                BEQ SERVE_NEXT_STATE
+.3e0157		e6 69		inc $69		                INC INTERRUPT_COUNT
+.3e0159		6b		rtl		                RTL
+.3e015a						SERVE_NEXT_STATE
+.3e015a		a9 00		lda #$00	                LDA #$00
+.3e015c		85 69		sta $69		                STA INTERRUPT_COUNT
+.3e015e		a9 01		lda #$01	                LDA #IRQ_SOF_ST1
+.3e0160		85 68		sta $68		                STA INTERRUPT_STATE
+.3e0162		6b		rtl		                RTL
+.3e0163						SERVE_STATE1
+.3e0163		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3e0165		a9 00 00	lda #$0000	                LDA #$0000
+.3e0168		a2 00 00	ldx #$0000	                LDX #$0000
+.3e016b		e2 30		sep #$30	                SEP #$30        ; set A&X short
+.3e016d		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e016f		bf b0 02 3e	lda $3e02b0,x	                LDA @lCOLOR_POINTER+0, X
+.3e0173		aa		tax		                TAX
+.3e0174		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e0178		8f e0 3f af	sta $af3fe0	                STA @lGRPH_LUT7_PTR+992
+.3e017c		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e0180		8f e1 3f af	sta $af3fe1	                STA @lGRPH_LUT7_PTR+993
+.3e0184		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e0188		8f e2 3f af	sta $af3fe2	                STA @lGRPH_LUT7_PTR+994
+.3e018c		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e018e		bf b1 02 3e	lda $3e02b1,x	                LDA @lCOLOR_POINTER+1, X
+.3e0192		aa		tax		                TAX
+.3e0193		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e0197		8f e4 3f af	sta $af3fe4	                STA @lGRPH_LUT7_PTR+996
+.3e019b		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e019f		8f e5 3f af	sta $af3fe5	                STA @lGRPH_LUT7_PTR+997
+.3e01a3		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e01a7		8f e6 3f af	sta $af3fe6	                STA @lGRPH_LUT7_PTR+998
+.3e01ab		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e01ad		bf b2 02 3e	lda $3e02b2,x	                LDA @lCOLOR_POINTER+2, X
+.3e01b1		aa		tax		                TAX
+.3e01b2		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e01b6		8f e8 3f af	sta $af3fe8	                STA @lGRPH_LUT7_PTR+1000
+.3e01ba		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e01be		8f e9 3f af	sta $af3fe9	                STA @lGRPH_LUT7_PTR+1001
+.3e01c2		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e01c6		8f ea 3f af	sta $af3fea	                STA @lGRPH_LUT7_PTR+1002
+.3e01ca		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e01cc		bf b3 02 3e	lda $3e02b3,x	                LDA @lCOLOR_POINTER+3, X
+.3e01d0		aa		tax		                TAX
+.3e01d1		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e01d5		8f ec 3f af	sta $af3fec	                STA @lGRPH_LUT7_PTR+1004
+.3e01d9		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e01dd		8f ed 3f af	sta $af3fed	                STA @lGRPH_LUT7_PTR+1005
+.3e01e1		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e01e5		8f ee 3f af	sta $af3fee	                STA @lGRPH_LUT7_PTR+1006
+.3e01e9		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e01eb		bf b4 02 3e	lda $3e02b4,x	                LDA @lCOLOR_POINTER+4, X
+.3e01ef		aa		tax		                TAX
+.3e01f0		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e01f4		8f f0 3f af	sta $af3ff0	                STA @lGRPH_LUT7_PTR+1008
+.3e01f8		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e01fc		8f f1 3f af	sta $af3ff1	                STA @lGRPH_LUT7_PTR+1009
+.3e0200		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e0204		8f f2 3f af	sta $af3ff2	                STA @lGRPH_LUT7_PTR+1010
+.3e0208		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e020a		bf b5 02 3e	lda $3e02b5,x	                LDA @lCOLOR_POINTER+5, X
+.3e020e		aa		tax		                TAX
+.3e020f		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e0213		8f f4 3f af	sta $af3ff4	                STA @lGRPH_LUT7_PTR+1012
+.3e0217		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e021b		8f f5 3f af	sta $af3ff5	                STA @lGRPH_LUT7_PTR+1013
+.3e021f		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e0223		8f f6 3f af	sta $af3ff6	                STA @lGRPH_LUT7_PTR+1014
+.3e0227		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e0229		bf b6 02 3e	lda $3e02b6,x	                LDA @lCOLOR_POINTER+6, X
+.3e022d		aa		tax		                TAX
+.3e022e		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e0232		8f f8 3f af	sta $af3ff8	                STA @lGRPH_LUT7_PTR+1016
+.3e0236		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e023a		8f f9 3f af	sta $af3ff9	                STA @lGRPH_LUT7_PTR+1017
+.3e023e		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e0242		8f fa 3f af	sta $af3ffa	                STA @lGRPH_LUT7_PTR+1018
+.3e0246		a6 6a		ldx $6a		                LDX IRQ_COLOR_CHOICE
+.3e0248		bf b7 02 3e	lda $3e02b7,x	                LDA @lCOLOR_POINTER+7, X
+.3e024c		aa		tax		                TAX
+.3e024d		bf 90 02 3e	lda $3e0290,x	                LDA @lCOLOR_CHART, X
+.3e0251		8f fc 3f af	sta $af3ffc	                STA @lGRPH_LUT7_PTR+1020
+.3e0255		8f 50 1f af	sta $af1f50	                STA @lFG_CHAR_LUT_PTR + $10           ;
+.3e0259		bf 91 02 3e	lda $3e0291,x	                LDA @lCOLOR_CHART+1, X
+.3e025d		8f fd 3f af	sta $af3ffd	                STA @lGRPH_LUT7_PTR+1021
+.3e0261		8f 51 1f af	sta $af1f51	                STA @lFG_CHAR_LUT_PTR + $11            ;
+.3e0265		bf 92 02 3e	lda $3e0292,x	                LDA @lCOLOR_CHART+2, X
+.3e0269		8f fe 3f af	sta $af3ffe	                STA @lGRPH_LUT7_PTR+1022
+.3e026d		8f 52 1f af	sta $af1f52	                STA @lFG_CHAR_LUT_PTR + $12            ;
+.3e0271						HERE
+.3e0271		18		clc		                CLC
+.3e0272		a5 6a		lda $6a		                LDA IRQ_COLOR_CHOICE
+.3e0274		69 09		adc #$09	                ADC #$09
+.3e0276		85 6a		sta $6a		                STA IRQ_COLOR_CHOICE
+.3e0278		a5 6a		lda $6a		                LDA IRQ_COLOR_CHOICE
+.3e027a		c9 48		cmp #$48	                CMP #$48
+.3e027c		d0 04		bne $3e0282	                BNE EXIT_COLOR_CHANGE
+.3e027e		a9 00		lda #$00	                LDA #$00
+.3e0280		85 6a		sta $6a		                STA IRQ_COLOR_CHOICE
+.3e0282						EXIT_COLOR_CHANGE
+.3e0282		c2 10		rep #$10	                REP #$10        ; set X long
+.3e0284		a9 00		lda #$00	                LDA #IRQ_SOF_ST0
+.3e0286		85 68		sta $68		                STA INTERRUPT_STATE
+.3e0288		6b		rtl		                RTL
+.3e0289						SERVE_STATE2
+.3e0289		a9 00		lda #$00	                LDA #IRQ_SOF_ST0
+.3e028b		85 68		sta $68		                STA INTERRUPT_STATE
+.3e028d		6b		rtl		                RTL
+>3e028e						.align 16
+>3e0290		2e 2e a4 00			COLOR_CHART     .text 46, 46, 164, 00     ;248
+>3e0294		25 67 c1 00			                .text 37, 103, 193, 00    ;249
+>3e0298		20 9d a4 00			                .text 32, 157, 164, 00    ;250
+>3e029c		2c 9c 37 00			                .text 44, 156 , 55, 00    ;251
+>3e02a0		94 8e 2c 00			                .text 148, 142, 44, 00    ;252
+>3e02a4		91 4b 2b 00			                .text 145, 75, 43, 00     ;253
+>3e02a8		8e 2f 61 00			                .text 142, 47, 97, 00     ;254
+>3e02ac		21 50 7f 00			                .text 33, 80, 127, 00     ;255
+>3e02b0		00 04 08 0c 10 14 18 1c		COLOR_POINTER   .text 0,4,8,12,16,20,24,28,0
+>3e02b8		00
+>3e02b9		04 08 0c 10 14 18 1c 00		                .text 4,8,12,16,20,24,28,0,0
+>3e02c1		00
+>3e02c2		08 0c 10 14 18 1c 00 04		                .text 8,12,16,20,24,28,0,4,0
+>3e02ca		00
+>3e02cb		0c 10 14 18 1c 00 04 08		                .text 12,16,20,24,28,0,4,8,0
+>3e02d3		00
+>3e02d4		10 14 18 1c 00 04 08 0c		                .text 16,20,24,28,0,4,8,12,0
+>3e02dc		00
+>3e02dd		14 18 1c 00 04 08 0c 10		                .text 20,24,28,0,4,8,12,16,0
+>3e02e5		00
+>3e02e6		18 1c 00 04 08 0c 10 14		                .text 24,28,0,4,8,12,16,20,0
+>3e02ee		00
+>3e02ef		1c 00 04 08 0c 10 14 18		                .text 28,0,4,8,12,16,20,24,0
+>3e02f7		00
+
+;******  Processing file: src\SplashScreenCode/Splashscreen_Bitmap_Setup.asm
+
+=320						C256Moniker_SizeX = 320
+=64						C256Moniker_SizeY = 64
+=160						C256Moniker_PosX = 160
+=48						C256Moniker_PosY = 48
+=160						FMXMoniker_SizeX = 160
+=80						FMXMoniker_SizeY = 80
+=240						FMXMoniker_PosX = 240
+=110						FMXMoniker_PosY = 110
+=96						UPlusMoniker_SizeX = 96
+=64						UPlusMoniker_SizeY = 64
+=272						UPlusMoniker_PosX = 272
+=110						UPlusMoniker_PosY = 110
+=64						UMoniker_SizeX = 64
+=64						UMoniker_SizeY = 64
+=288						UMoniker_PosX = 288
+=110						UMoniker_PosY = 110
+=640						Bitmap_X_Size  = 640
+=480						Bitmap_Y_Size  = 480
+.3e02f8						Splashscreen_BitMapSetup
+.3e02f8		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e02fa		c2 10		rep #$10	                REP #$10        ; set X long
+.3e02fc		a9 0f		lda #$0f	        LDA #( Mstr_Ctrl_Graph_Mode_En | Mstr_Ctrl_Bitmap_En | Mstr_Ctrl_Text_Mode_En | Mstr_Ctrl_Text_Overlay );
+.3e02fe		8f 00 00 af	sta $af0000	        STA @l MASTER_CTRL_REG_L
+.3e0302		a9 00		lda #$00	        LDA #$00
+.3e0304		8f 01 00 af	sta $af0001	        STA @l MASTER_CTRL_REG_H
+.3e0308		a9 00		lda #$00	        LDA #$00
+.3e030a		8f 00 01 af	sta $af0100	        STA @l BM0_CONTROL_REG
+.3e030e		a9 0f		lda #$0f	        LDA #( BM_Enable | BM_LUT7)
+.3e0310		8f 08 01 af	sta $af0108	        STA @l BM1_CONTROL_REG
+.3e0314		a9 00		lda #$00	        LDA #$00
+.3e0316		8f 09 01 af	sta $af0109	        STA @l BM1_START_ADDY_L
+.3e031a		a9 00		lda #$00	        LDA #$00
+.3e031c		8f 0a 01 af	sta $af010a	        STA @l BM1_START_ADDY_M
+.3e0320		8f 0b 01 af	sta $af010b	        STA @l BM1_START_ADDY_H
+.3e0324		a9 01		lda #$01	        LDA #$01
+.3e0326		8f 04 00 af	sta $af0004	        STA BORDER_CTRL_REG
+.3e032a		a9 08		lda #$08	        LDA #$08
+.3e032c		8f 08 00 af	sta $af0008	        STA BORDER_X_SIZE
+.3e0330		8f 09 00 af	sta $af0009	        STA BORDER_Y_SIZE
+.3e0334		a9 80		lda #$80	        LDA #$80
+.3e0336		8f 06 00 af	sta $af0006	        STA BORDER_COLOR_G
+.3e033a		a9 00		lda #$00	        LDA #$00
+.3e033c		8f 05 00 af	sta $af0005	        STA BORDER_COLOR_B
+.3e0340		8f 07 00 af	sta $af0007	        STA BORDER_COLOR_R
+.3e0344		a9 a0		lda #$a0	        LDA #$A0
+.3e0346		8f 12 00 af	sta $af0012	        STA @l VKY_TXT_CURSOR_CHAR_REG
+.3e034a		a9 10		lda #$10	        LDA #$10
+.3e034c		8f 0e 00 af	sta $af000e	        STA @l BACKGROUND_COLOR_G
+.3e0350		a9 10		lda #$10	        LDA #$10
+.3e0352		8f 0f 00 af	sta $af000f	        STA @l BACKGROUND_COLOR_R
+.3e0356		8f 0d 00 af	sta $af000d	        STA @l BACKGROUND_COLOR_B
+.3e035a		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e035c		c2 10		rep #$10	                REP #$10        ; set X long
+.3e035e		a2 00 00	ldx #$0000	        LDX #$0000
+.3e0361						SS_LUT_BRANCH:
+.3e0361		bf 00 0d 3e	lda $3e0d00,x	        LDA @l SS_MONIKER_LUT, X
+.3e0365		ea		nop		        NOP
+.3e0366		9f 00 3c af	sta $af3c00,x	        STA @l GRPH_LUT7_PTR, X
+.3e036a		e8		inx		        INX
+.3e036b		e0 00 04	cpx #$0400	        CPX #1024
+.3e036e		d0 f1		bne $3e0361	        BNE SS_LUT_BRANCH
+.3e0370		a9 00		lda #$00	        LDA #$00
+.3e0372		8f 04 3c af	sta $af3c04	        STA @l GRPH_LUT7_PTR + 4
+.3e0376		8f 05 3c af	sta $af3c05	        STA @l GRPH_LUT7_PTR + 5
+.3e037a		8f 06 3c af	sta $af3c06	        STA @l GRPH_LUT7_PTR + 6
+.3e037e		22 2c 05 3e	jsl $3e052c	        JSL SS_VDMA_CLEAR_MEMORY_640_480;
+.3e0382		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0384		a9 00 11	lda #$1100	        LDA #<>SS_MONIKER      ; Set up the Source
+.3e0387		8f 22 04 af	sta $af0422	        STA @l SDMA_SRC_ADDY_L
+.3e038b		a9 00 50	lda #$5000	        LDA #<>( C256Moniker_SizeX * C256Moniker_SizeY )
+.3e038e		8f 28 04 af	sta $af0428	        STA @l SDMA_SIZE_L
+.3e0392		a9 00 00	lda #$0000	        LDA #$0000
+.3e0395		8f 2c 04 af	sta $af042c	        STA @l SDMA_SRC_STRIDE_L  ; Set the Source Stride in SDMA
+.3e0399		a9 a0 78	lda #$78a0	        LDA #<>( C256Moniker_PosY * Bitmap_X_Size + C256Moniker_PosX)    ; Set up the Source
+.3e039c		8f 05 04 af	sta $af0405	        STA @l VDMA_DST_ADDY_L
+.3e03a0		a9 40 01	lda #$0140	        LDA #C256Moniker_SizeX
+.3e03a3		8f 08 04 af	sta $af0408	        STA @l VDMA_X_SIZE_L
+.3e03a7		a9 40 00	lda #$0040	        LDA #C256Moniker_SizeY
+.3e03aa		8f 0a 04 af	sta $af040a	        STA @l VDMA_Y_SIZE_L
+.3e03ae		a9 80 02	lda #$0280	        LDA #Bitmap_X_Size
+.3e03b1		8f 0e 04 af	sta $af040e	        STA @l VDMA_DST_STRIDE_L  ; Set the Destination Stride in the VDMA
+.3e03b5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e03b7		a9 3e		lda #$3e	        LDA #`SS_MONIKER
+.3e03b9		8f 24 04 af	sta $af0424	        STA @l SDMA_SRC_ADDY_H
+.3e03bd		a9 00		lda #$00	        LDA #`( C256Moniker_SizeX * C256Moniker_SizeY )
+.3e03bf		8f 2a 04 af	sta $af042a	        STA @l SDMA_SIZE_H
+.3e03c3		a9 00		lda #$00	        LDA #$00
+.3e03c5		8f 2b 04 af	sta $af042b	        STA @l SDMA_SIZE_H+1 ; Just making sure there is no spurious data in the next register
+.3e03c9		a9 00		lda #$00	        LDA #`( C256Moniker_PosY * Bitmap_X_Size + C256Moniker_PosX)
+.3e03cb		8f 07 04 af	sta $af0407	        STA @l VDMA_DST_ADDY_H
+.3e03cf		22 e7 04 3e	jsl $3e04e7	        JSL SS_VDMA_SETUP_2_TRANSFER_IMAGE  ;VDMA Transfer from SRAM To VRAM to Transfer the Moniker 320x64
+.3e03d3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e03d5		af b0 00 00	lda $0000b0	        LDA @lMODEL
+.3e03d9		29 03		and #$03	        AND #$03
+.3e03db		c9 00		cmp #$00	        CMP #$00
+.3e03dd		f0 0b		beq $3e03ea	        BEQ DMA_FMX_Moniker
+.3e03df		c9 01		cmp #$01	        CMP #$01
+.3e03e1		f0 5b		beq $3e043e	        BEQ DMA_UPlus_Moniker
+.3e03e3		c9 02		cmp #$02	        CMP #$02
+.3e03e5		d0 03		bne $3e03ea	        BNE BAD_MODEL_NUMBER
+.3e03e7		82 a8 00	brl $3e0492	        BRL DMA_U_Moniker
+.3e03ea						 BAD_MODEL_NUMBER:
+.3e03ea						DMA_FMX_Moniker:
+.3e03ea		c2 20		rep #$20	                REP #$20        ; set A long
+.3e03ec		a9 00 61	lda #$6100	        LDA #<>SS_FMX_TXT      ; Set up the Source
+.3e03ef		8f 22 04 af	sta $af0422	        STA @l SDMA_SRC_ADDY_L
+.3e03f3		a9 00 32	lda #$3200	        LDA #<>( FMXMoniker_SizeX * FMXMoniker_SizeY )
+.3e03f6		8f 28 04 af	sta $af0428	        STA @l SDMA_SIZE_L
+.3e03fa		a9 00 00	lda #$0000	        LDA #$0000
+.3e03fd		8f 2c 04 af	sta $af042c	        STA @l SDMA_SRC_STRIDE_L  ; Set the Source Stride in SDMA
+.3e0401		a9 f0 13	lda #$13f0	        LDA #<>( FMXMoniker_PosY * Bitmap_X_Size + FMXMoniker_PosX)    ; Set up the Source
+.3e0404		8f 05 04 af	sta $af0405	        STA @l VDMA_DST_ADDY_L
+.3e0408		a9 a0 00	lda #$00a0	        LDA #FMXMoniker_SizeX
+.3e040b		8f 08 04 af	sta $af0408	        STA @l VDMA_X_SIZE_L
+.3e040f		a9 50 00	lda #$0050	        LDA #FMXMoniker_SizeY
+.3e0412		8f 0a 04 af	sta $af040a	        STA @l VDMA_Y_SIZE_L
+.3e0416		a9 80 02	lda #$0280	        LDA #Bitmap_X_Size
+.3e0419		8f 0e 04 af	sta $af040e	        STA @l VDMA_DST_STRIDE_L  ; Set the Destination Stride in the VDMA
+.3e041d		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e041f		a9 3e		lda #$3e	        LDA #`SS_FMX_TXT
+.3e0421		8f 24 04 af	sta $af0424	        STA @l SDMA_SRC_ADDY_H
+.3e0425		a9 00		lda #$00	        LDA #`( FMXMoniker_SizeX * FMXMoniker_SizeY )
+.3e0427		8f 2a 04 af	sta $af042a	        STA @l SDMA_SIZE_H
+.3e042b		a9 00		lda #$00	        LDA #$00
+.3e042d		8f 2b 04 af	sta $af042b	        STA @l SDMA_SIZE_H+1 ; Just making sure there is no spurious data in the next register
+.3e0431		a9 01		lda #$01	        LDA #`( FMXMoniker_PosY * Bitmap_X_Size + FMXMoniker_PosX)
+.3e0433		8f 07 04 af	sta $af0407	        STA @l VDMA_DST_ADDY_H
+.3e0437		22 e7 04 3e	jsl $3e04e7	        JSL SS_VDMA_SETUP_2_TRANSFER_IMAGE  ;VDMA Transfer from SRAM To VRAM to Transfer the Moniker 320x64
+.3e043b		4c e6 04	jmp $3e04e6	        JMP Done_DMA_Model_Moniker
+.3e043e						DMA_UPlus_Moniker:
+.3e043e		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0440		a9 00 93	lda #$9300	        LDA #<>SS_UPlus_TXT      ; Set up the Source
+.3e0443		8f 22 04 af	sta $af0422	        STA @l SDMA_SRC_ADDY_L
+.3e0447		a9 00 18	lda #$1800	        LDA #<>( UPlusMoniker_SizeX * UPlusMoniker_SizeY )
+.3e044a		8f 28 04 af	sta $af0428	        STA @l SDMA_SIZE_L
+.3e044e		a9 00 00	lda #$0000	        LDA #$0000
+.3e0451		8f 2c 04 af	sta $af042c	        STA @l SDMA_SRC_STRIDE_L  ; Set the Source Stride in SDMA
+.3e0455		a9 10 14	lda #$1410	        LDA #<>( UPlusMoniker_PosY * Bitmap_X_Size + UPlusMoniker_PosX)    ; Set up the Source
+.3e0458		8f 05 04 af	sta $af0405	        STA @l VDMA_DST_ADDY_L
+.3e045c		a9 60 00	lda #$0060	        LDA #UPlusMoniker_SizeX
+.3e045f		8f 08 04 af	sta $af0408	        STA @l VDMA_X_SIZE_L
+.3e0463		a9 40 00	lda #$0040	        LDA #UPlusMoniker_SizeY
+.3e0466		8f 0a 04 af	sta $af040a	        STA @l VDMA_Y_SIZE_L
+.3e046a		a9 80 02	lda #$0280	        LDA #Bitmap_X_Size
+.3e046d		8f 0e 04 af	sta $af040e	        STA @l VDMA_DST_STRIDE_L  ; Set the Destination Stride in the VDMA
+.3e0471		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0473		a9 3e		lda #$3e	        LDA #`SS_UPlus_TXT
+.3e0475		8f 24 04 af	sta $af0424	        STA @l SDMA_SRC_ADDY_H
+.3e0479		a9 00		lda #$00	        LDA #`( UPlusMoniker_SizeX * UPlusMoniker_SizeY )
+.3e047b		8f 2a 04 af	sta $af042a	        STA @l SDMA_SIZE_H
+.3e047f		a9 00		lda #$00	        LDA #$00
+.3e0481		8f 2b 04 af	sta $af042b	        STA @l SDMA_SIZE_H+1 ; Just making sure there is no spurious data in the next register
+.3e0485		a9 01		lda #$01	        LDA #`( UPlusMoniker_PosY * Bitmap_X_Size + UPlusMoniker_PosX)
+.3e0487		8f 07 04 af	sta $af0407	        STA @l VDMA_DST_ADDY_H
+.3e048b		22 e7 04 3e	jsl $3e04e7	        JSL SS_VDMA_SETUP_2_TRANSFER_IMAGE  ;VDMA Transfer from SRAM To VRAM to Transfer the Moniker 320x64
+.3e048f		4c e6 04	jmp $3e04e6	        JMP Done_DMA_Model_Moniker
+.3e0492						DMA_U_Moniker:
+.3e0492		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0494		a9 00 ab	lda #$ab00	        LDA #<>SS_U_TXT      ; Set up the Source
+.3e0497		8f 22 04 af	sta $af0422	        STA @l SDMA_SRC_ADDY_L
+.3e049b		a9 00 10	lda #$1000	        LDA #<>( UMoniker_SizeX *UMoniker_SizeY )
+.3e049e		8f 28 04 af	sta $af0428	        STA @l SDMA_SIZE_L
+.3e04a2		a9 00 00	lda #$0000	        LDA #$0000
+.3e04a5		8f 2c 04 af	sta $af042c	        STA @l SDMA_SRC_STRIDE_L  ; Set the Source Stride in SDMA
+.3e04a9		a9 20 14	lda #$1420	        LDA #<>( UMoniker_PosY * Bitmap_X_Size + UMoniker_PosX)    ; Set up the Source
+.3e04ac		8f 05 04 af	sta $af0405	        STA @l VDMA_DST_ADDY_L
+.3e04b0		a9 40 00	lda #$0040	        LDA #UMoniker_SizeX
+.3e04b3		8f 08 04 af	sta $af0408	        STA @l VDMA_X_SIZE_L
+.3e04b7		a9 40 00	lda #$0040	        LDA #UMoniker_SizeY
+.3e04ba		8f 0a 04 af	sta $af040a	        STA @l VDMA_Y_SIZE_L
+.3e04be		a9 80 02	lda #$0280	        LDA #Bitmap_X_Size
+.3e04c1		8f 0e 04 af	sta $af040e	        STA @l VDMA_DST_STRIDE_L  ; Set the Destination Stride in the VDMA
+.3e04c5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e04c7		a9 3e		lda #$3e	        LDA #`SS_U_TXT
+.3e04c9		8f 24 04 af	sta $af0424	        STA @l SDMA_SRC_ADDY_H
+.3e04cd		a9 00		lda #$00	        LDA #`( UMoniker_SizeX * UMoniker_SizeY )
+.3e04cf		8f 2a 04 af	sta $af042a	        STA @l SDMA_SIZE_H
+.3e04d3		a9 00		lda #$00	        LDA #$00
+.3e04d5		8f 2b 04 af	sta $af042b	        STA @l SDMA_SIZE_H+1 ; Just making sure there is no spurious data in the next register
+.3e04d9		a9 01		lda #$01	        LDA #`( UMoniker_PosY * Bitmap_X_Size + UMoniker_PosX)
+.3e04db		8f 07 04 af	sta $af0407	        STA @l VDMA_DST_ADDY_H
+.3e04df		22 e7 04 3e	jsl $3e04e7	        JSL SS_VDMA_SETUP_2_TRANSFER_IMAGE  ;VDMA Transfer from SRAM To VRAM to Transfer the Moniker 320x64
+.3e04e3		4c e6 04	jmp $3e04e6	        JMP Done_DMA_Model_Moniker
+.3e04e6						Done_DMA_Model_Moniker
+.3e04e6		6b		rtl		        RTL
+.3e04e7						SS_VDMA_SETUP_2_TRANSFER_IMAGE
+.3e04e7		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e04e9		a9 11		lda #$11	        LDA #( SDMA_CTRL0_Enable | SDMA_CTRL0_SysRAM_Src )
+.3e04eb		8f 20 04 af	sta $af0420	        STA @l SDMA_CTRL_REG0
+.3e04ef		a9 13		lda #$13	        LDA #( VDMA_CTRL_Enable |  VDMA_CTRL_SysRAM_Src | VDMA_CTRL_1D_2D )
+.3e04f1		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e04f5		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e04f7		af 00 04 af	lda $af0400	        LDA @l VDMA_CONTROL_REG
+.3e04fb		09 80		ora #$80	        ORA #VDMA_CTRL_Start_TRF
+.3e04fd		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e0501		af 20 04 af	lda $af0420	        LDA @l SDMA_CTRL_REG0
+.3e0505		09 80		ora #$80	        ORA #SDMA_CTRL0_Start_TRF
+.3e0507		8f 20 04 af	sta $af0420	        STA @l SDMA_CTRL_REG0
+.3e050b		ea		nop		        NOP ; When the transfer is started the CPU will be put on Hold (RDYn)...
+.3e050c		ea		nop		        NOP ; Before it actually gets to stop it will execute a couple more instructions
+.3e050d		ea		nop		        NOP ; From that point on, the CPU is halted (keep that in mind) No IRQ will be processed either during that time
+.3e050e		ea		nop		        NOP
+.3e050f		ea		nop		        NOP
+.3e0510		ea		nop		        NOP
+.3e0511		ea		nop		        NOP
+.3e0512		ea		nop		        NOP
+.3e0513		ea		nop		        NOP
+.3e0514		ea		nop		        NOP
+.3e0515		a9 00		lda #$00	        LDA #$00
+.3e0517		8f 20 04 af	sta $af0420	        STA @l SDMA_CTRL_REG0
+.3e051b						NOTFINISHED:
+.3e051b		af 01 04 af	lda $af0401	        LDA @l VDMA_STATUS_REG
+.3e051f		29 80		and #$80	        AND #$80
+.3e0521		c9 80		cmp #$80	        CMP #$80
+.3e0523		f0 f6		beq $3e051b	        BEQ NOTFINISHED
+.3e0525		a9 00		lda #$00	        LDA #$00
+.3e0527		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e052b		6b		rtl		        RTL
+.3e052c						SS_VDMA_CLEAR_MEMORY_640_480
+.3e052c		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e052e		a9 05		lda #$05	        LDA #( VDMA_CTRL_Enable | VDMA_CTRL_TRF_Fill )
+.3e0530		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e0534		a9 00		lda #$00	        LDA #$00
+.3e0536		8f 01 04 af	sta $af0401	        STA @l VDMA_BYTE_2_WRITE
+.3e053a		c2 20		rep #$20	                REP #$20        ; set A long
+.3e053c		a9 00 00	lda #$0000	        LDA #$0000      ; Set up the Source
+.3e053f		8f 05 04 af	sta $af0405	        STA @l VDMA_DST_ADDY_L
+.3e0543		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0545		a9 00		lda #$00	        LDA #$00
+.3e0547		8f 07 04 af	sta $af0407	        STA @l VDMA_DST_ADDY_H
+.3e054b		c2 20		rep #$20	                REP #$20        ; set A long
+.3e054d		a9 00 b0	lda #$b000	        LDA #<>(640*480)
+.3e0550		8f 08 04 af	sta $af0408	        STA @l VDMA_SIZE_L
+.3e0554		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0556		a9 04		lda #$04	        LDA #`(640*480)
+.3e0558		8f 0a 04 af	sta $af040a	        STA @l VDMA_SIZE_H
+.3e055c		a9 00		lda #$00	        LDA #$00
+.3e055e		8f 0b 04 af	sta $af040b	        STA @l VDMA_SIZE_H+1 ; Just making sure there is no spurious data in the next register
+.3e0562		af 00 04 af	lda $af0400	        LDA VDMA_CONTROL_REG
+.3e0566		09 80		ora #$80	        ORA #VDMA_CTRL_Start_TRF
+.3e0568		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e056c		ea		nop		         NOP ; When the transfer is started the CPU will be put on Hold (RDYn)...
+.3e056d		ea		nop		        NOP ; Before it actually gets to stop it will execute a couple more instructions
+.3e056e		ea		nop		        NOP ; From that point on, the CPU is halted (keep that in mind) No IRQ will be processed either during that time
+.3e056f		ea		nop		        NOP
+.3e0570		ea		nop		        NOP
+.3e0571		ea		nop		        NOP
+.3e0572		ea		nop		        NOP
+.3e0573		ea		nop		        NOP
+.3e0574						SS_VDMA_CLR_LOOPA:
+.3e0574		af 01 04 af	lda $af0401	        LDA @l VDMA_STATUS_REG
+.3e0578		29 80		and #$80	        AND #$80
+.3e057a		c9 80		cmp #$80	        CMP #$80  ; Check if bit $80 is cleared to indicate that the VDMA is done.
+.3e057c		f0 f6		beq $3e0574	        BEQ SS_VDMA_CLR_LOOPA
+.3e057e		ea		nop		        NOP
+.3e057f		a9 00		lda #$00	        LDA #$00
+.3e0581		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e0585		6b		rtl		        RTL
+.3e0586						SS_VDMA_TRANSFER_VRAM_2_VRAM
+.3e0586		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0588		a9 01		lda #$01	        LDA #( VDMA_CTRL_Enable )
+.3e058a		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e058e		a9 00		lda #$00	        LDA #$00
+.3e0590		8f 01 04 af	sta $af0401	        STA @l VDMA_BYTE_2_WRITE
+.3e0594		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0596		a9 00 96	lda #$9600	        LDA #$9600      ; Set up the Source
+.3e0599		8f 02 04 af	sta $af0402	        STA @l VDMA_SRC_ADDY_L
+.3e059d		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e059f		a9 00		lda #$00	        LDA #$00
+.3e05a1		8f 04 04 af	sta $af0404	        STA @l VDMA_SRC_ADDY_H
+.3e05a5		c2 20		rep #$20	                REP #$20        ; set A long
+.3e05a7		a9 00 00	lda #$0000	        LDA #$0000      ; Set up the Source
+.3e05aa		8f 05 04 af	sta $af0405	        STA @l VDMA_DST_ADDY_L
+.3e05ae		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e05b0		a9 00		lda #$00	        LDA #$00
+.3e05b2		8f 07 04 af	sta $af0407	        STA @l VDMA_DST_ADDY_H
+.3e05b6		c2 20		rep #$20	                REP #$20        ; set A long
+.3e05b8		a9 00 14	lda #$1400	        LDA #<>(320*16)
+.3e05bb		8f 08 04 af	sta $af0408	        STA @l VDMA_SIZE_L
+.3e05bf		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e05c1		a9 00		lda #$00	        LDA #`(320*16)
+.3e05c3		8f 0a 04 af	sta $af040a	        STA @l VDMA_SIZE_H
+.3e05c7		a9 00		lda #$00	        LDA #$00
+.3e05c9		8f 0b 04 af	sta $af040b	        STA @l VDMA_SIZE_H+1 ; Just making sure there is no spurious data in the next register
+.3e05cd		af 00 04 af	lda $af0400	        LDA VDMA_CONTROL_REG
+.3e05d1		09 80		ora #$80	        ORA #VDMA_CTRL_Start_TRF
+.3e05d3		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e05d7		ea		nop		        NOP
+.3e05d8		ea		nop		        NOP
+.3e05d9		ea		nop		        NOP
+.3e05da						SS_VDMA_CLR_LOOPB:
+.3e05da		af 01 04 af	lda $af0401	        LDA @l VDMA_STATUS_REG
+.3e05de		29 80		and #$80	        AND #$80
+.3e05e0		c9 80		cmp #$80	        CMP #$80  ; Check if bit $80 is cleared to indicate that the VDMA is done.
+.3e05e2		f0 f6		beq $3e05da	        BEQ SS_VDMA_CLR_LOOPB
+.3e05e4		ea		nop		        NOP
+.3e05e5		a9 00		lda #$00	        LDA #$00
+.3e05e7		8f 00 04 af	sta $af0400	        STA @l VDMA_CONTROL_REG
+.3e05eb		6b		rtl		        RTL
+
+;******  Return to file: src\kernel.asm
+
+
+;******  Processing file: src\SplashScreenCode/Splashscreen_Text_Display.asm
+
+=$000098					TEXT_SRC_PTR_L      = $000098
+=$00009a					TEXT_SRC_PTR_H      = $00009A
+=$00009c					TEXT_DST_PTR_L      = $00009C
+=$00009e					TEXT_DST_PTR_H      = $00009E
+=$0000a0					TEXT_INDEX          = $0000A0
+=$0000a0					MOD_SELECT_L        = $0000A0
+=$0000a2					MOD_SELECT_H        = $0000A2
+=$0000a2					TEXT_CURSOR_X       = $0000A2
+=$0000a4					TEXT_CURSOR_Y       = $0000A4
+=$0000a6					LINE_INDEX          = $0000A6
+=$0000a8					COLOR_DST_PTR_L     = $0000A8
+=$0000aa					COLOR_DST_PTR_H     = $0000AA
+=$0000b0					MODEL               = $0000B0
+=23						NumberOfEntry = size( TEXT_POSX ) / 2; (1 more then the actual number)
+.3e05ec						Set_Text_Color:
+.3e05ec		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3e05ee		a9 00 00	lda #$0000	            LDA #00
+.3e05f1		85 a2		sta $a2		            STA TEXT_CURSOR_X
+.3e05f3		a9 30 00	lda #$0030	            LDA #48
+.3e05f6		85 a4		sta $a4		            STA TEXT_CURSOR_Y
+.3e05f8		20 90 08	jsr $3e0890	            JSR Line_Display_Compute_Pointer
+.3e05fb		a0 00 00	ldy #$0000	            LDY #$0000
+.3e05fe		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0600		a9 40		lda #$40	            LDA #$40
+.3e0602						SetColorBranch:
+.3e0602		97 a8		sta [$a8],y	            STA [COLOR_DST_PTR_L],Y
+.3e0604		c8		iny		            INY
+.3e0605		c0 50 00	cpy #$0050	            CPY #80
+.3e0608		d0 f8		bne $3e0602	            BNE SetColorBranch
+.3e060a		60		rts		            RTS
+.3e060b						Model_Update_Info_Field:
+.3e060b		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3e060d		a9 00 00	lda #$0000	            LDA #$0000
+.3e0610		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0612		a5 b0		lda $b0		            LDA MODEL
+.3e0614		0a		asl a		            ASL
+.3e0615		0a		asl a		            ASL
+.3e0616		aa		tax		            TAX
+.3e0617		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0619		bf 43 0c 3e	lda $3e0c43,x	            LDA MODEL_TABLE, X
+.3e061d		85 a0		sta $a0		            STA MOD_SELECT_L
+.3e061f		bf 45 0c 3e	lda $3e0c45,x	            LDA MODEL_TABLE + 2, X
+.3e0623		85 a2		sta $a2		            STA MOD_SELECT_H
+.3e0625		a0 00 00	ldy #$0000	            LDY #$0000
+.3e0628		84 a6		sty $a6		            STY LINE_INDEX
+.3e062a						Next_Change_Here:
+.3e062a		c2 20		rep #$20	                REP #$20        ; set A long
+.3e062c		a4 a6		ldy $a6		            LDY LINE_INDEX
+.3e062e		bb		tyx		            TYX
+.3e062f		b7 a0		lda [$a0],y	            LDA [MOD_SELECT_L], Y
+.3e0631		85 98		sta $98		            STA TEXT_SRC_PTR_L
+.3e0633		bf 93 0c 3e	lda $3e0c93,x	            LDA LINE_MOD, X
+.3e0637		85 9c		sta $9c		            STA TEXT_DST_PTR_L
+.3e0639		c8		iny		            INY
+.3e063a		c8		iny		            INY
+.3e063b		bb		tyx		            TYX
+.3e063c		b7 a0		lda [$a0],y	            LDA [MOD_SELECT_L], Y
+.3e063e		85 9a		sta $9a		            STA TEXT_SRC_PTR_H
+.3e0640		bf 93 0c 3e	lda $3e0c93,x	            LDA LINE_MOD, X
+.3e0644		85 9e		sta $9e		            STA TEXT_DST_PTR_H
+.3e0646		c8		iny		            INY
+.3e0647		c8		iny		            INY
+.3e0648		84 a6		sty $a6		            STY LINE_INDEX
+.3e064a		c0 10 00	cpy #$0010	            CPY #16
+.3e064d		f0 10		beq $3e065f	            BEQ LetsMoveOn
+.3e064f		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0651		a0 00 00	ldy #$0000	            LDY #$0000
+.3e0654						nextchar:
+.3e0654		b7 98		lda [$98],y	            LDA [TEXT_SRC_PTR_L], Y
+.3e0656		c9 00		cmp #$00	            CMP #$00
+.3e0658		f0 d0		beq $3e062a	            BEQ Next_Change_Here
+.3e065a		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e065c		c8		iny		            INY
+.3e065d		80 f5		bra $3e0654	            BRA nextchar
+.3e065f						LetsMoveOn:
+.3e065f		af 9f 0c 3e	lda $3e0c9f	            LDA LINE_MOD + 12
+.3e0663		85 9c		sta $9c		            STA TEXT_DST_PTR_L
+.3e0665		a0 00 00	ldy #$0000	            LDY #$0000
+.3e0668		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e066a		af 05 e8 af	lda $afe805	            LDA @lREVOFPCB_C
+.3e066e		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e0670		c8		iny		            INY
+.3e0671		af 06 e8 af	lda $afe806	            LDA @lREVOFPCB_4
+.3e0675		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e0677		c8		iny		            INY
+.3e0678		af 07 e8 af	lda $afe807	            LDA @lREVOFPCB_A
+.3e067c		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e067e		18		clc		            CLC
+.3e067f		af 0d 07 af	lda $af070d	            LDA @lFPGA_DOR   ; it is in BCD
+.3e0683		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e0686		8f 6e 0a 3e	sta $3e0a6e	            STA @lLINE8 + 56    ; FAT VICKY in U/U+ Model
+.3e068a		8f a7 0a 3e	sta $3e0aa7	            STA @lLINE9 + 47    ; GABE in FMX
+.3e068e		8f ed 0a 3e	sta $3e0aed	            STA @lLINE10 + 51   ; VICKY II in FMX
+.3e0692		af 0d 07 af	lda $af070d	            LDA @lFPGA_DOR
+.3e0696		29 0f		and #$0f	            AND #$0F
+.3e0698		69 30		adc #$30	            ADC #$30
+.3e069a		8f 6f 0a 3e	sta $3e0a6f	            STA @lLINE8 + 57    ; FAT VICKY in U/U+ Model
+.3e069e		8f a8 0a 3e	sta $3e0aa8	            STA @lLINE9 + 48    ; GABE in FMX
+.3e06a2		8f ee 0a 3e	sta $3e0aee	            STA @lLINE10 + 52   ; VICKY II in FMX
+.3e06a6		af 0e 07 af	lda $af070e	            LDA @lFPGA_MOR   ; it is in BCD
+.3e06aa		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e06ad		8f 71 0a 3e	sta $3e0a71	            STA @lLINE8 + 59    ; FAT VICKY in U/U+ Model
+.3e06b1		8f aa 0a 3e	sta $3e0aaa	            STA @lLINE9 + 50    ; GABE in FMX
+.3e06b5		8f f0 0a 3e	sta $3e0af0	            STA @lLINE10 + 54   ; VICKY II in FMX
+.3e06b9		af 0e 07 af	lda $af070e	            LDA @lFPGA_MOR
+.3e06bd		29 0f		and #$0f	            AND #$0F
+.3e06bf		69 30		adc #$30	            ADC #$30
+.3e06c1		8f 72 0a 3e	sta $3e0a72	            STA @lLINE8 + 60    ; FAT VICKY in U/U+ Model
+.3e06c5		8f ab 0a 3e	sta $3e0aab	            STA @lLINE9 + 51    ; GABE in FMX
+.3e06c9		8f f1 0a 3e	sta $3e0af1	            STA @lLINE10 + 55   ; VICKY II in FMX
+.3e06cd		af 0f 07 af	lda $af070f	            LDA @lFPGA_YOR   ; it is in BCD
+.3e06d1		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e06d4		8f 74 0a 3e	sta $3e0a74	            STA @lLINE8 + 62    ; FAT VICKY in U/U+ Model
+.3e06d8		8f ad 0a 3e	sta $3e0aad	            STA @lLINE9 + 53    ; GABE in FMX
+.3e06dc		8f f2 0a 3e	sta $3e0af2	            STA @lLINE10 + 56   ; VICKY II in FMX
+.3e06e0		af 0f 07 af	lda $af070f	            LDA @lFPGA_YOR
+.3e06e4		29 0f		and #$0f	            AND #$0F
+.3e06e6		69 30		adc #$30	            ADC #$30
+.3e06e8		8f 75 0a 3e	sta $3e0a75	            STA @lLINE8 + 63    ; FAT VICKY in U/U+ Model
+.3e06ec		8f ae 0a 3e	sta $3e0aae	            STA @lLINE9 + 54    ; GABE in FMX
+.3e06f0		8f f3 0a 3e	sta $3e0af3	            STA @lLINE10 + 57   ; VICKY II in FMX
+.3e06f4		af 8b e8 af	lda $afe88b	            LDA @l GABE_SUBVERSION_HI
+.3e06f8		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e06fb		8f 64 0a 3e	sta $3e0a64	            STA @lLINE8 + 46
+.3e06ff		8f 9d 0a 3e	sta $3e0a9d	            STA @lLINE9 + 37    ; When FMX, this is the Info for GABE
+.3e0703		af 8b e8 af	lda $afe88b	            LDA @l GABE_SUBVERSION_HI
+.3e0707		29 0f		and #$0f	            AND #$0F
+.3e0709		69 30		adc #$30	            ADC #$30
+.3e070b		8f 65 0a 3e	sta $3e0a65	            STA @lLINE8 + 47
+.3e070f		8f 9e 0a 3e	sta $3e0a9e	            STA @lLINE9 + 38    ; When FMX, this is the Info for GABE
+.3e0713		af 8a e8 af	lda $afe88a	            LDA @l GABE_SUBVERSION_LO
+.3e0717		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e071a		8f 66 0a 3e	sta $3e0a66	            STA @lLINE8 + 48
+.3e071e		8f 9f 0a 3e	sta $3e0a9f	            STA @lLINE9 + 39    ; When FMX, this is the Info for GABE
+.3e0722		af 8a e8 af	lda $afe88a	            LDA @l GABE_SUBVERSION_LO
+.3e0726		29 0f		and #$0f	            AND #$0F
+.3e0728		69 30		adc #$30	            ADC #$30
+.3e072a		8f 67 0a 3e	sta $3e0a67	            STA @lLINE8 + 49
+.3e072e		8f a0 0a 3e	sta $3e0aa0	            STA @lLINE9 + 40    ; When FMX, this is the Info for GABE
+.3e0732		af 8d e8 af	lda $afe88d	            LDA @l GABE_VERSION_HI
+.3e0736		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e0739		8f 58 0a 3e	sta $3e0a58	            STA @lLINE8 + 34
+.3e073d		8f 91 0a 3e	sta $3e0a91	            STA @lLINE9 + 25    ; When FMX, this is the Info for GABE
+.3e0741		af 8d e8 af	lda $afe88d	            LDA @l GABE_VERSION_HI
+.3e0745		29 0f		and #$0f	            AND #$0F
+.3e0747		69 30		adc #$30	            ADC #$30
+.3e0749		8f 59 0a 3e	sta $3e0a59	            STA @lLINE8 + 35
+.3e074d		8f 92 0a 3e	sta $3e0a92	            STA @lLINE9 + 26    ; When FMX, this is the Info for GABE
+.3e0751		af 8c e8 af	lda $afe88c	            LDA @l GABE_VERSION_LO
+.3e0755		20 8a 07	jsr $3e078a	            JSR HighNibblerBCD
+.3e0758		8f 5a 0a 3e	sta $3e0a5a	            STA @lLINE8 + 36
+.3e075c		8f 93 0a 3e	sta $3e0a93	            STA @lLINE9 + 27    ; When FMX, this is the Info for GABE
+.3e0760		af 8c e8 af	lda $afe88c	            LDA @l GABE_VERSION_LO
+.3e0764		29 0f		and #$0f	            AND #$0F
+.3e0766		69 30		adc #$30	            ADC #$30
+.3e0768		8f 5b 0a 3e	sta $3e0a5b	            STA @lLINE8 + 37
+.3e076c		8f 94 0a 3e	sta $3e0a94	            STA @lLINE9 + 28    ; When FMX, this is the Info for GABE
+.3e0770		20 e3 07	jsr $3e07e3	            JSR GODETECTHIRES ; Dip-Switch and Change Text
+.3e0773		20 04 08	jsr $3e0804	            JSR GODETECTHDD   ; Dip-Switch and Change Text
+.3e0776		20 05 08	jsr $3e0805	            JSR GODETECTEXP   ; Go Check if there is a Card Change Text
+.3e0779		a5 b0		lda $b0		            LDA MODEL
+.3e077b		29 03		and #$03	            AND #$03
+.3e077d		c9 00		cmp #$00	            CMP #$00
+.3e077f		f0 12		beq $3e0793	            BEQ Erase_FATVicky_Line;
+.3e0781		c9 01		cmp #$01	            CMP #$01
+.3e0783		f0 29		beq $3e07ae	            BEQ Erase_2Lines;
+.3e0785		c9 02		cmp #$02	            CMP #$02
+.3e0787		f0 25		beq $3e07ae	            BEQ Erase_2Lines;
+.3e0789		60		rts		            RTS
+.3e078a						HighNibblerBCD:
+.3e078a		29 f0		and #$f0	            AND #$F0
+.3e078c		4a		lsr a		            LSR A
+.3e078d		4a		lsr a		            LSR A
+.3e078e		4a		lsr a		            LSR A
+.3e078f		4a		lsr a		            LSR A
+.3e0790		69 30		adc #$30	            ADC #$30
+.3e0792		60		rts		            RTS
+.3e0793						Erase_FATVicky_Line:
+.3e0793		c2 20		rep #$20	                REP #$20        ; set A long
+.3e0795		a9 36 0a	lda #$0a36	            LDA #<>LINE8
+.3e0798		85 9c		sta $9c		            STA TEXT_DST_PTR_L
+.3e079a		a9 3e 00	lda #$003e	            LDA #`LINE8
+.3e079d		85 9e		sta $9e		            STA TEXT_DST_PTR_H
+.3e079f		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e07a1		a0 00 00	ldy #$0000	            LDY #$0000
+.3e07a4		a9 20		lda #$20	            LDA #$20    ; Put One Space
+.3e07a6		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e07a8		c8		iny		            INY
+.3e07a9		a9 00		lda #$00	            LDA #$00    ; Terminate the Line
+.3e07ab		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e07ad		60		rts		            RTS
+.3e07ae						Erase_2Lines
+.3e07ae		c2 20		rep #$20	                REP #$20        ; set A long
+.3e07b0		a9 78 0a	lda #$0a78	            LDA #<>LINE9
+.3e07b3		85 9c		sta $9c		            STA TEXT_DST_PTR_L
+.3e07b5		a9 3e 00	lda #$003e	            LDA #`LINE9
+.3e07b8		85 9e		sta $9e		            STA TEXT_DST_PTR_H
+.3e07ba		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e07bc		a0 00 00	ldy #$0000	            LDY #$0000
+.3e07bf		a9 20		lda #$20	            LDA #$20    ; Put One Space
+.3e07c1		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e07c3		c8		iny		            INY
+.3e07c4		a9 00		lda #$00	            LDA #$00    ; Terminate the Line
+.3e07c6		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e07c8		c2 20		rep #$20	                REP #$20        ; set A long
+.3e07ca		a9 ba 0a	lda #$0aba	            LDA #<>LINE10
+.3e07cd		85 9c		sta $9c		            STA TEXT_DST_PTR_L
+.3e07cf		a9 3e 00	lda #$003e	            LDA #`LINE10
+.3e07d2		85 9e		sta $9e		            STA TEXT_DST_PTR_H
+.3e07d4		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e07d6		a0 00 00	ldy #$0000	            LDY #$0000
+.3e07d9		a9 20		lda #$20	            LDA #$20    ; Put One Space
+.3e07db		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e07dd		c8		iny		            INY
+.3e07de		a9 00		lda #$00	            LDA #$00    ; Terminate the Line
+.3e07e0		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e07e2		60		rts		            RTS
+.3e07e3						GODETECTHIRES
+.3e07e3		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e07e5		af 02 00 af	lda $af0002	            LDA @l GAMMA_CTRL_REG   ; Go Read the Hi-Res DIP Switch Value
+.3e07e9		29 10		and #$10	            AND #HIRES_DP_SW_VAL    ; Isolate the Hi-Res Bit ($10) when 1 = 640x480, 0 = 800x600
+.3e07eb		c9 10		cmp #$10	            CMP #HIRES_DP_SW_VAL    ; When the Switch is off, the Returned value is 1 (The Pullup is there)
+.3e07ed		f0 14		beq $3e0803	            BEQ WeAreDone
+.3e07ef		c2 10		rep #$10	                REP #$10        ; set X long
+.3e07f1		a2 00 00	ldx #$0000	            LDX #$0000
+.3e07f4						ChangeNextChar
+.3e07f4		bf f3 0c 3e	lda $3e0cf3,x	            LDA @l ON_TEXT, X
+.3e07f8		c9 00		cmp #$00	            CMP #$00
+.3e07fa		f0 07		beq $3e0803	            BEQ WeAreDone
+.3e07fc		9f e7 0b 3e	sta $3e0be7,x	            STA @l LINE17 +13, X
+.3e0800		e8		inx		            INX
+.3e0801		d0 f1		bne $3e07f4	            BNE ChangeNextChar
+.3e0803						WeAreDone
+.3e0803						NoExpansionCardPresent
+.3e0803		60		rts		            RTS
+.3e0804						GODETECTHDD
+.3e0804		60		rts		            RTS
+.3e0805						GODETECTEXP
+.3e0805		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0807		af 87 e8 af	lda $afe887	            LDA @L GABE_SYS_STAT      ; Let's check the Presence of an Expansion Card here
+.3e080b		29 10		and #$10	            AND #GABE_SYS_STAT_EXP    ; When there is a Card the Value is 1
+.3e080d		c9 10		cmp #$10	            CMP #GABE_SYS_STAT_EXP
+.3e080f		d0 25		bne $3e0836	            BNE NoExpansionCardPresent
+.3e0811		c2 10		rep #$10	                REP #$10        ; set X long
+.3e0813		a2 00 00	ldx #$0000	            LDX #$0000
+.3e0816						ChangeNextChar
+.3e0816		bf f7 0c 3e	lda $3e0cf7,x	            LDA @l YES_TEXT, X
+.3e081a		c9 00		cmp #$00	            CMP #$00
+.3e081c		f0 07		beq $3e0825	            BEQ WeAreDone
+.3e081e		9f 19 0c 3e	sta $3e0c19,x	            STA @l LINE19 +26, X
+.3e0822		e8		inx		            INX
+.3e0823		d0 f1		bne $3e0816	            BNE ChangeNextChar
+.3e0825						WeAreDone
+.3e0825		a2 00 00	ldx #$0000	            LDX #$0000
+.3e0828						AddCardName
+.3e0828		bf 00 00 ae	lda $ae0000,x	            LDA @l EVID_ID_NAME_ASCII, X
+.3e082c		9f 1d 0c 3e	sta $3e0c1d,x	            STA @l LINE20, X
+.3e0830		e8		inx		            INX
+.3e0831		e0 10 00	cpx #$0010	            CPX #$10
+.3e0834		d0 f2		bne $3e0828	            BNE AddCardName
+.3e0836						NoExpansionCardPresent
+.3e0836		60		rts		            RTS
+.3e0837						Line_Setup_Before_Display
+.3e0837		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3e0839		a5 a6		lda $a6		            LDA LINE_INDEX
+.3e083b		c9 17 00	cmp #$0017	            CMP #NumberOfEntry
+.3e083e		f0 33		beq $3e0873	            BEQ DONE
+.3e0840		a5 a6		lda $a6		            LDA LINE_INDEX
+.3e0842		0a		asl a		            ASL A
+.3e0843		0a		asl a		            ASL A
+.3e0844		aa		tax		            TAX
+.3e0845		bf b8 08 3e	lda $3e08b8,x	            LDA TEXT_TABLE, X
+.3e0849		85 98		sta $98		            STA TEXT_SRC_PTR_L
+.3e084b		bf ba 08 3e	lda $3e08ba,x	            LDA TEXT_TABLE + 2, X
+.3e084f		85 9a		sta $9a		            STA TEXT_SRC_PTR_H
+.3e0851		a5 a6		lda $a6		            LDA LINE_INDEX
+.3e0853		0a		asl a		            ASL A
+.3e0854		aa		tax		            TAX
+.3e0855		bf 14 09 3e	lda $3e0914,x	            LDA TEXT_POSX, X
+.3e0859		85 a2		sta $a2		            STA TEXT_CURSOR_X
+.3e085b		8f 14 00 af	sta $af0014	            STA @l VKY_TXT_CURSOR_X_REG_L
+.3e085f		bf 42 09 3e	lda $3e0942,x	            LDA TEXT_POSY, X
+.3e0863		85 a4		sta $a4		            STA TEXT_CURSOR_Y
+.3e0865		8f 16 00 af	sta $af0016	            STA @l VKY_TXT_CURSOR_Y_REG_L
+.3e0869		20 90 08	jsr $3e0890	            JSR Line_Display_Compute_Pointer
+.3e086c		a9 00 00	lda #$0000	            LDA #$0000
+.3e086f		85 a0		sta $a0		            STA TEXT_INDEX
+.3e0871		e6 a6		inc $a6		            INC LINE_INDEX
+.3e0873						DONE:
+.3e0873		60		rts		            RTS
+.3e0874						Line_Display_1_Character
+.3e0874		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3e0876		e6 a2		inc $a2		            INC TEXT_CURSOR_X       ; Always put the Cursor In Front of the "To be displayed Char"
+.3e0878		a5 a2		lda $a2		            LDA TEXT_CURSOR_X
+.3e087a		8f 14 00 af	sta $af0014	            STA @l VKY_TXT_CURSOR_X_REG_L
+.3e087e		e2 20		sep #$20	                SEP #$20        ; set A short
+.3e0880		38		sec		            SEC
+.3e0881		a4 a0		ldy $a0		            LDY TEXT_INDEX
+.3e0883		b7 98		lda [$98],y	            LDA [TEXT_SRC_PTR_L], Y
+.3e0885		c9 00		cmp #$00	            CMP #$00
+.3e0887		f0 06		beq $3e088f	            BEQ WE_ARE_DONE;
+.3e0889		18		clc		            CLC
+.3e088a		97 9c		sta [$9c],y	            STA [TEXT_DST_PTR_L], Y
+.3e088c		c8		iny		            INY
+.3e088d		84 a0		sty $a0		            STY TEXT_INDEX
+.3e088f						WE_ARE_DONE:
+.3e088f		60		rts		            RTS
+.3e0890						Line_Display_Compute_Pointer
+.3e0890		c2 30		rep #$30	                REP #$30        ; set A&X long
+.3e0892		a5 a4		lda $a4		            LDA TEXT_CURSOR_Y
+.3e0894		8f 00 01 00	sta $000100	            STA @lUNSIGNED_MULT_A_LO
+.3e0898		a9 50 00	lda #$0050	            LDA #80
+.3e089b		8f 02 01 00	sta $000102	            STA @lUNSIGNED_MULT_B_LO
+.3e089f		18		clc		            CLC
+.3e08a0		af 04 01 00	lda $000104	            LDA @lUNSIGNED_MULT_AL_LO
+.3e08a4		65 a2		adc $a2		            ADC TEXT_CURSOR_X
+.3e08a6		69 00 a0	adc #$a000	            ADC #$A000
+.3e08a9		85 9c		sta $9c		            STA TEXT_DST_PTR_L
+.3e08ab		69 00 20	adc #$2000	            ADC #$2000
+.3e08ae		85 a8		sta $a8		            STA COLOR_DST_PTR_L
+.3e08b0		a9 af 00	lda #$00af	            LDA #$00AF
+.3e08b3		85 9e		sta $9e		            STA TEXT_DST_PTR_H
+.3e08b5		85 aa		sta $aa		            STA COLOR_DST_PTR_H
+.3e08b7		60		rts		            RTS
+>3e08b8		70 09 3e 00 91 09 3e 00		TEXT_TABLE  .dword LINE0, LINE1, LINE2, LINE3, LINE4, LINE5, LINE6, LINE7
+>3e08c0		a7 09 3e 00 b5 09 3e 00 cd 09 3e 00 f0 09 3e 00
+>3e08d0		14 0a 3e 00 29 0a 3e 00
+>3e08d8		36 0a 3e 00 78 0a 3e 00		            .dword LINE8, LINE9, LINE10, LINE11, LINE12, LINE13, LINE14, LINE15
+>3e08e0		ba 0a 3e 00 fc 0a 3e 00 06 0b 3e 00 2f 0b 3e 00
+>3e08f0		66 0b 3e 00 89 0b 3e 00
+>3e08f8		9b 0b 3e 00 da 0b 3e 00		            .dword LINE16, LINE17, LINE18, LINE19, LINE20, LINE21, LINE22
+>3e0900		ec 0b 3e 00 ff 0b 3e 00 1d 0c 3e 00 2e 0c 3e 00
+>3e0910		41 0c 3e 00
+>3e0914		06 00 06 00 06 00 06 00		TEXT_POSX  .word  leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, leftAlign, 31, leftAlign, 5, 25, 45, 45, 30, 72                     ;
+>3e091c		06 00 06 00 06 00 06 00 06 00 06 00 06 00 06 00
+>3e092c		06 00 06 00 06 00 1f 00 06 00 05 00 19 00 2d 00
+>3e093c		2d 00 1e 00 48 00
+>3e0942		19 00 1a 00 1b 00 1c 00		TEXT_POSY  .word  25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 37, 38, 39, 40, 46, 48, 52, 52, 52, 53, 57, 57
+>3e094a		1d 00 1e 00 1f 00 20 00 21 00 22 00 23 00 25 00
+>3e095a		26 00 27 00 28 00 2e 00 30 00 34 00 34 00 34 00
+>3e096a		35 00 39 00 39 00
+=6						leftAlign = 6
+>3e0970		43 4f 4d 50 55 54 45 52		LINE0  .text "COMPUTER MODEL:                 ", $00 ; Offset $10
+>3e0978		20 4d 4f 44 45 4c 3a 20 20 20 20 20 20 20 20 20
+>3e0988		20 20 20 20 20 20 20 20 00
+>3e0991		20 20 20 20 20 20 20 20		LINE1  .text "                     ", $00
+>3e0999		20 20 20 20 20 20 20 20 20 20 20 20 20 00
+>3e09a7		53 59 53 54 45 4d 20 49		LINE2  .text "SYSTEM INFO: ", $00
+>3e09af		4e 46 4f 3a 20 00
+>3e09b5		43 50 55 3a 20 57 44 43		LINE3  .text "CPU: WDC65C816 @ 14MHZ ", $00
+>3e09bd		36 35 43 38 31 36 20 40 20 31 34 4d 48 5a 20 00
+>3e09cd		43 4f 44 45 20 4d 45 4d		LINE4  .text "CODE MEMORY SIZE:                 ", $00 ; Offset 17
+>3e09d5		4f 52 59 20 53 49 5a 45 3a 20 20 20 20 20 20 20
+>3e09e5		20 20 20 20 20 20 20 20 20 20 00
+>3e09f0		56 49 44 45 4f 20 4d 45		LINE5  .text "VIDEO MEMORY SIZE:                 ", $00 ; Offset
+>3e09f8		4d 4f 52 59 20 53 49 5a 45 3a 20 20 20 20 20 20
+>3e0a08		20 20 20 20 20 20 20 20 20 20 20 00
+>3e0a14		50 43 42 20 52 45 56 49		LINE6  .text "PCB REVISION:       ", $00
+>3e0a1c		53 49 4f 4e 3a 20 20 20 20 20 20 20 00
+>3e0a29		43 48 49 50 53 45 54 28		LINE7  .text "CHIPSET(S): ", $00
+>3e0a31		53 29 3a 20 00
+>3e0a36		50 4e 3a 20 43 46 50 39		LINE8  .text "PN: CFP95169 - FAT VICKY II - REV:0000 SUBREV:0000 DATE:00/00/00 ", $00
+>3e0a3e		35 31 36 39 20 2d 20 46 41 54 20 56 49 43 4b 59
+>3e0a4e		20 49 49 20 2d 20 52 45 56 3a 30 30 30 30 20 53
+>3e0a5e		55 42 52 45 56 3a 30 30 30 30 20 44 41 54 45 3a
+>3e0a6e		30 30 2f 30 30 2f 30 30 20 00
+>3e0a78		50 4e 3a 20 43 46 50 39		LINE9  .text "PN: CFP9533 - GABE - REV:0000 SUBREV:0000 DATE:00/00/00          ", $00
+>3e0a80		35 33 33 20 2d 20 47 41 42 45 20 2d 20 52 45 56
+>3e0a90		3a 30 30 30 30 20 53 55 42 52 45 56 3a 30 30 30
+>3e0aa0		30 20 44 41 54 45 3a 30 30 2f 30 30 2f 30 30 20
+>3e0ab0		20 20 20 20 20 20 20 20 20 00
+>3e0aba		50 4e 3a 20 43 46 50 39		LINE10 .text "PN: CFP9551 - VICKY II - REV:0000 SUBREV:0000 DATE:00/00/00      ", $00
+>3e0ac2		35 35 31 20 2d 20 56 49 43 4b 59 20 49 49 20 2d
+>3e0ad2		20 52 45 56 3a 30 30 30 30 20 53 55 42 52 45 56
+>3e0ae2		3a 30 30 30 30 20 44 41 54 45 3a 30 30 2f 30 30
+>3e0af2		2f 30 30 20 20 20 20 20 20 00
+>3e0afc		43 52 45 44 49 54 53 3a		LINE11 .text "CREDITS: ", $00
+>3e0b04		20 00
+>3e0b06		43 4f 4e 43 45 50 54 20		LINE12 .text "CONCEPT & SYSTEM DESIGN: STEFANY ALLAIRE", $00
+>3e0b0e		26 20 53 59 53 54 45 4d 20 44 45 53 49 47 4e 3a
+>3e0b1e		20 53 54 45 46 41 4e 59 20 41 4c 4c 41 49 52 45
+>3e0b2e		00
+>3e0b2f		4b 45 52 4e 45 4c 20 44		LINE13 .text "KERNEL DESIGN / BASIC816 CREATOR: PETER J. WEINGARTNER", $00
+>3e0b37		45 53 49 47 4e 20 2f 20 42 41 53 49 43 38 31 36
+>3e0b47		20 43 52 45 41 54 4f 52 3a 20 50 45 54 45 52 20
+>3e0b57		4a 2e 20 57 45 49 4e 47 41 52 54 4e 45 52 00
+>3e0b66		46 4f 45 4e 49 58 20 49		LINE14 .text "FOENIX IDE DESIGN: DANIEL TREMBLAY", $00
+>3e0b6e		44 45 20 44 45 53 49 47 4e 3a 20 44 41 4e 49 45
+>3e0b7e		4c 20 54 52 45 4d 42 4c 41 59 00
+>3e0b89		2d 2d 2d 2d 42 4f 4f 54		LINE15 .text "----BOOT MENU----", $00
+>3e0b91		20 4d 45 4e 55 2d 2d 2d 2d 00
+>3e0b9b		20 50 52 45 53 53 20 46		LINE16 .text " PRESS F2 = SDCARD, F3 = HDD, RETURN = BASIC, SPACE = DEFAULT ", $00
+>3e0ba3		32 20 3d 20 53 44 43 41 52 44 2c 20 46 33 20 3d
+>3e0bb3		20 48 44 44 2c 20 52 45 54 55 52 4e 20 3d 20 42
+>3e0bc3		41 53 49 43 2c 20 53 50 41 43 45 20 3d 20 44 45
+>3e0bd3		46 41 55 4c 54 20 00
+>3e0bda		48 49 2d 52 45 53 20 4d		LINE17 .text "HI-RES MODE: OFF ", $00
+>3e0be2		4f 44 45 3a 20 4f 46 46 20 00
+>3e0bec		48 44 44 20 49 4e 53 54		LINE18 .text "HDD INSTALLED: -- ", $00
+>3e0bf4		41 4c 4c 45 44 3a 20 2d 2d 20 00
+>3e0bff		45 58 50 41 4e 53 49 4f		LINE19 .text "EXPANSION CARD INSTALLED: NO ", $00
+>3e0c07		4e 20 43 41 52 44 20 49 4e 53 54 41 4c 4c 45 44
+>3e0c17		3a 20 4e 4f 20 00
+>3e0c1d		20 20 20 20 00 00 00 00		LINE20 .text $20, $20, $20, $20, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00
+>3e0c25		00 00 00 00 00 00 00 00 00
+>3e0c2e		57 57 57 2e 43 32 35 36		LINE21 .text "WWW.C256FOENIX.COM", $00
+>3e0c36		46 4f 45 4e 49 58 2e 43 4f 4d 00
+>3e0c41		20 00				LINE22 .text " ", $00
+>3e0c43		53 0c 3e 00 63 0c 3e 00		MODEL_TABLE .dword MODEL_00, MODEL_01, MODEL_02, MODEL_03
+>3e0c4b		73 0c 3e 00 83 0c 3e 00
+>3e0c53		a3 0c 3e 00 e3 0c 3e 00		MODEL_00   .dword FIELD_MOD0, FIELD_MEM1, FIELD_MEM1, $00000000 ; FMX
+>3e0c5b		e3 0c 3e 00 00 00 00 00
+>3e0c63		b3 0c 3e 00 e3 0c 3e 00		MODEL_01   .dword FIELD_MOD1, FIELD_MEM1, FIELD_MEM0, $00000000 ; U+
+>3e0c6b		d3 0c 3e 00 00 00 00 00
+>3e0c73		c3 0c 3e 00 d3 0c 3e 00		MODEL_02   .dword FIELD_MOD2, FIELD_MEM0, FIELD_MEM0, $00000000 ; U
+>3e0c7b		d3 0c 3e 00 00 00 00 00
+>3e0c83		00 00 00 00 00 00 00 00		MODEL_03   .dword  $00000000,  $00000000, $00000000, $00000000  ; TBD
+>3e0c8b		00 00 00 00 00 00 00 00
+>3e0c93		80 09 3e 00 df 09 3e 00		LINE_MOD   .dword LINE0 + $10, LINE4 + $12, LINE5 + $13, LINE6 + $0E
+>3e0c9b		03 0a 3e 00 22 0a 3e 00
+>3e0ca3		43 32 35 36 20 46 4f 45		FIELD_MOD0 .text "C256 FOENIX FMX", $00 ; 15 Characters
+>3e0cab		4e 49 58 20 46 4d 58 00
+>3e0cb3		43 32 35 36 20 46 4f 45		FIELD_MOD1 .text "C256 FOENIX U+ ", $00
+>3e0cbb		4e 49 58 20 55 2b 20 00
+>3e0cc3		43 32 35 36 20 46 4f 45		FIELD_MOD2 .text "C256 FOENIX U  ", $00
+>3e0ccb		4e 49 58 20 55 20 20 00
+>3e0cd3		32 2c 30 39 37 2c 31 35		FIELD_MEM0 .text "2,097,152 BYTES", $00
+>3e0cdb		32 20 42 59 54 45 53 00
+>3e0ce3		34 2c 31 39 34 2c 33 30		FIELD_MEM1 .text "4,194,304 BYTES", $00
+>3e0ceb		34 20 42 59 54 45 53 00
+>3e0cf3		4f 4e 20 00			ON_TEXT    .text "ON ", $00
+>3e0cf7		59 45 53 00			YES_TEXT   .text "YES", $00
+
+;******  Return to file: src\kernel.asm
+
+>3e0cfb						.align 256
+.3e0d00						SS_MONIKER_LUT
+>3e0d00		00 00 00 00 aa aa 00 00		.binary "SplashScreenCode/Graphics Assets/Graphic_C256Foenix.data.pal"
+>3e0d08		00 aa 00 00 aa aa 00 00 00 00 aa 00 aa 00 aa 00
+>3e0d18		00 55 aa 00 aa aa aa 00 55 55 55 00 ff 55 55 00
+>3e0d28		55 ff 55 00 ff ff 55 00 55 55 ff 00 ff 55 ff 00
+>3e0d38		55 ff ff 00 ff ff ff 00 00 00 00 00 10 10 10 00
+>3e0d48		20 20 20 00 35 35 35 00 45 45 45 00 55 55 55 00
+>3e0d58		65 65 65 00 75 75 75 00 8a 8a 8a 00 9a 9a 9a 00
+>3e0d68		aa aa aa 00 ba ba ba 00 ca ca ca 00 df df df 00
+>3e0d78		ef ef ef 00 ff ff ff 00 ff 00 00 00 ff 00 41 00
+>3e0d88		ff 00 82 00 ff 00 be 00 ff 00 ff 00 be 00 ff 00
+>3e0d98		82 00 ff 00 41 00 ff 00 00 00 ff 00 00 41 ff 00
+>3e0da8		00 82 ff 00 00 be ff 00 00 ff ff 00 00 ff be 00
+>3e0db8		00 ff 82 00 00 ff 41 00 00 ff 00 00 41 ff 00 00
+>3e0dc8		82 ff 00 00 be ff 00 00 ff ff 00 00 ff be 00 00
+>3e0dd8		ff 82 00 00 ff 41 00 00 ff 82 82 00 ff 82 9e 00
+>3e0de8		ff 82 be 00 ff 82 df 00 ff 82 ff 00 df 82 ff 00
+>3e0df8		be 82 ff 00 9e 82 ff 00 82 82 ff 00 82 9e ff 00
+>3e0e08		82 be ff 00 82 df ff 00 82 ff ff 00 82 ff df 00
+>3e0e18		82 ff be 00 82 ff 9e 00 82 ff 82 00 9e ff 82 00
+>3e0e28		be ff 82 00 df ff 82 00 ff ff 82 00 ff df 82 00
+>3e0e38		ff be 82 00 ff 9e 82 00 ff ba ba 00 ff ba ca 00
+>3e0e48		ff ba df 00 ff ba ef 00 ff ba ff 00 ef ba ff 00
+>3e0e58		df ba ff 00 ca ba ff 00 ba ba ff 00 ba ca ff 00
+>3e0e68		ba df ff 00 ba ef ff 00 ba ff ff 00 ba ff ef 00
+>3e0e78		ba ff df 00 ba ff ca 00 ba ff ba 00 ca ff ba 00
+>3e0e88		df ff ba 00 ef ff ba 00 ff ff ba 00 ff ef ba 00
+>3e0e98		ff df ba 00 ff ca ba 00 71 00 00 00 71 00 1c 00
+>3e0ea8		71 00 39 00 71 00 55 00 71 00 71 00 55 00 71 00
+>3e0eb8		39 00 71 00 1c 00 71 00 00 00 71 00 00 1c 71 00
+>3e0ec8		00 39 71 00 00 55 71 00 00 71 71 00 00 71 55 00
+>3e0ed8		00 71 39 00 00 71 1c 00 00 71 00 00 1c 71 00 00
+>3e0ee8		39 71 00 00 55 71 00 00 71 71 00 00 71 55 00 00
+>3e0ef8		71 39 00 00 71 1c 00 00 71 39 39 00 71 39 45 00
+>3e0f08		71 39 55 00 71 39 61 00 71 39 71 00 61 39 71 00
+>3e0f18		55 39 71 00 45 39 71 00 39 39 71 00 39 45 71 00
+>3e0f28		39 55 71 00 39 61 71 00 39 71 71 00 39 71 61 00
+>3e0f38		39 71 55 00 39 71 45 00 39 71 39 00 45 71 39 00
+>3e0f48		55 71 39 00 61 71 39 00 71 71 39 00 71 61 39 00
+>3e0f58		71 55 39 00 71 45 39 00 71 51 51 00 71 51 59 00
+>3e0f68		71 51 61 00 71 51 69 00 71 51 71 00 69 51 71 00
+>3e0f78		61 51 71 00 59 51 71 00 51 51 71 00 51 59 71 00
+>3e0f88		51 61 71 00 51 69 71 00 51 71 71 00 51 71 69 00
+>3e0f98		51 71 61 00 51 71 59 00 51 71 51 00 59 71 51 00
+>3e0fa8		61 71 51 00 69 71 51 00 71 71 51 00 71 69 51 00
+>3e0fb8		71 61 51 00 71 59 51 00 41 00 00 00 41 00 10 00
+>3e0fc8		41 00 20 00 41 00 31 00 41 00 41 00 31 00 41 00
+>3e0fd8		20 00 41 00 10 00 41 00 00 00 41 00 00 10 41 00
+>3e0fe8		00 20 41 00 00 31 41 00 00 41 41 00 00 41 31 00
+>3e0ff8		00 41 20 00 00 41 10 00 00 41 00 00 10 41 00 00
+>3e1008		20 41 00 00 31 41 00 00 41 41 00 00 41 31 00 00
+>3e1018		41 20 00 00 41 10 00 00 41 20 20 00 41 20 28 00
+>3e1028		41 20 31 00 41 20 39 00 41 20 41 00 39 20 41 00
+>3e1038		31 20 41 00 28 20 41 00 20 20 41 00 20 28 41 00
+>3e1048		20 31 41 00 20 39 41 00 20 41 41 00 20 41 39 00
+>3e1058		20 41 31 00 20 41 28 00 20 41 20 00 28 41 20 00
+>3e1068		31 41 20 00 39 41 20 00 41 41 20 00 41 39 20 00
+>3e1078		41 31 20 00 41 28 20 00 41 2d 2d 00 41 2d 31 00
+>3e1088		41 2d 35 00 41 2d 3d 00 41 2d 41 00 3d 2d 41 00
+>3e1098		35 2d 41 00 31 2d 41 00 2d 2d 41 00 2d 31 41 00
+>3e10a8		2d 35 41 00 2d 3d 41 00 2d 41 41 00 2d 41 3d 00
+>3e10b8		2d 41 35 00 2d 41 31 00 2d 41 2d 00 31 41 2d 00
+>3e10c8		35 41 2d 00 3d 41 2d 00 41 41 2d 00 41 3d 2d 00
+>3e10d8		41 35 2d 00 41 31 2d 00 18 18 e7 00 00 ff ff 00
+>3e10e8		00 ff 00 00 ff 00 00 00 ff 00 ff 00 ff ff 00 00
+>3e10f8		ff ff ff 00 e5 80 80 00
+.3e1100						SS_MONIKER
+>3e1100		00 00 00 00 00 00 00 00		.binary "SplashScreenCode/Graphics Assets/Graphic_C256Foenix.data"
+>3e1108		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 95 times (1520 bytes)...
+>3e1708		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e1718		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e1728		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1848		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 ff
+>3e1858		ff 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e1868		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1988		00 00 00 00 00 00 00 00 00 00 00 00 00 01 ff ff
+>3e1998		ff ff ff ff 01 01 00 00 00 00 00 00 00 00 00 00
+>3e19a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1ac8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 ff ff
+>3e1ad8		ff ff ff ff ff ff 01 00 00 00 00 00 00 00 00 00
+>3e1ae8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1c08		00 00 00 00 00 00 00 00 00 00 00 00 01 ff ff ff
+>3e1c18		ff ff ff ff ff ff ff 01 00 00 00 00 00 00 00 00
+>3e1c28		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1d48		00 00 00 00 00 00 00 00 00 00 00 00 01 ff ff ff
+>3e1d58		ff ff ff ff ff ff 01 00 00 00 00 00 00 00 00 00
+>3e1d68		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1e88		00 00 00 00 00 00 00 00 00 00 00 01 ff ff ff ff
+>3e1e98		ff ff ff ff ff ff 01 00 00 00 00 00 00 00 00 00
+>3e1ea8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3e1fc8		00 00 00 00 00 00 00 00 00 00 00 01 ff ff ff ff
+>3e1fd8		ff ff ff ff ff 01 00 00 00 00 00 00 00 00 00 00
+>3e1fe8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e2028		00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00
+>3e2038		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 12 times (192 bytes)...
+>3e2108		00 01 00 00 00 00 00 00 00 00 00 00 01 01 ff ff
+>3e2118		ff ff ff ff ff 01 00 00 00 00 00 00 00 00 00 00
+>3e2128		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e2168		00 00 00 01 01 01 00 00 00 00 00 00 00 00 00 00
+>3e2178		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 12 times (192 bytes)...
+>3e2248		01 01 00 00 00 00 00 00 00 00 00 00 00 00 01 01
+>3e2258		01 01 fe fe 01 00 00 00 00 00 00 00 00 00 00 00
+>3e2268		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e22a8		00 00 01 fe 01 00 00 00 00 00 00 00 00 00 00 00
+>3e22b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 11 times (176 bytes)...
+>3e2378		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e2388		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e2398		00 01 fe fe 01 00 00 00 00 00 00 00 00 00 00 00
+>3e23a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e23e8		00 01 fe 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e23f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 11 times (176 bytes)...
+>3e24b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e24c8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e24d8		00 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e24e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e2528		01 fe fe 01 00 01 00 00 00 00 00 00 00 00 00 00
+>3e2538		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e2548		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e2558		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e2568		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e2578		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 7 times (112 bytes)...
+>3e25f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fe
+>3e2608		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e2618		00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
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+;		...repeated 4 times (64 bytes)...
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+;		...repeated 2 times (32 bytes)...
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+>3e49c8		00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 01 00
+>3e49d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e49e8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e49f8		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 01 f9
+>3e4a08		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4a18		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4a28		f9 f9 f9 f9 01 00 00 00 00 00 00 00 01 f9 f9 f9
+>3e4a38		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 01 f9 f9
+>3e4a48		f9 f9 f9 f9 f9 f9 01 00 00 00 01 f9 f9 f9 f9 f9
+>3e4a58		f9 f9 f9 f9 f9 f9 01 01 00 00 01 f9 f9 f9 f9 f9
+>3e4a68		f9 f9 f9 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4a78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e4a88		f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00
+>3e4a98		00 01 01 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4aa8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+;		...repeated 2 times (32 bytes)...
+>3e4ad8		01 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4ae8		01 01 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00
+>3e4af8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4b08		00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 01 00 00
+>3e4b18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e4b28		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4b38		f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00 01 f9
+>3e4b48		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4b58		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4b68		f9 f9 f9 f9 01 00 00 00 00 00 00 00 01 f9 f9 f9
+>3e4b78		f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 01 f9 f9 f9
+>3e4b88		f9 f9 f9 f9 f9 01 00 00 00 01 f9 f9 f9 f9 f9 f9
+>3e4b98		f9 f9 f9 f9 f9 01 00 00 00 00 00 01 f9 f9 f9 f9
+>3e4ba8		f9 01 f9 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4bb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e4bc8		f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 01 01
+>3e4bd8		01 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4be8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4bf8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4c08		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01
+>3e4c18		00 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4c28		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00
+>3e4c38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4c48		00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00
+>3e4c58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4c68		01 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4c78		f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00 01 f9 f9
+>3e4c88		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4c98		f9 f9 f9 f9 f9 f9 f9 01 01 01 f9 f9 f9 f9 f9 f9
+>3e4ca8		f9 f9 f9 01 00 00 00 00 00 00 00 00 00 01 f9 f9
+>3e4cb8		f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 01 f9 f9 f9
+>3e4cc8		f9 f9 f9 f9 01 00 00 00 01 f9 f9 f9 f9 f9 f9 f9
+>3e4cd8		f9 f9 f9 f9 01 01 00 00 00 00 00 01 f9 f9 f9 f9
+>3e4ce8		01 00 01 f9 01 00 00 00 00 00 00 00 00 00 00 00
+>3e4cf8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e4d08		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 01 01 01 f9 f9
+>3e4d18		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 f9 f9 f9 f9
+>3e4d28		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4d38		f9 f9 f9 01 f9 01 01 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4d48		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 01 00
+>3e4d58		00 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4d68		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 01 00 00 00
+>3e4d78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4d88		00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 01 00 00 00
+>3e4d98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4da8		00 01 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4db8		f9 f9 f9 01 01 00 00 00 00 00 00 00 00 01 f9 f9
+>3e4dc8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3e4dd8		f9 f9 f9 01 01 01 01 00 00 00 01 f9 f9 f9 f9 f9
+>3e4de8		f9 f9 f9 01 00 00 00 00 00 00 00 00 00 01 f9 f9
+>3e4df8		f9 f9 f9 f9 f9 01 00 00 00 00 00 00 01 f9 f9 f9
+>3e4e08		f9 f9 f9 01 01 00 00 00 01 f9 f9 f9 f9 f9 f9 f9
+>3e4e18		f9 f9 f9 01 00 00 00 00 00 00 00 00 01 f9 f9 f9
+>3e4e28		f9 01 00 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3e4e38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e4e48		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4e58		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01 00 01 f8 f8 f8
+>3e4e68		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4e78		f8 f8 01 00 01 00 00 01 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4e88		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01 01 01 00 00 00
+>3e4e98		00 00 00 00 00 00 00 01 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4ea8		f8 f8 f8 f8 f8 f8 f8 f8 f8 01 01 00 00 00 00 00
+>3e4eb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4ec8		00 00 00 00 01 f8 f8 f8 f8 f8 f8 01 00 00 00 00
+>3e4ed8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4ee8		00 01 01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4ef8		f8 01 01 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
+>3e4f08		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01
+>3e4f18		01 01 01 00 00 00 00 00 00 00 01 f8 f8 f8 f8 f8
+>3e4f28		01 01 01 00 00 00 00 00 00 00 00 00 00 01 f8 f8
+>3e4f38		f8 f8 f8 f8 f8 01 00 00 00 00 00 01 f8 f8 f8 f8
+>3e4f48		f8 f8 01 00 01 00 00 01 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4f58		f8 f8 01 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
+>3e4f68		f8 01 00 00 01 00 00 00 00 00 00 00 00 00 00 00
+>3e4f78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e4f88		01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4f98		f8 f8 f8 f8 f8 f8 f8 f8 01 01 00 01 01 f8 f8 f8
+>3e4fa8		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01 01 01
+>3e4fb8		01 f8 f8 01 f8 01 01 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4fc8		f8 f8 f8 f8 f8 01 f8 f8 01 01 00 00 00 00 00 00
+>3e4fd8		00 00 00 00 00 00 00 01 f8 f8 f8 f8 f8 f8 f8 f8
+>3e4fe8		f8 f8 f8 f8 f8 f8 f8 01 01 00 00 00 00 00 00 00
+>3e4ff8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5008		00 00 00 01 f8 f8 f8 f8 f8 f8 01 00 00 00 00 00
+>3e5018		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5028		00 00 00 01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01
+>3e5038		01 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
+>3e5048		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01 01 01 01 00
+>3e5058		00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8 f8 01
+>3e5068		00 00 01 00 00 00 00 00 00 00 00 00 00 01 01 f8
+>3e5078		f8 f8 f8 f8 01 00 00 00 00 00 00 01 f8 01 f8 01
+>3e5088		01 01 00 00 00 00 00 01 f8 f8 01 f8 f8 01 f8 f8
+>3e5098		f8 01 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8
+>3e50a8		f8 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e50b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e50c8		01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e50d8		f8 f8 f8 f8 f8 f8 f8 01 00 00 00 00 00 01 f8 f8
+>3e50e8		f8 f8 f8 f8 f8 f8 f8 f8 01 01 01 01 01 00 00 00
+>3e50f8		00 01 01 01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e5108		f8 f8 f8 f8 01 00 01 01 00 00 00 00 00 00 00 00
+>3e5118		00 00 00 00 00 00 00 00 01 01 f8 f8 f8 f8 f8 f8
+>3e5128		f8 f8 f8 01 01 01 01 00 00 00 00 00 00 00 00 00
+>3e5138		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5148		00 00 00 01 f8 f8 f8 f8 f8 f8 01 00 00 00 00 00
+>3e5158		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5168		00 00 00 00 01 01 01 01 f8 f8 01 01 01 01 01 00
+>3e5178		00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8
+>3e5188		f8 f8 f8 f8 f8 f8 f8 01 01 01 01 00 00 00 00 00
+>3e5198		00 00 00 00 00 00 00 00 00 01 f8 f8 f8 f8 f8 01
+>3e51a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e51b8		f8 f8 f8 f8 01 00 00 00 00 00 01 f8 01 00 01 00
+>3e51c8		00 00 00 00 00 00 01 f8 f8 01 00 01 01 00 01 f8
+>3e51d8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8
+>3e51e8		f8 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e51f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5208		01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e5218		f8 f8 f8 f8 01 01 01 00 00 00 00 00 00 00 01 01
+>3e5228		01 f8 f8 f8 f8 01 01 01 00 00 00 00 00 00 00 00
+>3e5238		00 00 00 00 01 01 01 01 01 01 01 01 01 01 01 01
+>3e5248		01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5258		00 00 00 00 00 00 00 00 00 00 01 01 01 01 f8 01
+>3e5268		01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5278		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5288		00 00 01 f8 f8 f8 f8 f8 f8 01 00 00 00 00 00 00
+>3e5298		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e52a8		00 00 00 00 00 00 00 00 01 01 00 00 00 00 00 00
+>3e52b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01
+>3e52c8		f8 f8 f8 01 01 01 01 00 00 00 00 00 00 00 00 00
+>3e52d8		00 00 00 00 00 00 00 00 00 01 f8 f8 01 f8 01 00
+>3e52e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e52f8		01 01 01 01 00 00 00 00 00 00 01 01 00 00 01 00
+>3e5308		00 00 00 00 00 00 01 f8 01 00 00 00 00 00 01 01
+>3e5318		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8
+>3e5328		01 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5338		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5348		00 01 01 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3e5358		f8 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5368		00 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3e5378		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5388		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5398		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00
+>3e53a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e53b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e53c8		00 00 01 f8 f8 f8 f8 f8 01 00 00 00 00 00 00 00
+>3e53d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e5408		01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5418		00 00 00 00 00 00 00 00 00 01 f8 01 00 01 00 00
+>3e5428		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5438		00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00
+>3e5448		00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 00
+>3e5458		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e5468		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5478		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5488		00 00 00 01 01 01 f8 f8 f8 f8 f8 f8 f8 f8 01 01
+>3e5498		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e54a8		00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e54b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e5508		00 00 01 f8 f8 01 f8 01 00 00 00 00 00 00 00 00
+>3e5518		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e5558		00 00 00 00 00 00 00 00 01 f8 01 00 00 01 00 00
+>3e5568		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5578		00 00 00 00 00 00 00 00 00 01 01 00 00 00 00 00
+>3e5588		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5598		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e55a8		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e55b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e55c8		00 00 00 00 00 01 01 01 01 01 01 01 01 01 00 00
+>3e55d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 6 times (96 bytes)...
+>3e5648		00 01 f8 f8 01 00 01 01 00 00 00 00 00 00 00 00
+>3e5658		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e5698		00 00 00 00 00 00 00 00 01 01 00 00 00 00 00 00
+>3e56a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e56b8		00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00
+>3e56c8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e56d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e56e8		00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e56f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e5788		00 01 f8 01 01 00 01 00 00 00 00 00 00 00 00 00
+>3e5798		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e57d8		00 00 00 00 00 00 00 00 01 00 00 00 00 00 00 00
+>3e57e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e5828		00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5838		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e58c8		00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e58d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e5918		00 00 00 00 00 00 00 01 01 00 00 00 00 00 00 00
+>3e5928		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 13 times (208 bytes)...
+>3e5a08		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5a18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 18 times (288 bytes)...
+>3e5b48		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e5b58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 89 times (1424 bytes)...
+>3e60f8		00 00 00 00 00 00 00 00
+.3e6100						SS_FMX_TXT
+>3e6100		00 00 00 00 00 00 00 00		.binary "SplashScreenCode/Graphics Assets/Graphic_FMX.data"
+>3e6108		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 42 times (672 bytes)...
+>3e63b8		00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00
+>3e63c8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e6458		00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00
+>3e6468		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e64f8		00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 00
+>3e6508		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e6598		00 00 00 00 00 00 00 00 00 01 01 00 00 00 00 00
+>3e65a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e65f8		00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00
+>3e6608		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e6638		00 00 00 00 00 00 00 00 00 01 01 00 00 00 00 00
+>3e6648		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e6698		00 00 01 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3e66a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e66d8		00 00 00 00 00 00 00 00 00 00 01 01 00 01 01 00
+>3e66e8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e66f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e6728		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e6738		01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e6748		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e6778		00 00 00 00 00 00 00 00 00 00 01 01 00 01 01 00
+>3e6788		00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e6798		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e67c8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 ff
+>3e67d8		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e67e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e6818		00 00 00 00 00 00 00 00 00 00 01 ff 01 ff ff 01
+>3e6828		00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e6838		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e6868		00 00 00 00 00 00 00 00 00 00 00 00 01 01 ff 01
+>3e6878		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e68b8		00 00 00 00 00 00 00 00 00 00 01 ff ff ff ff ff
+>3e68c8		01 ff 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e68d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e6908		00 00 00 00 00 00 00 00 00 00 01 01 ff ff ff 01
+>3e6918		00 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e6928		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8868		00 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 01 00 00
+>3e8878		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e88a8		00 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 01
+>3e88b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e88d8		00 00 00 00 00 00 00 01 f9 f9 f9 f9 f9 01 00 01
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+>3e8908		00 00 00 00 00 01 f9 f9 f9 f9 01 00 01 01 00 00
+>3e8918		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e8948		00 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 f9 f9 01
+>3e8958		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e89a8		00 00 00 00 00 01 f9 f9 f9 01 00 01 01 00 00 00
+>3e89b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e89e8		00 00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 01 01 00
+>3e89f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8a48		00 00 00 00 00 01 f8 01 01 00 00 01 00 00 00 00
+>3e8a58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e8a88		00 00 00 00 00 01 f9 f9 f9 f9 f9 f9 01 00 00 00
+>3e8a98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8ae8		00 00 00 00 01 f8 01 00 00 00 00 01 00 00 00 00
+>3e8af8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e8b28		00 00 00 00 00 01 f8 f8 f8 f8 f8 f8 01 00 00 00
+>3e8b38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8b88		00 00 00 00 01 f8 01 00 00 00 01 00 00 00 00 00
+>3e8b98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e8bc8		00 00 00 00 00 01 f8 f8 f8 f8 f8 01 00 00 00 00
+>3e8bd8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8c28		00 00 00 00 01 01 00 00 00 00 00 00 00 00 00 00
+>3e8c38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e8c68		00 00 00 00 01 f8 f8 f8 f8 f8 f8 01 00 00 00 00
+>3e8c78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8cc8		00 00 00 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3e8cd8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e8d08		00 00 00 00 01 f8 f8 f8 f8 f8 01 00 00 00 00 00
+>3e8d18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8d38		00 00 00 00 00 00 00 00 00 00 00 01 f8 01 00 00
+>3e8d48		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 5 times (80 bytes)...
+>3e8da8		00 00 00 00 01 f8 f8 f8 01 01 00 00 00 00 00 00
+>3e8db8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+>3e8dd8		00 00 00 00 00 00 00 00 00 00 00 00 01 01 00 00
+>3e8de8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 5 times (80 bytes)...
+>3e8e48		00 00 00 00 01 f8 f8 01 00 01 00 00 00 00 00 00
+>3e8e58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8e68		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8e78		00 00 00 00 00 00 00 00 00 00 00 00 00 01 01 00
+>3e8e88		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 5 times (80 bytes)...
+>3e8ee8		00 00 00 01 f8 f8 01 01 00 00 00 00 00 00 00 00
+>3e8ef8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8f08		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8f18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01
+>3e8f28		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 5 times (80 bytes)...
+>3e8f88		00 00 00 01 f8 01 00 00 00 00 00 00 00 00 00 00
+>3e8f98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8fa8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8fb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e8fc8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e8fd8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e9028		00 00 00 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3e9038		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e90c8		00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e90d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 8 times (128 bytes)...
+>3e9168		00 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9178		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 23 times (368 bytes)...
+>3e92f8		00 00 00 00 00 00 00 00
+.3e9300						SS_UPlus_TXT
+>3e9300		00 00 00 00 00 00 00 00		.binary "SplashScreenCode/Graphics Assets/Graphic_UPlus.data"
+>3e9308		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 14 times (224 bytes)...
+>3e93f8		00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9408		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e9458		00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9468		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e94b8		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e94c8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e9508		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e9518		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9528		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e9568		00 00 00 00 00 00 01 01 00 00 00 00 00 00 00 01
+>3e9578		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9588		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 3 times (48 bytes)...
+>3e95c8		00 00 00 00 00 00 01 00 00 00 00 00 00 00 01 01
+>3e95d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e9628		00 00 00 00 00 01 01 00 00 00 01 01 01 01 fe 01
+>3e9638		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e9688		00 00 00 00 01 fe 01 00 00 00 01 fe fe fe fe 01
+>3e9698		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e96e8		00 00 00 00 01 fe 01 00 00 01 fe fe fe fe 01 00
+>3e96f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e9748		00 00 00 01 fd fd 01 00 01 fd fd fd fd fd 01 00
+>3e9758		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 4 times (64 bytes)...
+>3e97a8		00 00 01 fd fd fd fd 01 fd fd fd fd fd fd 01 00
+>3e97b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e97e8		00 00 00 00 00 00 00 00 00 00 00 01 01 01 00 00
+>3e97f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9808		00 00 01 fd fd fd fd fd fd fd fd fd fd 01 00 00
+>3e9818		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e9848		00 00 00 00 00 00 00 00 00 00 01 fd fd fd 01 00
+>3e9858		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9868		00 01 fd fd fd fd fd fd fd fd fd fd fd 01 00 00
+>3e9878		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3e98a8		00 00 00 00 00 00 00 00 00 01 fd fd fd fd fd 01
+>3e98b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e98c8		00 01 fd fd fd fd fd fd fd fd fd fd 01 00 00 00
+>3e98d8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00
+>3e98e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e98f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9908		00 00 00 00 00 00 00 01 01 fd fd fd fd fd fd fd
+>3e9918		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9928		01 fd fd fd fd fd fd fd fd fd fd fd 01 00 00 00
+>3e9938		00 00 00 00 00 00 00 00 00 00 00 00 01 01 00 00
+>3e9948		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9958		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9968		00 00 00 00 00 00 01 fd fd fd fd fd fd fd fd fd
+>3e9978		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e9988		fd fd fd fd fd fd fd fd fd fd fd 01 00 00 00 00
+>3e9998		00 00 00 00 00 00 00 00 00 00 00 01 fd 01 00 00
+>3e99a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e99b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e99c8		00 00 00 00 00 00 01 fd fd fd fd fd fd fd fd fd
+>3e99d8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e99e8		fd fd fd fd fd fd fd fd fd fd fd 01 00 00 00 00
+>3e99f8		00 00 00 00 00 00 00 00 00 00 01 fd fd fd 01 01
+>3e9a08		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9a18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9a28		00 00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc
+>3e9a38		01 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fc
+>3e9a48		fc fc fc fc fc fc fc fc fc fc 01 00 00 00 00 00
+>3e9a58		00 00 00 00 00 00 00 00 00 01 fc fc fc fc fc fc
+>3e9a68		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9a78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9a88		00 00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc
+>3e9a98		01 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fc
+>3e9aa8		fc fc fc fc fc fc fc fc fc fc 01 00 00 00 00 00
+>3e9ab8		00 00 00 00 00 00 00 00 01 fc fc fc fc fc fc fc
+>3e9ac8		fc 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9ad8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9ae8		00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc fc
+>3e9af8		01 00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc
+>3e9b08		fc fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00
+>3e9b18		00 00 00 00 00 00 00 01 fc fc fc fc fc fc fc fc
+>3e9b28		fc 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9b38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9b48		00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc 01
+>3e9b58		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc
+>3e9b68		fc fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00
+>3e9b78		00 00 00 00 00 00 00 01 fc fc fc fc fc fc fc fc
+>3e9b88		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9b98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9ba8		00 00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01
+>3e9bb8		00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc
+>3e9bc8		fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00
+>3e9bd8		00 00 00 00 00 00 01 fc fc fc fc fc fc fc fc 01
+>3e9be8		00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9bf8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9c08		00 00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01
+>3e9c18		00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc
+>3e9c28		fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00
+>3e9c38		00 00 00 00 00 00 01 fc fc fc fc fc fc fc fc fc
+>3e9c48		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9c58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9c68		00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01 00
+>3e9c78		00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc fc
+>3e9c88		fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00 00
+>3e9c98		00 00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc
+>3e9ca8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9cb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9cc8		00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01 00
+>3e9cd8		00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc fc
+>3e9ce8		fc fc fc fc fc fc 01 00 00 00 00 00 00 00 00 00
+>3e9cf8		00 00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc
+>3e9d08		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9d18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9d28		00 01 fb fb fb fb fb fb fb fb fb fb fb 01 00 00
+>3e9d38		00 00 00 00 00 00 00 00 00 00 01 fb fb fb fb fb
+>3e9d48		fb fb fb fb fb fb 01 00 00 00 00 00 00 00 00 00
+>3e9d58		00 00 00 00 01 fb fb fb fb fb fb fb fb fb fb 01
+>3e9d68		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9d78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9d88		00 01 fb fb fb fb fb fb fb fb fb fb fb 01 00 00
+>3e9d98		00 00 00 00 00 00 00 00 00 01 fb fb fb fb fb fb
+>3e9da8		fb fb fb fb fb 01 00 00 00 00 00 00 00 00 00 00
+>3e9db8		00 00 00 00 01 fb fb fb fb fb fb fb fb fb 01 00
+>3e9dc8		00 00 00 00 00 00 01 01 01 01 00 00 00 00 00 00
+>3e9dd8		00 00 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9de8		00 01 fb fb fb fb fb fb fb fb fb fb 01 00 00 00
+>3e9df8		00 00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb
+>3e9e08		fb fb fb fb fb 01 00 00 00 00 00 00 00 00 00 00
+>3e9e18		00 00 00 01 fb fb fb fb fb fb fb fb fb fb fb 01
+>3e9e28		01 01 01 01 01 01 01 fb fb fb 01 01 01 01 01 01
+>3e9e38		01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9e48		01 fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00
+>3e9e58		00 00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb
+>3e9e68		fb fb fb fb 01 00 00 00 00 00 00 00 00 00 00 00
+>3e9e78		00 00 00 01 fb fb fb fb fb fb fb fb fb fb fb fb
+>3e9e88		fb fb fb fb fb fb fb fb fb 01 01 01 01 01 00 00
+>3e9e98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9ea8		01 fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00
+>3e9eb8		00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb
+>3e9ec8		fb fb fb 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3e9ed8		00 00 01 fb fb fb fb fb fb fb fb fb fb fb fb fb
+>3e9ee8		fb fb fb fb fb fb fb fb 01 00 00 00 00 00 00 00
+>3e9ef8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e9f08		fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00
+>3e9f18		00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb
+>3e9f28		fb fb fb 01 00 00 00 00 00 00 00 00 00 01 01 01
+>3e9f38		01 01 fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+>3e9f48		fb fb fb fb fb fb fb fb fb 01 01 01 01 01 01 01
+>3e9f58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e9f68		fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00 00
+>3e9f78		00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb fb
+>3e9f88		fb fb 01 00 00 00 00 00 00 01 01 01 01 fb fb fb
+>3e9f98		fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+>3e9fa8		fb fb fb fb fb fb fb fb fb fb 01 01 00 00 00 00
+>3e9fb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3e9fc8		fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00 00
+>3e9fd8		00 00 00 00 00 01 fb fb fb fb fb fb fb fb fb fb
+>3e9fe8		fb fb 01 00 00 00 01 01 01 fb fb fb fb fb fb fb
+>3e9ff8		fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb fb
+>3ea008		fb fb fb fb fb fb fb fb fb 01 00 00 00 00 00 00
+>3ea018		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa
+>3ea028		fa fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00
+>3ea038		00 00 00 00 00 01 fa fa fa fa fa fa fa fa fa fa
+>3ea048		fa 01 00 00 01 01 fa fa fa fa fa fa fa fa fa fa
+>3ea058		fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea068		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3ea078		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa
+>3ea088		fa fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00
+>3ea098		00 00 00 00 01 fa fa fa fa fa fa fa fa fa fa fa
+>3ea0a8		01 00 00 01 fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea0b8		fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea0c8		fa fa fa fa fa fa fa fa 01 01 00 00 00 00 00 00
+>3ea0d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa
+>3ea0e8		fa fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00
+>3ea0f8		00 00 00 01 fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea108		01 00 01 fa fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea118		fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea128		fa fa fa fa fa 01 01 01 00 00 00 00 00 00 00 00
+>3ea138		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3ea148		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3ea158		00 00 00 01 fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea168		01 00 01 fa fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea178		fa fa fa fa fa fa fa fa fa fa fa fa fa fa 01 01
+>3ea188		01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3ea198		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3ea1a8		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3ea1b8		00 00 01 fa fa fa fa fa fa fa fa fa fa fa fa fa
+>3ea1c8		01 00 00 01 01 01 fa fa fa fa fa fa fa fa fa fa
+>3ea1d8		fa fa fa fa fa fa fa fa fa fa fa fa 01 01 00 01
+>3ea1e8		01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3ea1f8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3ea208		fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00
+>3ea218		00 01 fa fa fa fa fa fa fa fa fa fa fa fa fa 01
+>3ea228		00 00 00 00 00 00 01 01 fa fa fa fa fa fa fa fa
+>3ea238		fa fa fa fa fa fa fa fa fa fa 01 01 00 00 00 00
+>3ea248		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea258		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3ea268		fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00
+>3ea278		01 fa fa fa fa fa fa fa fa fa fa fa fa fa 01 00
+>3ea288		00 00 00 00 00 00 00 00 01 01 01 01 01 fa fa fa
+>3ea298		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3ea2a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea2b8		00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa fa
+>3ea2c8		fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00 01
+>3ea2d8		fa fa fa fa fa fa fa fa fa fa fa fa fa fa 01 00
+>3ea2e8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3ea2f8		fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00
+>3ea308		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea318		00 00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9
+>3ea328		f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 01 f9
+>3ea338		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00
+>3ea348		00 00 00 00 00 00 00 00 00 00 00 00 00 01 f9 f9
+>3ea358		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00 00
+>3ea368		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea378		00 00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9
+>3ea388		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 01 f9
+>3ea398		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00
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+>3ea3f8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00
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+>3ea418		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00 00
+>3ea428		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea438		00 00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9
+>3ea448		f9 f9 f9 f9 f9 f9 f9 f9 01 00 01 01 f9 f9 f9 f9
+>3ea458		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00
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+>3ea478		f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00 00 00
+>3ea488		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea498		00 00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9
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+>3ea518		f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00
+>3ea528		00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 01
+>3ea538		00 01 f9 f9 f9 f9 01 00 00 00 00 00 00 00 00 00
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+>3ea558		00 00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9
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+>3ea588		00 00 00 00 00 00 00 00 00 00 00 01 01 01 01 01
+>3ea598		00 01 f9 f9 f9 01 00 00 00 00 00 00 00 00 00 00
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+>3ea5d8		f9 f9 f9 f9 f9 f9 01 01 00 00 00 00 00 00 00 00
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+>3ea608		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea618		00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
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+>3ea638		f8 f8 f8 f8 f8 01 00 00 00 00 00 00 00 00 00 00
+>3ea648		00 00 00 00 00 00 00 00 00 00 01 f8 f8 01 00 00
+>3ea658		01 01 00 01 01 00 00 00 00 00 00 00 00 00 00 00
+>3ea668		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea678		00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
+>3ea688		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3ea698		f8 f8 f8 f8 01 00 00 00 00 00 00 00 00 00 00 00
+>3ea6a8		00 00 00 00 00 00 00 00 00 00 01 f8 f8 01 00 00
+>3ea6b8		01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea6c8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea6d8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8
+>3ea6e8		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3ea6f8		f8 f8 f8 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea708		00 00 00 00 00 00 00 00 00 00 01 f8 f8 01 00 00
+>3ea718		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea728		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea738		00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8
+>3ea748		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3ea758		f8 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea768		00 00 00 00 00 00 00 00 00 00 01 f8 01 00 00 01
+>3ea778		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea788		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea798		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8
+>3ea7a8		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3ea7b8		f8 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea7c8		00 00 00 00 00 00 00 00 00 00 01 01 00 00 00 01
+>3ea7d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea7e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea7f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3ea808		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3ea818		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea828		00 00 00 00 00 00 00 00 00 00 01 01 00 00 00 00
+>3ea838		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3ea868		01 f8 f8 f8 f8 f8 f8 f8 f8 f8 01 f8 f8 01 01 01
+>3ea878		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea888		00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00
+>3ea898		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3ea8c8		00 01 01 01 f8 f8 f8 01 01 01 00 01 01 00 00 00
+>3ea8d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3ea8e8		00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00
+>3ea8f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3ea928		00 00 00 00 01 01 01 00 00 00 00 00 00 00 00 00
+>3ea938		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 27 times (432 bytes)...
+>3eaaf8		00 00 00 00 00 00 00 00
+.3eab00						SS_U_TXT
+>3eab00		00 00 00 00 00 00 00 00		.binary "SplashScreenCode/Graphics Assets/Graphic_U.data"
+>3eab08		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 10 times (160 bytes)...
+>3eabb8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eabc8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eabf8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eac08		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eac18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eac28		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3eac38		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eac48		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eac58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eac68		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 01
+>3eac78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eaca8		00 00 00 00 00 01 01 00 00 00 00 00 00 00 01 01
+>3eacb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eace8		00 00 00 00 00 01 00 00 00 00 00 00 00 01 01 00
+>3eacf8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3ead28		00 00 00 00 01 01 00 00 00 01 01 01 01 fe 01 00
+>3ead38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3ead68		00 00 00 01 fe 01 00 00 00 01 fe fe fe fe 01 00
+>3ead78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eada8		00 00 00 01 fe 01 00 00 01 fe fe fe fe 01 00 00
+>3eadb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eade8		00 00 01 fd fd 01 00 01 fd fd fd fd fd 01 00 00
+>3eadf8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eae28		00 01 fd fd fd fd 01 fd fd fd fd fd fd 01 00 00
+>3eae38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eae48		00 00 00 00 00 00 00 00 00 00 01 01 01 00 00 00
+>3eae58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eae68		00 01 fd fd fd fd fd fd fd fd fd fd 01 00 00 00
+>3eae78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eae88		00 00 00 00 00 00 00 00 00 01 fd fd fd 01 00 00
+>3eae98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eaea8		01 fd fd fd fd fd fd fd fd fd fd fd 01 00 00 00
+>3eaeb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eaec8		00 00 00 00 00 00 00 00 01 fd fd fd fd fd 01 00
+>3eaed8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eaee8		01 fd fd fd fd fd fd fd fd fd fd 01 00 00 00 00
+>3eaef8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eaf08		00 00 00 00 00 00 01 01 fd fd fd fd fd fd fd 01
+>3eaf18		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3eaf28		fd fd fd fd fd fd fd fd fd fd fd 01 00 00 00 00
+>3eaf38		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eaf48		00 00 00 00 00 01 fd fd fd fd fd fd fd fd fd 01
+>3eaf58		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fd
+>3eaf68		fd fd fd fd fd fd fd fd fd fd 01 00 00 00 00 00
+>3eaf78		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eaf88		00 00 00 00 00 01 fd fd fd fd fd fd fd fd fd 01
+>3eaf98		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fd
+>3eafa8		fd fd fd fd fd fd fd fd fd fd 01 00 00 00 00 00
+>3eafb8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eafc8		00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc 01
+>3eafd8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc
+>3eafe8		fc fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00
+>3eaff8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb008		00 00 00 00 01 fc fc fc fc fc fc fc fc fc fc 01
+>3eb018		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc
+>3eb028		fc fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00
+>3eb038		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb048		00 00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01
+>3eb058		00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc
+>3eb068		fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00
+>3eb078		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb088		00 00 00 01 fc fc fc fc fc fc fc fc fc fc 01 00
+>3eb098		00 00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc
+>3eb0a8		fc fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00
+>3eb0b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb0c8		00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01 00
+>3eb0d8		00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc fc
+>3eb0e8		fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00 00
+>3eb0f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb108		00 00 01 fc fc fc fc fc fc fc fc fc fc fc 01 00
+>3eb118		00 00 00 00 00 00 00 00 00 00 00 01 fc fc fc fc
+>3eb128		fc fc fc fc fc fc fc 01 00 00 00 00 00 00 00 00
+>3eb138		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb148		00 01 fc fc fc fc fc fc fc fc fc fc fc 01 00 00
+>3eb158		00 00 00 00 00 00 00 00 00 00 01 fc fc fc fc fc
+>3eb168		fc fc fc fc fc fc 01 00 00 00 00 00 00 00 00 00
+>3eb178		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb188		00 01 fc fc fc fc fc fc fc fc fc fc fc 01 00 00
+>3eb198		00 00 00 00 00 00 00 00 00 00 01 fc fc fc fc fc
+>3eb1a8		fc fc fc fc fc 01 00 00 00 00 00 00 00 00 00 00
+>3eb1b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb1c8		01 fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00
+>3eb1d8		00 00 00 00 00 00 00 00 00 01 fb fb fb fb fb fb
+>3eb1e8		fb fb fb fb fb 01 00 00 00 00 00 00 00 00 00 00
+>3eb1f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb208		01 fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00
+>3eb218		00 00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb
+>3eb228		fb fb fb fb 01 00 00 00 00 00 00 00 00 00 00 00
+>3eb238		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb248		01 fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00
+>3eb258		00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb
+>3eb268		fb fb fb fb 01 00 00 00 00 00 00 00 00 00 00 00
+>3eb278		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3eb288		fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00
+>3eb298		00 00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb
+>3eb2a8		fb fb fb 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb2b8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3eb2c8		fb fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00
+>3eb2d8		00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb fb
+>3eb2e8		fb fb 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb2f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fb
+>3eb308		fb fb fb fb fb fb fb fb fb fb 01 00 00 00 00 00
+>3eb318		00 00 00 00 00 00 01 fb fb fb fb fb fb fb fb fb
+>3eb328		fb fb 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb338		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fb
+>3eb348		fb fb fb fb fb fb fb fb fb 01 00 00 00 00 00 00
+>3eb358		00 00 00 00 00 01 fb fb fb fb fb fb fb fb fb fb
+>3eb368		fb 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb378		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 fb
+>3eb388		fb fb fb fb fb fb fb fb fb 01 00 00 00 00 00 00
+>3eb398		00 00 00 00 01 fb fb fb fb fb fb fb fb fb fb fb
+>3eb3a8		fb 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb3b8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3eb3c8		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3eb3d8		00 00 00 00 01 fa fa fa fa fa fa fa fa fa fa fa
+>3eb3e8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb3f8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3eb408		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3eb418		00 00 00 01 fa fa fa fa fa fa fa fa fa fa fa 01
+>3eb428		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb438		00 00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa
+>3eb448		fa fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00
+>3eb458		00 00 01 fa fa fa fa fa fa fa fa fa fa fa fa 01
+>3eb468		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb478		00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa fa
+>3eb488		fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00
+>3eb498		00 00 01 fa fa fa fa fa fa fa fa fa fa fa fa 01
+>3eb4a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb4b8		00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa fa
+>3eb4c8		fa fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00
+>3eb4d8		00 01 fa fa fa fa fa fa fa fa fa fa fa fa fa 01
+>3eb4e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb4f8		00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa fa
+>3eb508		fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00 00
+>3eb518		01 fa fa fa fa fa fa fa fa fa fa fa fa fa 01 00
+>3eb528		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb538		00 00 00 00 00 00 00 00 00 00 00 00 01 fa fa fa
+>3eb548		fa fa fa fa fa fa fa 01 00 00 00 00 00 00 00 01
+>3eb558		fa fa fa fa fa fa fa fa fa fa fa fa fa 01 00 00
+>3eb568		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb578		00 00 00 00 00 00 00 00 00 00 00 01 fa fa fa fa
+>3eb588		fa fa fa fa fa fa fa 01 00 00 00 00 00 00 01 fa
+>3eb598		fa fa fa fa fa fa fa fa fa fa fa fa fa 01 00 00
+>3eb5a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb5b8		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb5c8		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 01 f9 f9
+>3eb5d8		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00
+>3eb5e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb5f8		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb608		f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 01 f9 f9
+>3eb618		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00
+>3eb628		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb638		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb648		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 01 01 f9 f9 f9
+>3eb658		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00
+>3eb668		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb678		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb688		f9 f9 f9 f9 f9 f9 f9 01 00 01 01 f9 f9 f9 f9 f9
+>3eb698		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00
+>3eb6a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb6b8		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb6c8		f9 f9 f9 f9 f9 f9 f9 f9 01 f9 f9 f9 f9 f9 f9 f9
+>3eb6d8		f9 f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00
+>3eb6e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb6f8		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb708		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3eb718		f9 f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00
+>3eb728		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb738		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb748		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3eb758		f9 f9 f9 f9 f9 f9 f9 01 00 00 00 00 00 00 00 00
+>3eb768		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb778		00 00 00 00 00 00 00 00 00 00 00 01 f9 f9 f9 f9
+>3eb788		f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9 f9
+>3eb798		f9 f9 f9 f9 f9 01 01 00 00 00 00 00 00 00 00 00
+>3eb7a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb7b8		00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8 f8
+>3eb7c8		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3eb7d8		f8 f8 f8 f8 01 00 00 00 00 00 00 00 00 00 00 00
+>3eb7e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb7f8		00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8 f8
+>3eb808		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3eb818		f8 f8 f8 01 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb828		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb838		00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
+>3eb848		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3eb858		f8 f8 01 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb868		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb878		00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8 f8
+>3eb888		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3eb898		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb8a8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb8b8		00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8 f8
+>3eb8c8		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8
+>3eb8d8		01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb8e8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb8f8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 01 f8
+>3eb908		f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 f8 01
+>3eb918		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb928		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+>3eb938		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 01
+>3eb948		f8 f8 f8 f8 f8 f8 f8 f8 f8 01 f8 f8 01 01 01 00
+>3eb958		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eb988		01 01 01 f8 f8 f8 01 01 01 00 01 01 00 00 00 00
+>3eb998		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 2 times (32 bytes)...
+>3eb9c8		00 00 00 01 01 01 00 00 00 00 00 00 00 00 00 00
+>3eb9d8		00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+;		...repeated 17 times (272 bytes)...
+>3ebaf8		00 00 00 00 00 00 00 00
+.3f0000						FONT_4_BANK0
+>3f0000		00 00 00 00 00 00 00 00		.binary "FONT/Bm437_PhoenixEGA_8x8.bin", 0, 2048
+>3f0008		7e 81 a5 81 bd 99 81 7e 3c 7e db ff c3 7e 3c 00
+>3f0018		00 ee fe fe 7c 38 10 00 10 38 7c fe 7c 38 10 00
+>3f0028		00 3c 18 ff ff 08 18 00 10 38 7c fe fe 10 38 00
+>3f0038		00 00 18 3c 18 00 00 00 ff ff e7 c3 e7 ff ff ff
+>3f0048		00 3c 42 81 81 42 3c 00 ff c3 bd 7e 7e bd c3 ff
+>3f0058		01 03 07 0f 1f 3f 7f ff ff fe fc f8 f0 e0 c0 80
+>3f0068		04 06 07 04 04 fc f8 00 0c 0a 0d 0b f9 f9 1f 1f
+>3f0078		00 92 7c 44 c6 7c 92 00 00 00 60 78 7e 78 60 00
+>3f0088		00 00 06 1e 7e 1e 06 00 18 7e 18 18 18 18 7e 18
+>3f0098		66 66 66 66 66 00 66 00 ff b6 76 36 36 36 36 00
+>3f00a8		7e c1 dc 22 22 1f 83 7e 00 00 00 7e 7e 00 00 00
+>3f00b8		18 7e 18 18 7e 18 00 ff 18 7e 18 18 18 18 18 00
+>3f00c8		18 18 18 18 18 7e 18 00 00 04 06 ff 06 04 00 00
+>3f00d8		00 20 60 ff 60 20 00 00 00 00 00 c0 c0 c0 ff 00
+>3f00e8		00 24 66 ff 66 24 00 00 00 00 10 38 7c fe 00 00
+>3f00f8		00 00 00 fe 7c 38 10 00 00 00 00 00 00 00 00 00
+>3f0108		30 30 30 30 30 00 30 00 66 66 00 00 00 00 00 00
+>3f0118		6c 6c fe 6c fe 6c 6c 00 10 7c d2 7c 86 7c 10 00
+>3f0128		f0 96 fc 18 3e 72 de 00 30 48 30 78 ce cc 78 00
+>3f0138		0c 0c 18 00 00 00 00 00 10 60 c0 c0 c0 60 10 00
+>3f0148		10 0c 06 06 06 0c 10 00 00 54 38 fe 38 54 00 00
+>3f0158		00 18 18 7e 18 18 00 00 00 00 00 00 00 00 18 70
+>3f0168		00 00 00 7e 00 00 00 00 00 00 00 00 00 00 18 00
+>3f0178		02 06 0c 18 30 60 c0 00 7c ce de f6 e6 e6 7c 00
+>3f0188		18 38 78 18 18 18 3c 00 7c c6 06 0c 30 60 fe 00
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+
+;******  End of listing
diff --git a/Main/UI/MainWindow.Designer.cs b/Main/UI/MainWindow.Designer.cs
index 2dcb57f..4843518 100644
--- a/Main/UI/MainWindow.Designer.cs
+++ b/Main/UI/MainWindow.Designer.cs
@@ -71,6 +71,8 @@ private void InitializeComponent()
             this.aboutToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();
             this.Tooltip = new System.Windows.Forms.ToolTip(this.components);
             this.gpu = new FoenixIDE.Display.Gpu();
+            this.settingsToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();
+            this.autorunEmulatorToolStripMenuItem = new System.Windows.Forms.ToolStripMenuItem();
             this.statusStrip1.SuspendLayout();
             this.menuStrip1.SuspendLayout();
             this.SuspendLayout();
@@ -174,7 +176,7 @@ private void InitializeComponent()
             this.SDCardPath.Font = new System.Drawing.Font("Segoe UI", 9F, System.Drawing.FontStyle.Bold);
             this.SDCardPath.Name = "SDCardPath";
             this.SDCardPath.Overflow = System.Windows.Forms.ToolStripItemOverflow.Always;
-            this.SDCardPath.Size = new System.Drawing.Size(210, 23);
+            this.SDCardPath.Size = new System.Drawing.Size(241, 23);
             this.SDCardPath.Spring = true;
             this.SDCardPath.Text = "SD Card Disabled";
             this.SDCardPath.TextAlign = System.Drawing.ContentAlignment.MiddleLeft;
@@ -187,6 +189,7 @@ private void InitializeComponent()
             this.menuStrip1.Items.AddRange(new System.Windows.Forms.ToolStripItem[] {
             this.fileToolStripMenuItem,
             this.toolsToolStripMenuItem,
+            this.settingsToolStripMenuItem,
             this.windowsToolStripMenuItem,
             this.resetToolStripMenuItem,
             this.helpToolStripMenuItem});
@@ -212,42 +215,42 @@ private void InitializeComponent()
             // menuOpenHexFile
             // 
             this.menuOpenHexFile.Name = "menuOpenHexFile";
-            this.menuOpenHexFile.Size = new System.Drawing.Size(167, 22);
+            this.menuOpenHexFile.Size = new System.Drawing.Size(180, 22);
             this.menuOpenHexFile.Text = "&Open Hex File";
             this.menuOpenHexFile.Click += new System.EventHandler(this.MenuOpenHexFile_Click);
             // 
             // loadFNXMLFileToolStripMenuItem
             // 
             this.loadFNXMLFileToolStripMenuItem.Name = "loadFNXMLFileToolStripMenuItem";
-            this.loadFNXMLFileToolStripMenuItem.Size = new System.Drawing.Size(167, 22);
+            this.loadFNXMLFileToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.loadFNXMLFileToolStripMenuItem.Text = "&Load Project...";
             this.loadFNXMLFileToolStripMenuItem.Click += new System.EventHandler(this.LoadFNXMLFileToolStripMenuItem_Click);
             // 
             // saveProjectToolStripMenuItem
             // 
             this.saveProjectToolStripMenuItem.Name = "saveProjectToolStripMenuItem";
-            this.saveProjectToolStripMenuItem.Size = new System.Drawing.Size(167, 22);
+            this.saveProjectToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.saveProjectToolStripMenuItem.Text = "&Save Project...";
             this.saveProjectToolStripMenuItem.Click += new System.EventHandler(this.SaveProjectToolStripMenuItem_Click);
             // 
             // loadWatchListToolStripMenuItem
             // 
             this.loadWatchListToolStripMenuItem.Name = "loadWatchListToolStripMenuItem";
-            this.loadWatchListToolStripMenuItem.Size = new System.Drawing.Size(167, 22);
+            this.loadWatchListToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.loadWatchListToolStripMenuItem.Text = "Load Watch List...";
             this.loadWatchListToolStripMenuItem.Click += new System.EventHandler(this.LoadWatchListToolStripMenuItem_Click);
             // 
             // saveWatchListToolStripMenuItem
             // 
             this.saveWatchListToolStripMenuItem.Name = "saveWatchListToolStripMenuItem";
-            this.saveWatchListToolStripMenuItem.Size = new System.Drawing.Size(167, 22);
+            this.saveWatchListToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.saveWatchListToolStripMenuItem.Text = "Save Watch List...";
             this.saveWatchListToolStripMenuItem.Click += new System.EventHandler(this.SaveWatchListToolStripMenuItem_Click);
             // 
             // exitToolStripMenuItem
             // 
             this.exitToolStripMenuItem.Name = "exitToolStripMenuItem";
-            this.exitToolStripMenuItem.Size = new System.Drawing.Size(167, 22);
+            this.exitToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.exitToolStripMenuItem.Text = "E&xit";
             this.exitToolStripMenuItem.Click += new System.EventHandler(this.ExitToolStripMenuItem_Click);
             // 
@@ -344,7 +347,7 @@ private void InitializeComponent()
             // terminalToolStripMenuItem
             // 
             this.terminalToolStripMenuItem.Name = "terminalToolStripMenuItem";
-            this.terminalToolStripMenuItem.Size = new System.Drawing.Size(129, 22);
+            this.terminalToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.terminalToolStripMenuItem.Text = "&Terminal";
             this.terminalToolStripMenuItem.Click += new System.EventHandler(this.TerminalToolStripMenuItem_Click);
             // 
@@ -352,7 +355,7 @@ private void InitializeComponent()
             // 
             this.cPUToolStripMenuItem.Enabled = false;
             this.cPUToolStripMenuItem.Name = "cPUToolStripMenuItem";
-            this.cPUToolStripMenuItem.Size = new System.Drawing.Size(129, 22);
+            this.cPUToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.cPUToolStripMenuItem.Text = "&CPU";
             this.cPUToolStripMenuItem.Click += new System.EventHandler(this.CPUToolStripMenuItem_Click);
             // 
@@ -360,14 +363,14 @@ private void InitializeComponent()
             // 
             this.memoryToolStripMenuItem.Enabled = false;
             this.memoryToolStripMenuItem.Name = "memoryToolStripMenuItem";
-            this.memoryToolStripMenuItem.Size = new System.Drawing.Size(129, 22);
+            this.memoryToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.memoryToolStripMenuItem.Text = "&Memory";
             this.memoryToolStripMenuItem.Click += new System.EventHandler(this.MemoryToolStripMenuItem_Click);
             // 
             // watchListToolStripMenuItem
             // 
             this.watchListToolStripMenuItem.Name = "watchListToolStripMenuItem";
-            this.watchListToolStripMenuItem.Size = new System.Drawing.Size(129, 22);
+            this.watchListToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.watchListToolStripMenuItem.Text = "Watch List";
             this.watchListToolStripMenuItem.Click += new System.EventHandler(this.WatchListToolStripMenuItem_Click);
             // 
@@ -410,14 +413,14 @@ private void InitializeComponent()
             // checkForUpdateToolStripMenuItem
             // 
             this.checkForUpdateToolStripMenuItem.Name = "checkForUpdateToolStripMenuItem";
-            this.checkForUpdateToolStripMenuItem.Size = new System.Drawing.Size(166, 22);
+            this.checkForUpdateToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.checkForUpdateToolStripMenuItem.Text = "Check for &Update";
             this.checkForUpdateToolStripMenuItem.Click += new System.EventHandler(this.CheckForUpdateToolStripMenuItem_Click);
             // 
             // aboutToolStripMenuItem
             // 
             this.aboutToolStripMenuItem.Name = "aboutToolStripMenuItem";
-            this.aboutToolStripMenuItem.Size = new System.Drawing.Size(166, 22);
+            this.aboutToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
             this.aboutToolStripMenuItem.Text = "&About";
             this.aboutToolStripMenuItem.Click += new System.EventHandler(this.AboutToolStripMenuItem_Click);
             // 
@@ -443,6 +446,25 @@ private void InitializeComponent()
             this.gpu.MouseMove += new System.Windows.Forms.MouseEventHandler(this.Gpu_MouseMove);
             this.gpu.MouseUp += new System.Windows.Forms.MouseEventHandler(this.Gpu_MouseUp);
             // 
+            // settingsToolStripMenuItem
+            // 
+            this.settingsToolStripMenuItem.DropDownItems.AddRange(new System.Windows.Forms.ToolStripItem[] {
+            this.autorunEmulatorToolStripMenuItem});
+            this.settingsToolStripMenuItem.Name = "settingsToolStripMenuItem";
+            this.settingsToolStripMenuItem.Size = new System.Drawing.Size(61, 20);
+            this.settingsToolStripMenuItem.Text = "&Settings";
+            // 
+            // autorunEmulatorToolStripMenuItem
+            // 
+            this.autorunEmulatorToolStripMenuItem.Checked = true;
+            this.autorunEmulatorToolStripMenuItem.CheckOnClick = true;
+            this.autorunEmulatorToolStripMenuItem.CheckState = System.Windows.Forms.CheckState.Checked;
+            this.autorunEmulatorToolStripMenuItem.DisplayStyle = System.Windows.Forms.ToolStripItemDisplayStyle.Text;
+            this.autorunEmulatorToolStripMenuItem.Name = "autorunEmulatorToolStripMenuItem";
+            this.autorunEmulatorToolStripMenuItem.Size = new System.Drawing.Size(180, 22);
+            this.autorunEmulatorToolStripMenuItem.Text = "Autorun Emulator";
+            this.autorunEmulatorToolStripMenuItem.Click += new System.EventHandler(this.autorunEmulatorToolStripMenuItem_Click);
+            // 
             // MainWindow
             // 
             this.AllowDrop = true;
@@ -518,6 +540,8 @@ private void InitializeComponent()
         private System.Windows.Forms.ToolStripMenuItem ConvertBinToPGXToolStripMenuItem;
         private System.Windows.Forms.ToolStripMenuItem checkForUpdateToolStripMenuItem;
         private System.Windows.Forms.ToolStripMenuItem gameEditorToolStripMenuItem;
+        private System.Windows.Forms.ToolStripMenuItem settingsToolStripMenuItem;
+        private System.Windows.Forms.ToolStripMenuItem autorunEmulatorToolStripMenuItem;
     }
 }
 
diff --git a/Main/UI/MainWindow.cs b/Main/UI/MainWindow.cs
index 3f8ac9b..90a51db 100644
--- a/Main/UI/MainWindow.cs
+++ b/Main/UI/MainWindow.cs
@@ -19,6 +19,7 @@
 using System.Text.RegularExpressions;
 using System.Net;
 using FoenixIDE.Display;
+using System.Runtime.InteropServices;
 
 namespace FoenixIDE.UI
 {
@@ -85,6 +86,30 @@ public MainWindow(Dictionary<string, string> context)
                     {
                         version = BoardVersion.RevU;
                     }
+                    else if (context["version"] == "RevU+")
+                    {
+                        version = BoardVersion.RevUPlus;
+                    }
+                }
+            }
+            // If the user didn't specify context switches, read the ini setting
+            if (context == null)
+            {
+                autoRun = Simulator.Properties.Settings.Default.Autorun;
+                switch (Simulator.Properties.Settings.Default.BoardRevision)
+                {
+                    case "B":
+                        version = BoardVersion.RevB;
+                        break;
+                    case "C":
+                        version = BoardVersion.RevC;
+                        break;
+                    case "U":
+                        version = BoardVersion.RevU;
+                        break;
+                    case "U+":
+                        version = BoardVersion.RevUPlus;
+                        break;
                 }
             }
             if (context == null || "true".Equals(context["Continue"]))
@@ -146,6 +171,7 @@ private void BasicWindow_Load(object sender, EventArgs e)
             {
                 debugWindow.RunButton_Click(null, null);
             }
+            autorunEmulatorToolStripMenuItem.Checked = autoRun;
         }
 
         private void LoadHexFile(string Filename)
@@ -643,6 +669,10 @@ private void LoadWatchListToolStripMenuItem_Click(object sender, EventArgs e)
                 FoeniXmlFile xmlFile = new FoeniXmlFile(kernel, null);
                 xmlFile.ReadWatches(dialog.FileName);
                 watchWindow.SetKernel(kernel);
+                if (!watchWindow.Visible)
+                {
+                    watchWindow.Show();
+                }
             }
         }
 
@@ -851,9 +881,11 @@ private void ResetSDCard()
 
         private void DisplayBoardVersion()
         {
+            string shortVersion = "C";
             if (version == BoardVersion.RevB)
             {
                 toolStripRevision.Text = "Rev B";
+                shortVersion = "B";
             }
             else if (version == BoardVersion.RevC)
             {
@@ -862,13 +894,17 @@ private void DisplayBoardVersion()
             else if (version == BoardVersion.RevU)
             {
                 toolStripRevision.Text = "Rev U";
+                shortVersion = "U";
             }
             else
             {
                 toolStripRevision.Text = "Rev U+";
+                shortVersion = "U+";
             }
             // force repaint
             statusStrip1.Invalidate();
+            Simulator.Properties.Settings.Default.BoardRevision = shortVersion;
+            Simulator.Properties.Settings.Default.Save();
         }
 
         private void ToolStripRevision_Click(object sender, EventArgs e)
@@ -1196,6 +1232,12 @@ private void GameEditorToolStripMenuItem_Click(object sender, EventArgs e)
                 GGF.BringToFront();
             }
         }
+
+        private void autorunEmulatorToolStripMenuItem_Click(object sender, EventArgs e)
+        {
+            Simulator.Properties.Settings.Default.Autorun = autorunEmulatorToolStripMenuItem.Checked;
+            Simulator.Properties.Settings.Default.Save();
+        }
     }
 }
 
diff --git a/Main/UI/UploaderWindow.Designer.cs b/Main/UI/UploaderWindow.Designer.cs
index 5372ee8..e1cbe29 100644
--- a/Main/UI/UploaderWindow.Designer.cs
+++ b/Main/UI/UploaderWindow.Designer.cs
@@ -28,6 +28,7 @@ protected override void Dispose(bool disposing)
         /// </summary>
         private void InitializeComponent()
         {
+            this.components = new System.ComponentModel.Container();
             System.ComponentModel.ComponentResourceManager resources = new System.ComponentModel.ComponentResourceManager(typeof(UploaderWindow));
             this.ConnectButton = new System.Windows.Forms.Button();
             this.COMPortComboBox = new System.Windows.Forms.ComboBox();
@@ -60,6 +61,7 @@ private void InitializeComponent()
             this.ReflashCheckbox = new System.Windows.Forms.CheckBox();
             this.CountdownLabel = new System.Windows.Forms.Label();
             this.RevModeLabel = new System.Windows.Forms.Label();
+            this.hideLabelTimer = new System.Windows.Forms.Timer(this.components);
             this.SuspendLayout();
             // 
             // ConnectButton
@@ -421,6 +423,11 @@ private void InitializeComponent()
             this.RevModeLabel.TabIndex = 30;
             this.RevModeLabel.Text = "Mode: RevB";
             // 
+            // hideLabelTimer
+            // 
+            this.hideLabelTimer.Interval = 5000;
+            this.hideLabelTimer.Tick += new System.EventHandler(this.hideLabelTimer_Tick);
+            // 
             // UploaderWindow
             // 
             this.AutoScaleDimensions = new System.Drawing.SizeF(6F, 13F);
@@ -508,5 +515,6 @@ private void InitializeComponent()
         private System.Windows.Forms.CheckBox ReflashCheckbox;
         private System.Windows.Forms.Label CountdownLabel;
         private System.Windows.Forms.Label RevModeLabel;
+        private System.Windows.Forms.Timer hideLabelTimer;
     }
 }
\ No newline at end of file
diff --git a/Main/UI/UploaderWindow.cs b/Main/UI/UploaderWindow.cs
index 58ef766..7106c51 100644
--- a/Main/UI/UploaderWindow.cs
+++ b/Main/UI/UploaderWindow.cs
@@ -12,6 +12,7 @@
 using System.Threading;
 using System.Threading.Tasks;
 using System.Windows.Forms;
+using Timer = System.Windows.Forms.Timer;
 
 namespace FoenixIDE.UI
 {
@@ -231,7 +232,7 @@ private void SendBinaryButton_Click(object sender, EventArgs e)
         {
             SendBinaryButton.Enabled = false;
             DisconnectButton.Enabled = false;
-
+            hideLabelTimer_Tick(null, null);
             int transmissionSize = GetTransmissionSize();
             UploadProgressBar.Maximum = transmissionSize;
             UploadProgressBar.Value = 0;
@@ -355,16 +356,14 @@ private void SendBinaryButton_Click(object sender, EventArgs e)
                         EraseFlash();
                         int SrcFlashAddress = Convert.ToInt32(C256DestAddress.Text.Replace(":", ""), 16);
                         ProgramFlash(SrcFlashAddress);
-
                         CountdownLabel.Visible = false;
-                        this.Update();
                     }
                     if (DebugModeCheckbox.Checked)
                     {
                         // The Loading of the File is Done, Reset the FNX and Get out of Debug Mode
                         ExitFnxDebugMode();
                     }
-                    MessageBox.Show("Transfer Done! System Reset!", "Send Binary Success", MessageBoxButtons.OK, MessageBoxIcon.Information);
+                    HideProgressBarAfter5Seconds("Transfer Done! System Reset!");
                 }
             }
             else if (BlockSendRadio.Checked && kernel.CPU != null)
@@ -394,7 +393,7 @@ private void SendBinaryButton_Click(object sender, EventArgs e)
                     // The Loading of the File is Done, Reset the FNX and Get out of Debug Mode
                     ExitFnxDebugMode();
                 }
-                MessageBox.Show("Transfer Done! System Reset!", "Send Binary Success", MessageBoxButtons.OK, MessageBoxIcon.Information);
+                HideProgressBarAfter5Seconds("Transfer Done! System Reset!");
             }
             else
             {
@@ -415,12 +414,26 @@ private void SendBinaryButton_Click(object sender, EventArgs e)
                     tempMem.Show();
                 }
             }
-            
-            UploadProgressBar.Visible = false;
             SendBinaryButton.Enabled = true;
             DisconnectButton.Enabled = true;
         }
 
+        private void HideProgressBarAfter5Seconds(string message)
+        {
+            UploadProgressBar.Visible = false;
+            CountdownLabel.Visible = true;
+            CountdownLabel.Text = message;
+            hideLabelTimer.Enabled = true;
+        }
+
+        private void hideLabelTimer_Tick(object sender, EventArgs e)
+        {
+            hideLabelTimer.Enabled = false;
+            CountdownLabel.Visible = false;
+            CountdownLabel.Text = "";
+        }
+
+
         private byte Checksum(byte[] buffer, int length)
         {
             byte checksum = 0x55;
diff --git a/Main/UI/UploaderWindow.resx b/Main/UI/UploaderWindow.resx
index f18f0d4..9e4194a 100644
--- a/Main/UI/UploaderWindow.resx
+++ b/Main/UI/UploaderWindow.resx
@@ -117,6 +117,9 @@
   <resheader name="writer">
     <value>System.Resources.ResXResourceWriter, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>
   </resheader>
+  <metadata name="hideLabelTimer.TrayLocation" type="System.Drawing.Point, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a">
+    <value>17, 17</value>
+  </metadata>
   <assembly alias="System.Drawing" name="System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a" />
   <data name="$this.Icon" type="System.Drawing.Icon, System.Drawing" mimetype="application/x-microsoft.net.object.bytearray.base64">
     <value>