From 173d53cc2db7f2f9172a903482f3f58dffa482af Mon Sep 17 00:00:00 2001
From: Patrick Lehmann <Patrick.Lehmann@plc2.de>
Date: Wed, 23 Jun 2021 13:31:01 +0200
Subject: [PATCH] Split 'ConstrainedSubTypeSymbol' into a scalar and composite
 variant.

---
 pyVHDLModel/VHDLModel.py | 16 +++++++++++++++-
 1 file changed, 15 insertions(+), 1 deletion(-)

diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py
index a25657e7e..ebaa65bf9 100644
--- a/pyVHDLModel/VHDLModel.py
+++ b/pyVHDLModel/VHDLModel.py
@@ -326,7 +326,21 @@ def __init__(self, subTypeName: str):
 
 
 @export
-class ConstrainedSubTypeSymbol(SubTypeSymbol):
+class ConstrainedScalarSubTypeSymbol(SubTypeSymbol):
+	_range: 'Range'
+
+	def __init__(self, subTypeName: str, range: 'Range' = None):
+		super().__init__(symbolName = subTypeName)
+		self._subType = None
+		self._range = range
+
+	@property
+	def Range(self) -> 'Range':
+		return self._range
+
+
+@export
+class ConstrainedCompositeSubTypeSymbol(SubTypeSymbol):
 	_constraints: List[Constraint]
 
 	def __init__(self, subTypeName: str, constraints: List[Constraint] = None):