From 1ef05db6a96cac82d452f20f079b9e5f46f2049e Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Sat, 19 Jun 2021 12:10:33 +0200 Subject: [PATCH 1/8] Bump version to v0.10.2. --- doc/conf.py | 2 +- setup.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/doc/conf.py b/doc/conf.py index 063eb27a3..ba88b3854 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -37,7 +37,7 @@ def _LatestTagName(): # The full version, including alpha/beta/rc tags version = "0.9" # The short X.Y version. -release = "0.10.1" # The full version, including alpha/beta/rc tags. +release = "0.10.2" # The full version, including alpha/beta/rc tags. try: if _IsUnderGitControl: latestTagName = _LatestTagName()[1:] # remove prefix "v" diff --git a/setup.py b/setup.py index 9f26bf7d1..831e645fb 100644 --- a/setup.py +++ b/setup.py @@ -53,7 +53,7 @@ # Assemble all package information setuptools_setup( name=projectName, - version="0.10.1", + version="0.10.2", author="Patrick Lehmann", author_email="Paebbels@gmail.com", From 2d1ce4dfb2e7aa1f1322b051ade9b409a7c8af3c Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 16:54:49 +0200 Subject: [PATCH 2/8] Added SimpleObjectOrFunctionCallSymbol and IndexedObjectOrFunctionCallSymbol --- pyVHDLModel/VHDLModel.py | 25 ++++++++++++++++++++++--- 1 file changed, 22 insertions(+), 3 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index eb3da6dab..e67371055 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -329,16 +329,35 @@ class EnumerationLiteralSymbol(Symbol): class ObjectSymbol(Symbol): pass + +@export +class SimpleObjectOrFunctionCallSymbol(Symbol): + _object: Union['Constant', 'Signal', 'Variable', 'Function'] + + def __init__(self, objectName: str): + super().__init__(objectName) + self._object = None + + @property + def Object(self) -> Union['Constant', 'Signal', 'Variable', 'Function']: + return self._object + + def __str__(self) -> str: + if self._object is not None: + return str(self._object) + return super().__str__() + + @export -class SimpleObjectSymbol(Symbol): - _object: Union['Constant', 'Signal', 'Variable'] +class IndexedObjectOrFunctionCallSymbol(Symbol): + _object: Union['Constant', 'Signal', 'Variable', 'Function'] def __init__(self, objectName: str): super().__init__(objectName) self._object = None @property - def Object(self) -> Union['Constant', 'Signal', 'Variable']: + def Object(self) -> Union['Constant', 'Signal', 'Variable', 'Function']: return self._object def __str__(self) -> str: From 4884c3df6701275a260f08713482295eeca6502f Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 16:55:18 +0200 Subject: [PATCH 3/8] Added Alias. --- pyVHDLModel/VHDLModel.py | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index e67371055..129dbc196 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -546,6 +546,18 @@ def PackageBodies(self) -> List['PackageBody']: return self._packageBodies +@export +class Alias(ModelEntity, NamedEntity): + def __init__(self, name: str): + """ + Initializes underlying ``BaseType``. + + :param name: Name of the type. + """ + super().__init__() + NamedEntity.__init__(self, name) + + @export class BaseType(ModelEntity, NamedEntity): """``BaseType`` is the base class of all type entities in this model.""" From 780fcfd48feba2ae7f6a0975594e63562fdeee03 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 16:55:56 +0200 Subject: [PATCH 4/8] Fixed swap of NegationExpression and InverseExpression. --- pyVHDLModel/VHDLModel.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 129dbc196..5fd335d7a 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -904,7 +904,7 @@ def __str__(self) -> str: ) @export -class InverseExpression(UnaryExpression): +class NegationExpression(UnaryExpression): _FORMAT = ("-", "") @export @@ -912,7 +912,7 @@ class IdentityExpression(UnaryExpression): _FORMAT = ("+", "") @export -class NegationExpression(UnaryExpression): +class InverseExpression(UnaryExpression): _FORMAT = ("not ", "") @export From 840b6b75f6bd1ca1012f21dc63e884264541c5e5 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 16:56:57 +0200 Subject: [PATCH 5/8] Added a protocol for ParenthesisExpression and handling of SubExpression and QualifiedExpression. --- pyVHDLModel/VHDLModel.py | 42 +++++++++++++++++++++++++++++++++------- 1 file changed, 35 insertions(+), 7 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 5fd335d7a..2d99f6a97 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -43,7 +43,7 @@ # load dependencies from enum import Enum from pathlib import Path -from typing import List, Tuple, Union +from typing import List, Tuple, Union, Protocol from pydecor.decorators import export @@ -880,6 +880,13 @@ def __str__(self) -> str: return "\"" + self._value + "\"" +@export +class ParenthesisExpression(Protocol): + @property + def Operand(self) -> Expression: + pass + + @export class UnaryExpression(BaseExpression): """ @@ -927,8 +934,9 @@ class TypeConversion(UnaryExpression): class FunctionCall(UnaryExpression): pass + @export -class ParenthesisExpression(UnaryExpression): +class SubExpression(UnaryExpression, ParenthesisExpression): _FORMAT = ("(", ")") @@ -963,10 +971,6 @@ def __str__(self) -> str: ) -@export -class QualifiedExpression(BinaryExpression): - pass - @export class AddingExpression(BinaryExpression): """ @@ -1114,6 +1118,30 @@ class RotateRightExpression(RotateExpression): class RotateLeftExpression(RotateExpression): _FORMAT = ("", " rol ", "") + +@export +class QualifiedExpression(BaseExpression, ParenthesisExpression): + _operand: Expression + _subtype: SubTypeOrSymbol + + def __init__(self): + super().__init__() + + @property + def Operand(self): + return self._operand + + @property + def SubTyped(self): + return self._subtype + + def __str__(self) -> str: + return "{subtype}'({operand!s})".format( + subtype=self._subtype, + operand=self._operand, + ) + + @export class TernaryExpression(BaseExpression): """ @@ -1238,7 +1266,7 @@ def Elements(self) -> List[AggregateElement]: return self._elements def __str__(self) -> str: - choices = [self.formatAggregateElement(element) for element in self._elements] + choices = [str(element) for element in self._elements] return "({choices})".format( choices=", ".join(choices) ) From 17597bfba4c32815111fd8888ff0f56f3f7ff8d1 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 19:15:18 +0200 Subject: [PATCH 6/8] Added Component and matching symbol. --- pyVHDLModel/VHDLModel.py | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 2d99f6a97..5c9501af2 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -251,6 +251,19 @@ def Architecture(self) -> 'Architecture': return self._architecture +@export +class ComponentSymbol(Symbol): + _component: 'Component' + + def __init__(self): + super().__init__() + self._component = None + + @property + def Component(self) -> 'Component': + return self._component + + @export class ConfigurationSymbol(Symbol): _configuration: 'Configuration' @@ -1770,6 +1783,27 @@ def BodyItems(self) -> List['ConcurrentStatement']: return self._bodyItems +@export +class Component(ModelEntity, NamedEntity): + _genericItems: List[GenericInterfaceItem] + _portItems: List[PortInterfaceItem] + + def __init__(self, name: str): + super().__init__() + NamedEntity.__init__(self, name) + + self._genericItems = [] + self._portItems = [] + + @property + def GenericItems(self) -> List[GenericInterfaceItem]: + return self._genericItems + + @property + def PortItems(self) -> List[PortInterfaceItem]: + return self._portItems + + @export class Configuration(PrimaryUnit, MixinDesignUnitWithContext): def __init__(self, name: str): From 73492ba5b0cf011b85936a6f04692b1bc409b2cc Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 19:16:05 +0200 Subject: [PATCH 7/8] Added Physical...Literals. --- pyVHDLModel/VHDLModel.py | 40 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 39 insertions(+), 1 deletion(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 5c9501af2..2c9938729 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -842,7 +842,45 @@ def __str__(self) -> str: @export class PhysicalLiteral(NumericLiteral): - pass + _unitName: str + + def __init__(self, unitName: str): + super().__init__() + self._unitName = unitName + + @property + def UnitName(self) -> str: + return self._unitName + + def __str__(self) -> str: + return "{value} {unit}".format(value=self._value, unit=self._unitName) + + +@export +class PhysicalIntegerLiteral(PhysicalLiteral): + _value: int + _unitName: str + + def __init__(self, value: int, unitName: str): + super().__init__(unitName) + self._value = value + + @property + def Value(self) -> int: + return self._value + + +@export +class PhysicalFloatingLiteral(PhysicalLiteral): + _value: float + + def __init__(self, value: float, unitName: str): + super().__init__(unitName) + self._value = value + + @property + def Value(self) -> float: + return self._value @export From 23dabbc5121a663397f7bb9b5793b18dff5dbc25 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 21 Jun 2021 19:33:54 +0200 Subject: [PATCH 8/8] Testing Protocol dummy class --- pyVHDLModel/VHDLModel.py | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index 2c9938729..2c35fb9c5 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -43,7 +43,12 @@ # load dependencies from enum import Enum from pathlib import Path -from typing import List, Tuple, Union, Protocol +from typing import List, Tuple, Union +try: + from typing import Protocol +except ImportError: + class Protocol: + pass from pydecor.decorators import export