From 7f26cb1cf0d8ba37eda6d856f99a5d8f52b85db6 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 4 Jan 2021 10:57:31 +0100 Subject: [PATCH 1/5] Prepare for next version v0.8.1. --- doc/conf.py | 2 +- pyVHDLModel/__init__.py | 2 +- setup.py | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/doc/conf.py b/doc/conf.py index ecc42808f..6020ce0ea 100644 --- a/doc/conf.py +++ b/doc/conf.py @@ -37,7 +37,7 @@ def _LatestTagName(): # The full version, including alpha/beta/rc tags version = "0.8" # The short X.Y version. -release = "0.8.0" # The full version, including alpha/beta/rc tags. +release = "0.8.1" # The full version, including alpha/beta/rc tags. try: if _IsUnderGitControl: latestTagName = _LatestTagName()[1:] # remove prefix "v" diff --git a/pyVHDLModel/__init__.py b/pyVHDLModel/__init__.py index 07b5c31dd..2b052dfdd 100644 --- a/pyVHDLModel/__init__.py +++ b/pyVHDLModel/__init__.py @@ -38,4 +38,4 @@ :copyright: Copyright 2007-2021 Patrick Lehmann - Bötzingen, Germany :license: Apache License, Version 2.0 """ -__version__ = "0.8.0" +__version__ = "0.8.1" diff --git a/setup.py b/setup.py index 1123ee1e6..cade737ee 100644 --- a/setup.py +++ b/setup.py @@ -53,7 +53,7 @@ # Assemble all package information setuptools_setup( name=projectName, - version="0.8.0", + version="0.8.1", author="Patrick Lehmann", author_email="Paebbels@gmail.com", From 2989959f34e5ffd9be8621fe987d52b18fbb2ab1 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 4 Jan 2021 11:42:33 +0100 Subject: [PATCH 2/5] Renamed 'Use' to 'PackageReference'. --- pyVHDLModel/VHDLModel.py | 68 +++++++++++++++++++++++----------------- 1 file changed, 40 insertions(+), 28 deletions(-) diff --git a/pyVHDLModel/VHDLModel.py b/pyVHDLModel/VHDLModel.py index ebac4bfc3..72ded2408 100644 --- a/pyVHDLModel/VHDLModel.py +++ b/pyVHDLModel/VHDLModel.py @@ -61,7 +61,7 @@ class ModelEntity: a protected variable :attr:`_parent` is available and a readonly property :attr:`Parent`. """ - _parent: 'ModelEntity' + _parent: 'ModelEntity' #: Reference to a parent entity in the model. def __init__(self): self._parent = None @@ -80,7 +80,7 @@ class NamedEntity: A protected variable :attr:`_name` is available to derived classes as well as a readonly property :attr:`Name` for public access. """ - _name: str + _name: str #: The name of a model entity. def __init__(self, name: str): self._name = name @@ -100,7 +100,7 @@ class LabeledEntity: A protected variable :attr:`_label` is available to derived classes as well as a readonly property :attr:`Label` for public access. """ - _label: str + _label: str #: The label of a model entity. def __init__(self, label: str): self._label = label @@ -118,8 +118,8 @@ class Design(ModelEntity): and analysed. It's the root of this document-object-model (DOM). It contains at least on VHDL library (see :class:`~pyVHDLModel.VHDLModel.Library`). """ - _libraries: List['Library'] #: List of all libraries defined for a design - _documents: List['Document'] #: List of all documents loaded for a design + _libraries: List['Library'] #: List of all libraries defined for a design. + _documents: List['Document'] #: List of all documents loaded for a design. def __init__(self): super().__init__() @@ -242,12 +242,13 @@ def PackageBodies(self) -> List['PackageBody']: @export class Direction(Enum): """ - A ``Direction`` is an enumeration and represents a direction (``to`` or ``downto``) - in a range. + A ``Direction`` is an enumeration and represents a direction in a range + (``to`` or ``downto``). """ To = 0 DownTo = 1 + @export class Mode(Enum): """ @@ -281,6 +282,11 @@ class Class(Enum): class BaseType(ModelEntity, NamedEntity): """``BaseType`` is the base class of all type entities in this model.""" def __init__(self, name: str): + """ + Initializes underlying ``BaseType``. + + :param name: Name of the type. + """ super().__init__() NamedEntity.__init__(self, name) @@ -666,7 +672,7 @@ def Library(self) -> Library: @export -class Use(ModelEntity): +class PackageReference(ModelEntity): _library: Library _package: 'Package' _item: str @@ -703,22 +709,28 @@ def __init__(self, name: str): @export class Context(PrimaryUnit): - _uses: List[Use] + _libraryReferences: List[LibraryReference] + _packageReferences: List[PackageReference] def __init__(self, name): super().__init__(name) - self._uses = [] + self._libraryReferences = [] + self._packageReferences = [] + + @property + def LibraryReferences(self) -> List[LibraryReference]: + return self._libraryReferences @property - def Uses(self) -> List[Use]: - return self._uses + def PackageReferences(self) -> List[PackageReference]: + return self._packageReferences @export class Entity(PrimaryUnit): _libraryReferences: List[LibraryReference] - _uses: List[Use] + _packageReferences: List[PackageReference] _genericItems: List[GenericInterfaceItem] _portItems: List[PortInterfaceItem] _declaredItems: List # FIXME: define liste element type e.g. via Union @@ -728,7 +740,7 @@ def __init__(self, name: str): super().__init__(name) self._libraryReferences = [] - self._uses = [] + self._packageReferences = [] self._genericItems = [] self._portItems = [] self._declaredItems = [] @@ -739,8 +751,8 @@ def LibraryReferences(self) -> List[LibraryReference]: return self._libraryReferences @property - def Uses(self) -> List[Use]: - return self._uses + def PackageReferences(self) -> List[PackageReference]: + return self._packageReferences @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -763,7 +775,7 @@ def BodyItems(self) -> List['ConcurrentStatement']: class Architecture(SecondaryUnit): _entity: Entity _libraryReferences: List[Library] - _uses: List[Use] + _packageReferences: List[PackageReference] _declaredItems: List # FIXME: define liste element type e.g. via Union _bodyItems: List['ConcurrentStatement'] @@ -771,7 +783,7 @@ def __init__(self, name: str): super().__init__(name) self._libraryReferences = [] - self._uses = [] + self._packageReferences = [] self._declaredItems = [] self._bodyItems = [] @@ -784,8 +796,8 @@ def LibraryReferences(self) -> List[Library]: return self._libraryReferences @property - def Uses(self) -> List[Use]: - return self._uses + def PackageReferences(self) -> List[PackageReference]: + return self._packageReferences @property def DeclaredItems(self) -> List: # FIXME: define liste element type e.g. via Union @@ -841,7 +853,7 @@ class Instantiation: @export class Package(PrimaryUnit): _libraryReferences: List[Library] - _uses: List[Use] + _packageReferences: List[PackageReference] _genericItems: List[GenericInterfaceItem] _declaredItems: List @@ -849,7 +861,7 @@ def __init__(self, name: str): super().__init__(name) self._libraryReferences = [] - self._uses = [] + self._packageReferences = [] self._genericItems = [] self._declaredItems = [] @@ -858,8 +870,8 @@ def LibraryReferences(self) -> List[Library]: return self._libraryReferences @property - def Uses(self) -> List[Use]: - return self._uses + def PackageReferences(self) -> List[PackageReference]: + return self._packageReferences @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -874,14 +886,14 @@ def DeclaredItems(self) -> List: class PackageBody(SecondaryUnit): _package: Package _libraryReferences: List[Library] - _uses: List[Use] + _packageReferences: List[PackageReference] _declaredItems: List def __init__(self, name: str): super().__init__(name) self._libraryReferences = [] - self._uses = [] + self._packageReferences = [] self._declaredItems = [] @property @@ -893,8 +905,8 @@ def LibraryReferences(self) -> List[Library]: return self._libraryReferences @property - def Uses(self) -> List[Use]: - return self._uses + def PackageReferences(self) -> List[PackageReference]: + return self._packageReferences @property def DeclaredItems(self) -> List: From c22834a65fcf207f3543da96698ae9496a4664fd Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 4 Jan 2021 12:10:33 +0100 Subject: [PATCH 3/5] More documentation. --- doc/LanguageModel/Miscellaneous.rst | 31 ++++++++++++++++++----------- doc/LanguageModel/index.rst | 13 ++++++++++++ 2 files changed, 32 insertions(+), 12 deletions(-) diff --git a/doc/LanguageModel/Miscellaneous.rst b/doc/LanguageModel/Miscellaneous.rst index cb18e3d4f..13384290b 100644 --- a/doc/LanguageModel/Miscellaneous.rst +++ b/doc/LanguageModel/Miscellaneous.rst @@ -3,10 +3,16 @@ Concepts not defined by VHDL ############################ -Some features required for a holistic language model are not defined in -the VHDL :term:`LRM` (IEEE Std. 1076) or made explicitly implementation +Some features required for a holistic language model are not defined in the VHDL +:term:`LRM` (IEEE Std. 1076). Other features made explicitly implementation specific to the implementer. +.. rubric:: Table of Content + +* :ref:`Design ` +* :ref:`Library ` +* :ref:`Document ` + .. _vhdlmodel-design: Design @@ -72,20 +78,21 @@ is a *primary* design unit like: ``configuration``, ``entity``, ``package`` or -.. _vhdlmodel-sourcefile: +.. _vhdlmodel-document: -Sourcecode File -=============== +Document +======== -A source file contains multiple *design units*. Each design unit listed in a -sourcecode file is a *primary* or `secondary`design unit like: ``configuration``, -``entity``, ``architecture``, ``package``, ``package body`` or ``context``. +A source file (document) contains multiple *design units*. Each design unit +listed in a sourcecode file is a *primary* or *secondary* design unit like: +``configuration``, ``entity``, ``architecture``, ``package``, ``package body`` +or ``context``. Design unit may be preceded by a context made of ``library``, ``use`` and -``context`` statements. These statements are not directly visible in the ``Document`` -object, because design unit contexts are consumed by the design units. See the -``Libraries`` and ``Uses`` fields of each design unit to investigate the consumed -contexts. +``context`` statements. These statements are not directly visible in the +``Document`` object, because design unit contexts are consumed by the design +units. See the ``Libraries`` and ``Uses`` fields of each design unit to +investigate the consumed contexts. **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Document`: diff --git a/doc/LanguageModel/index.rst b/doc/LanguageModel/index.rst index e5f8eb9cd..c93e99c3c 100644 --- a/doc/LanguageModel/index.rst +++ b/doc/LanguageModel/index.rst @@ -3,7 +3,20 @@ VHDL Language Model ################### +.. topic:: Design Goal + + * Clearly named classes that model the semantics of VHDL. + * All language constructs (statements, declarations, specifications, …) have + their own classes. |br| These classes are arranged in a logical hierarchy, + with a single common base-class. + * Child objects shall have a reference to their parent. + * Comments will be associated with a particular code object. + * Easy modifications of the object tree. + +.. rubric:: Elements of the Language Model + .. toctree:: + :maxdepth: 1 Miscellaneous Enumerations From 0726aa52dba3a2e3429bc9524fad52ded9b95211 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Mon, 4 Jan 2021 13:28:04 +0100 Subject: [PATCH 4/5] Added more documentation. --- doc/LanguageModel/DesignUnits.rst | 63 ++++++++++++++------- doc/LanguageModel/Enumerations.rst | 22 +++++-- doc/LanguageModel/Miscellaneous.rst | 7 ++- doc/LanguageModel/SubprogramDefinitions.rst | 14 ++++- 4 files changed, 78 insertions(+), 28 deletions(-) diff --git a/doc/LanguageModel/DesignUnits.rst b/doc/LanguageModel/DesignUnits.rst index 6e24dfa55..9c88c708a 100644 --- a/doc/LanguageModel/DesignUnits.rst +++ b/doc/LanguageModel/DesignUnits.rst @@ -3,21 +3,31 @@ Design Units ############ -* Primary Units +A VHDL design (see :ref:`vhdlmodel-design`) is assembled from *design units*. VHDL distinguishes +between *primary* and *secondary* design units. - * Context - * Configuration - * Entity - * Package +.. rubric:: Table of Content -* Secondary Units +* :ref:`vhdlmodel-primary` - * Architeture - * Package Body + * :ref:`vhdlmodel-context` + * :ref:`vhdlmodel-configuration` + * :ref:`vhdlmodel-entity` + * :ref:`vhdlmodel-package` + +* :ref:`vhdlmodel-secondary` + + * :ref:`vhdlmodel-architeture` + * :ref:`vhdlmodel-packagebody` + + +.. _vhdlmodel-primary: Primary Units ============= +.. _vhdlmodel-context: + Context ------- @@ -25,6 +35,10 @@ Context Write documentation. + + +.. _vhdlmodel-configuration: + Configuration ------------- @@ -32,12 +46,15 @@ Configuration Write documentation. + + +.. _vhdlmodel-entity: + Entity ------ -.. todo:: - - Write documentation. +An ``Entity`` represents a VHDL entity declaration. It has a list of generic and +port items. It can contain a list of declared and body items. **Condensed definition of class** :class:`~pyVHDLModel.VHDLModel.Entity`: @@ -46,7 +63,7 @@ Entity @export class Entity(PrimaryUnit): _libraryReferences: List[LibraryReference] - _uses: List[Use] + _packageReferences: List[PackageReference] _genericItems: List[GenericInterfaceItem] _portItems: List[PortInterfaceItem] _declaredItems: List # FIXME: define liste element type e.g. via Union @@ -58,7 +75,7 @@ Entity def LibraryReferences(self) -> List[LibraryReference]: @property - def Uses(self) -> List[Use]: + def PackageReferences(self) -> List[PackageReference]: @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -74,6 +91,8 @@ Entity +.. _vhdlmodel-package: + Package ------- @@ -88,7 +107,7 @@ Package @export class Package(PrimaryUnit): _libraryReferences: List[Library] - _uses: List[Use] + _packageReferences: List[PackageReference] _genericItems: List[GenericInterfaceItem] _declaredItems: List @@ -98,7 +117,7 @@ Package def LibraryReferences(self) -> List[Library]: @property - def Uses(self) -> List[Use]: + def PackageReferences(self) -> List[PackageReference]: @property def GenericItems(self) -> List[GenericInterfaceItem]: @@ -108,9 +127,13 @@ Package +.. _vhdlmodel-secondary: + Secondary Units =============== +.. _vhdlmodel-architeture: + Architeture ----------- @@ -126,7 +149,7 @@ Architeture class Architecture(SecondaryUnit): _entity: Entity _libraryReferences: List[Library] - _uses: List[Use] + _packageReferences: List[PackageReference] _declaredItems: List # FIXME: define liste element type e.g. via Union _bodyItems: List['ConcurrentStatement'] @@ -139,7 +162,7 @@ Architeture def LibraryReferences(self) -> List[Library]: @property - def Uses(self) -> List[Use]: + def PackageReferences(self) -> List[PackageReference]: @property def DeclaredItems(self) -> List: @@ -149,6 +172,8 @@ Architeture +.. _vhdlmodel-packagebody: + Package Body ------------ @@ -164,7 +189,7 @@ Package Body class PackageBody(SecondaryUnit): _package: Package _libraryReferences: List[Library] - _uses: List[Use] + _packageReferences: List[PackageReference] _declaredItems: List def __init__(self, name: str): @@ -176,7 +201,7 @@ Package Body def LibraryReferences(self) -> List[Library]: @property - def Uses(self) -> List[Use]: + def PackageReferences(self) -> List[PackageReference]: @property def DeclaredItems(self) -> List: diff --git a/doc/LanguageModel/Enumerations.rst b/doc/LanguageModel/Enumerations.rst index f5ed26c8d..cf600196c 100644 --- a/doc/LanguageModel/Enumerations.rst +++ b/doc/LanguageModel/Enumerations.rst @@ -3,16 +3,30 @@ Enumerations ############ +The language model contains some enumerations to express a *kind* of a models entity. -Modes -===== +.. rubric:: Table of Content + +* :ref:`vhdlmodel-mode` +* :ref:`vhdlmodel-objclass` + + + +.. _vhdlmodel-mode: + +Mode +==== .. todo:: Write documentation. -Object Classes -============== + + +.. _vhdlmodel-objclass: + +Object Class +============ .. todo:: diff --git a/doc/LanguageModel/Miscellaneous.rst b/doc/LanguageModel/Miscellaneous.rst index 13384290b..9703a0f38 100644 --- a/doc/LanguageModel/Miscellaneous.rst +++ b/doc/LanguageModel/Miscellaneous.rst @@ -9,9 +9,10 @@ specific to the implementer. .. rubric:: Table of Content -* :ref:`Design ` -* :ref:`Library ` -* :ref:`Document ` +* :ref:`vhdlmodel-design` +* :ref:`vhdlmodel-library` +* :ref:`vhdlmodel-document` + .. _vhdlmodel-design: diff --git a/doc/LanguageModel/SubprogramDefinitions.rst b/doc/LanguageModel/SubprogramDefinitions.rst index ccad17f74..a47f70927 100644 --- a/doc/LanguageModel/SubprogramDefinitions.rst +++ b/doc/LanguageModel/SubprogramDefinitions.rst @@ -3,8 +3,14 @@ Subprogram Declarations ######################## -* Procedure -* Function +.. rubric:: Table of Content + +* :ref:`vhdlmodel-procedure` +* :ref:`vhdlmodel-function` + + + +.. _vhdlmodel-procedure: Procedure ========= @@ -13,6 +19,10 @@ Procedure Write documentation. + + +.. _vhdlmodel-function: + Function ======== From b2accde8bdd6aff02461c349f628a29465dff540 Mon Sep 17 00:00:00 2001 From: Patrick Lehmann Date: Wed, 9 Jun 2021 18:24:31 +0200 Subject: [PATCH 5/5] Minor updates. --- .github/workflows/Release.yml | 3 ++- .github/workflows/Test.yml | 6 ++++-- .gitignore | 8 +++++--- .idea/pyVHDLModel.iml | 2 +- tests/requirements.txt | 6 +++--- 5 files changed, 15 insertions(+), 10 deletions(-) diff --git a/.github/workflows/Release.yml b/.github/workflows/Release.yml index d77c3f8c5..b007cf1fd 100644 --- a/.github/workflows/Release.yml +++ b/.github/workflows/Release.yml @@ -11,7 +11,8 @@ jobs: env: PYTHON: ${{ github.event.client_payload.PYTHON }} steps: - - uses: actions/checkout@v2 + - name: Checkout repository + uses: actions/checkout@v2 with: ref: ${{ github.event.client_payload.ref }} diff --git a/.github/workflows/Test.yml b/.github/workflows/Test.yml index 2c79296af..8a8c4b9e2 100644 --- a/.github/workflows/Test.yml +++ b/.github/workflows/Test.yml @@ -15,7 +15,8 @@ jobs: env: PYTHON: ${{ matrix.python-version }} steps: - - uses: actions/checkout@v2 + - name: Checkout repository + uses: actions/checkout@v2 - name: Setup Python ${{ matrix.python-version }} uses: actions/setup-python@v2 @@ -38,7 +39,8 @@ jobs: env: PYTHON: 3.9 steps: - - uses: actions/checkout@v2 + - name: Checkout repository + uses: actions/checkout@v2 - name: Setup Python ${{ env.PYTHON }} uses: actions/setup-python@v2 diff --git a/.gitignore b/.gitignore index e7423b65d..ed3c5abb7 100644 --- a/.gitignore +++ b/.gitignore @@ -2,14 +2,16 @@ __pycache__/ *.py[cod] -# Python installation packages -dist/ - # Coverage.py .coverage .cov coverage.xml +# setuptools +/build +/dist +/*.egg-info + # Sphinx doc/_build/ doc/pyVHDLModel/**/*.* diff --git a/.idea/pyVHDLModel.iml b/.idea/pyVHDLModel.iml index 4085ce561..f8203ff07 100644 --- a/.idea/pyVHDLModel.iml +++ b/.idea/pyVHDLModel.iml @@ -7,7 +7,7 @@ - + diff --git a/tests/requirements.txt b/tests/requirements.txt index e42ba7a98..b6817b869 100644 --- a/tests/requirements.txt +++ b/tests/requirements.txt @@ -1,8 +1,8 @@ -r ../requirements.txt # Coverage collection -Coverage>=5.3 +Coverage>=5.5 # Test Runner -pytest>=6.2.1 -pytest-cov>=2.10.1 +pytest>=6.2.4 +pytest-cov>=2.12.1