Adding resolution of record element subtypes in packages

VHDL · Jun 7, 2024 · e7bdfe0 · e7bdfe0
1 parent 8086c37
commit e7bdfe0
Showing 1 changed file with 7 additions and 1 deletion.
diff --git a/pyVHDLModel/__init__.py b/pyVHDLModel/__init__.py
@@ -836,7 +836,13 @@ def _LinkItems(package: Package):
 					edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
 					edge["kind"] = ObjectGraphEdgeKind.Subtype
 				elif isinstance(item, RecordType):
-					print(f"record: {item}")
+					# Resolve each elements subtype
+					for element in item._elements:
+						subtype = package._namespace.FindSubtype(element._subtype)
+						element._subtype._reference = subtype
+
+						edge = item._objectVertex.EdgeToVertex(subtype._objectVertex)
+						edge["kind"] = ObjectGraphEdgeKind.Subtype
 				else:
 					print(f"not handled: {item}")