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instructions.py
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instructions.py
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class Instruction:
opcodes=[]
def __init__(self, opcode):
self.opcode = opcode
def __repr__(self):
return "UNK"
def fetch(self, cpu):
return 0 # return parameter byte count (or -1 for jump instructions)
def execute(self, cpu):
return 2 # return cycle count
def nextAddr(addr, off=1):
bank = addr & 0xFF0000
addrlo = addr & 0xFFFF
return bank | (addrlo + off) & 0xFFFF
def read16(addr, cpu):
return cpu.mem.read(addr) | (cpu.mem.read(nextAddr(addr)) << 8)
def read24(addr, cpu):
data = cpu.mem.read(addr); addr = nextAddr(addr)
data |= cpu.mem.read(addr) << 8; addr = nextAddr(addr)
data |= cpu.mem.read(addr) << 16
return data
def getAddr(offset, mode, cpu, is_pb):
if is_pb:
bankreg = cpu.PB
else:
bankreg = cpu.DB
x = cpu.X
y = cpu.Y
# if cpu.get_flag("X"):
# if x & 0x80:
# x |= 0xFF00
# if y & 0x80:
# y |= 0xFF00
if mode == "imm":
return 0 # means nothing to getAddr
elif mode == "abs": # absolute
return (bankreg << 16) | (offset & 0xFFFF)
elif mode == "absl": # absolute long
return offset & 0xFFFFFF
elif mode == "absx": # absolute indexed X
return (bankreg << 16) | ((offset + x) & 0xFFFF)
elif mode == "absy": # absolute indexed Y
return (bankreg << 16) | ((offset + y) & 0xFFFF)
elif mode == "abslx": # absolute long indexed X
return nextAddr(offset, x)
elif mode == "absly": # absolute long indexed Y (possibly unavailable)
return nextAddr(offset, y)
elif mode == "rel": # relative (short) -- 8 bit addition
return (bankreg << 16) | (cpu.PC & 0xFF00) | (((cpu.PC & 0xFF) + offset) & 0xFF)
elif mode == "rell": # relative (long) -- 16 bit addition
return nextAddr(cpu.PC, offset)
elif mode == "dp": # direct page
return (cpu.DP + offset) & 0xFFFF
elif mode == "dpx": # direct page indexed X
return (cpu.DP + offset + x) & 0xFFFF
elif mode == "dpy": # direct page indexed Y
return (cpu.DP + offset + y) & 0xFFFF
elif mode == "absi": # absolute indirect
ind_addr = getAddr(offset, "abs", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ind_data
elif mode == "absil": # absolute indirect long
ind_addr = getAddr(offset, "abs", cpu, is_pb)
ind_data = read24(ind_addr, cpu)
return ind_data
elif mode == "absxi": # absolute (indexed X) indirect
ind_addr = getAddr(offset, "absx", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ind_data
elif mode == "absyi": # absolute (indexed Y) indirect
ind_addr = getAddr(offset, "absy", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ind_data
elif mode == "dpi": # direct page indirect
ind_addr = getAddr(offset, "dp", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ind_data
elif mode == "dpxi": # direct-page (indexed X) indirect
ind_addr = getAddr(offset, "dpx", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ind_data
elif mode == "dpyi": # direct-page (indexed Y) indirect
ind_addr = getAddr(offset, "dpy", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ind_data
elif mode == "dpix": # direct-page indirect, indexed X
ind_addr = getAddr(offset, "dp", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ((ind_data + x) & 0xFFFF)
elif mode == "dpiy": # direct-page indirect, indexed Y
ind_addr = getAddr(offset, "dp", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ((ind_data + y) & 0xFFFF)
elif mode == "dpil": # direct-page indirect long
ind_addr = getAddr(offset, "dp", cpu, is_pb)
ind_data = read24(ind_addr, cpu)
return ind_data
elif mode == "dpixl": # direct-page indirect, indexed X, long
return nextAddr(getAddr(offset, "dpil", cpu, is_pb), x)
elif mode == "dpiyl": # direct-page indirect, indexed Y, long
return nextAddr(getAddr(offset, "dpil", cpu, is_pb), y)
elif mode == "sr": # stack relative
return (offset + cpu.S) & 0xFFFF
elif mode == "srix": # stack relative indirect, indexed X
ind_addr = getAddr(offset, "sr", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ((ind_data + x) & 0xFFFF)
elif mode == "sriy": # stack relative indirect, indexed Y
ind_addr = getAddr(offset, "sr", cpu, is_pb)
ind_data = read16(ind_addr, cpu)
return (bankreg << 16) | ((ind_data + x) & 0xFFFF)
def getAddrFormat(mode):
if mode == 'imm': # 1B
return '#$%02x'
elif mode in ['rel', 'dp']: # 1B
return '$%02x'
elif mode in ['rell', 'abs']: # 2B
return '$%04x'
elif mode == 'absl': # 3B
return '$%06x'
elif mode == 'dpx': # 1B
return '$%02x,X'
elif mode == 'dpy': # 1B
return '$%02x,Y'
elif mode == 'absx': # 2B
return '$%04x,X'
elif mode == 'absy': # 2B
return '$%04x,Y'
elif mode == 'dpi': # 1B
return '($%02x)'
elif mode == 'dpxi': # 1B
return '($%02x,X)'
elif mode == 'dpyi': # 1B
return '($%02x,Y)'
elif mode == 'dpix': # 1B
return '($%02x),X'
elif mode == 'dpiy': # 1B
return '($%02x),Y'
elif mode == 'dpil': # 1B
return '[$%02x]'
elif mode == 'dpixl': # 1B
return '[$%02x],X'
elif mode == 'dpiyl': # 1B
return '[$%02x],Y'
elif mode == 'abslx': # 3B
return '$%06x,X'
elif mode == 'absly': # 3B
return '$%06x,Y'
elif mode == 'sr': # 1B
return '$%02x,S'
elif mode == 'srix': # 1B
return '($%02x,S),X'
elif mode == 'sriy': # 1B
return '($%02x,S),Y'
elif mode == 'absi': # 2B
return '($%04x)'
elif mode == 'absil': # 2B
return '[$%04x]'
elif mode == 'absxi': # 2B
return '($%04x,X)'
elif mode == 'absyi': # 2B
return '($%04x,Y)'
def getParameter(addr, mode, cpu, two_byte, is_pb):
# print("getParameter from %06x mode=%s two_byte=%d use_pb=%d" % (
# addr, mode, two_byte, is_pb))
if mode == 'imm':
if two_byte: # 16-bit immediate
pm = read16(addr, cpu)
return (pm, 2, pm)
else:
pm = cpu.mem.read(addr)
return (pm, 1, pm)
else:
if mode in ['rel', 'dp', 'dpx', 'dpy', 'dpi', 'dpxi', 'dpyi', 'dpix',
'dpiy', 'dpil', 'dpixl', 'dpiyl', 'sr', 'srix', 'sriy']:
# 1-byte addressed/indirect
param = cpu.mem.read(addr)
width = 1
elif mode in ['rell', 'abs', 'absx', 'absy', 'absi', 'absil', 'absxi',
'absyi']:
param = read16(addr, cpu)
width = 2
else:
param = read24(addr, cpu)
width = 3
addr2 = getAddr(param, mode, cpu, is_pb)
if two_byte:
return (read16(addr2, cpu), width, param)
else:
return (cpu.mem.read(addr2), width, param)
def cycles(base, timing, cpu, bound_cross=False, branch_taken=False):
cyc = base
# ^1: +1 for M=0
if 1 in timing and not cpu.get_flag("M"):
cyc += 1
# ^2: +1 if low byte of DP != 0
if 2 in timing and cpu.DP & 0xFF:
cyc += 1
# ^3: +1 if page boundary cross or X=0
if 3 in timing and (bound_cross or not cpu.get_flag("X")):
cyc += 1
# ^4: +2 if M=0
if 4 in timing and not cpu.get_flag("M"):
cyc += 2
# ^5: +1 if branch taken
if 5 in timing and branch_taken:
cyc += 1
# ^6: [emulation mode specific]
# ^7: +1 if in native mode (i.e. always)
if 7 in timing and not cpu.EMU:
cyc += 1
# ^8: +1 if X=0
if 8 in timing and not cpu.get_flag("X"):
cyc += 1
# ^9, ^10: [shutdown instructions]
return cyc
class ArithmeticInstruction(Instruction):
def __init__(self, opcode):
super().__init__(opcode)
self.operand = 0
self.bc = False # boundary cross (^3)
self.op_literal = 0 # actual operand in code (not the value)
#########################
# Override These #
def _name(self):
"What is this opcode called (for disassembly purposes)"
return "[arithmetic]"
def _op(self, a, b):
"What does this opcode do?"
return a + b
def _flags(self):
"""What flags does this opcode affect?
Arithmetic ops (ADC, SUB) affect Z, C, V, and N
Bitwise ops (AND, ORA) affect Z and N only"""
return ["Z", "C", "V", "N"]
# #
#########################
def __repr__(self):
return self._name() + " " + (getAddrFormat(self.opcode_info[self.opcode]['mode']) % self.op_literal)
def fetch(self, cpu):
off = nextAddr(cpu.get_pc())
self.operand, width, param = getParameter(off, \
self.opcode_info[self.opcode]['mode'], cpu, \
not cpu.get_flag("M"), False)
mode = self.opcode_info[self.opcode]['mode']
if mode == 'dpiy': # dpiy
addr = getAddr(param, mode, cpu, False)
self.bc = ((addr & 0xFF) - cpu.Y) & 0xFF00 != 0
elif mode == 'absy': # absy
self.bc = ((param & 0xFF) + cpu.Y) & 0xFF00 != 0
elif mode == 'absx': # absx
self.bc = ((param & 0xFF) + cpu.X) & 0xFF00 != 0
self.op_literal = param
return width
def execute(self, cpu):
fs = self._flags()
for f in fs:
cpu.clear_flag(f)
a = self._op(cpu.A, self.operand)
if cpu.get_flag("M"):
hi = cpu.A & 0x80
cpu.A = a & 0xFF
mask = 0xFF
else:
hi = cpu.A & 0x8000
cpu.A = a & 0xFFFF
mask = 0xFFFF
if cpu.A == 0 and "Z" in fs:
cpu.set_flag("Z")
if a > mask and "C" in fs:
cpu.set_flag("C")
if cpu.A & (mask//2 + 1) and "N" in fs:
cpu.set_flag("N")
if (cpu.A & (mask//2 + 1)) != hi and "V" in fs:
cpu.set_flag("V")
return cycles(self.opcode_info[self.opcode]['bc'], \
self.opcode_info[self.opcode]['timing'], cpu, bound_cross=self.bc)
class ADC(ArithmeticInstruction):
opcodes = [
0x61, 0x63, 0x65, 0x67, 0x69, 0x6D, 0x6F, 0x71, 0x72, 0x73, 0x75, 0x77,
0x79, 0x7D, 0x7F
]
opcode_info = {
0x61: {'name': 'ADC', 'mode': 'dpxi', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x63: {'name': 'ADC', 'mode': 'sr', 'bc': 4, 'width': 1, 'timing': [1]},
0x65: {'name': 'ADC', 'mode': 'dp', 'bc': 3, 'width': 1, 'timing': [1, 2]},
0x67: {'name': 'ADC', 'mode': 'dpil', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x69: {'name': 'ADC', 'mode': 'imm', 'bc': 2, 'width': 0, 'timing': [1]},
0x6D: {'name': 'ADC', 'mode': 'abs', 'bc': 4, 'width': 2, 'timing': [1]},
0x6F: {'name': 'ADC', 'mode': 'absl', 'bc': 5, 'width': 3, 'timing': [1]},
0x71: {'name': 'ADC', 'mode': 'dpiy', 'bc': 5, 'width': 1, 'timing': [1, 2, 3]},
0x72: {'name': 'ADC', 'mode': 'dpi', 'bc': 5, 'width': 1, 'timing': [1, 2]},
0x73: {'name': 'ADC', 'mode': 'sriy', 'bc': 7, 'width': 1, 'timing': [1]},
0x75: {'name': 'ADC', 'mode': 'dpx', 'bc': 4, 'width': 1, 'timing': [1, 2]},
0x77: {'name': 'ADC', 'mode': 'dpiyl', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x79: {'name': 'ADC', 'mode': 'absy', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0x7D: {'name': 'ADC', 'mode': 'absx', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0x7F: {'name': 'ADC', 'mode': 'abslx', 'bc': 5, 'width': 3, 'timing': [1]},
}
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "ADC"
def _op(self, a, b):
return a + b
def _flags(self):
return ["Z", "C", "V", "N"]
class AND(ArithmeticInstruction):
opcodes = [0x21, 0x23, 0x25, 0x27, 0x29, 0x2D, 0x2F, 0x31, 0x32, 0x33, 0x35,
0x37, 0x39, 0x3D, 0x3F]
opcode_info = {
0x21: {'mode': 'dpxi', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x23: {'mode': 'sr', 'bc': 4, 'width': 1, 'timing': [1]},
0x25: {'mode': 'dp', 'bc': 3, 'width': 1, 'timing': [1, 2]},
0x27: {'mode': 'dpil', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x29: {'mode': 'imm', 'bc': 2, 'width': 0, 'timing': [1]},
0x2D: {'mode': 'abs', 'bc': 4, 'width': 2, 'timing': [1]},
0x2F: {'mode': 'absl', 'bc': 5, 'width': 3, 'timing': [1]},
0x31: {'mode': 'dpiy', 'bc': 5, 'width': 1, 'timing': [1, 2, 3]},
0x32: {'mode': 'dpi', 'bc': 5, 'width': 1, 'timing': [1, 2]},
0x33: {'mode': 'sriy', 'bc': 7, 'width': 1, 'timing': [1]},
0x35: {'mode': 'dpx', 'bc': 4, 'width': 1, 'timing': [1, 2]},
0x37: {'mode': 'dpiyl','bc': 6, 'width': 1, 'timing': [1, 2]},
0x39: {'mode': 'absy', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0x3D: {'mode': 'absx', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0x3F: {'mode': 'abslx','bc': 5, 'width': 3, 'timing': [1]}
}
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "AND"
def _op(self, a, b):
return a & b
def _flags(self):
return ["N", "Z"]
class ASL(Instruction):
opcodes = [0x06, 0x0A, 0x0E, 0x16, 0x1E]
opcode_info = {
0x06: {'mode': 'dp', 'base-cycles': 5, 'width': 1, 'timing': [2, 4]},
0x0A: {'mode': 'acc', 'base-cycles': 2, 'width': 0, 'timing': []},
0x0E: {'mode': 'abs', 'base-cycles': 6, 'width': 2, 'timing': [4]},
0x16: {'mode': 'dpx', 'base-cycles': 6, 'width': 1, 'timing': [2, 4]},
0x1E: {'mode': 'absx', 'base-cycles': 7, 'width': 2, 'timing': [4]}
}
def __init__(self, opcode):
super().__init__(opcode)
self.operand = 0
self.op_literal = 0 # actual operand in code (not the value)
def __repr__(self):
if self.opcode == 0x0A:
return "ASL A"
else:
return "ASL " + (getAddrFormat(self.opcode_info[self.opcode]['mode']) % self.op_literal)
def fetch(self, cpu):
if self.opcode == 0x0A:
return 0
off = nextAddr(cpu.get_pc())
if self.opcode_info[self.opcode]['width'] == 1:
param = cpu.mem.read(off)
width = 1
else:
param = read16(off, cpu)
width = 2
mode = self.opcode_info[self.opcode]['mode']
self.addr = getAddr(param, mode, cpu, False)
self.op_literal = param
return width
def _cycles(self, cpu):
cyc = self.opcode_info[self.opcode]['base-cycles']
if 2 in self.opcode_info[self.opcode]['timing'] \
and cpu.DP & 0xFF:
cyc += 1
if 4 in self.opcode_info[self.opcode]['timing'] \
and not cpu.get_flag("M"):
cyc += 2
return cyc
def execute(self, cpu):
cpu.clear_flag("N")
cpu.clear_flag("Z")
cpu.clear_flag("C")
if self.opcode == 0x0A:
# Shift accumulator (8 or 16 bits)
if cpu.get_flag("M"):
if cpu.A & 0x80: cpu.set_flag("C")
cpu.A = (cpu.A << 1) & 0xFF
if cpu.A == 0: cpu.set_flag("Z")
elif cpu.A & 0x80: cpu.set_flag("N")
else:
if cpu.A & 0x8000: cpu.set_flag("C")
cpu.A = (cpu.A << 1) & 0xFFFF
if cpu.A == 0: cpu.set_flag("Z")
elif cpu.A & 0x8000: cpu.set_flag("N")
else:
if cpu.get_flag("M"):
# Shift memory in-place (8 bits)
val = cpu.mem.read(self.addr)
if val & 0x80: cpu.set_flag("C")
val = (val << 1) & 0xFF
cpu.mem.write(self.addr, val)
if val == 0: cpu.set_flag("Z")
elif val & 0x80: cpu.set_flag("N")
else:
val = read16(self.addr, cpu)
if val & 0x8000: cpu.set_flag("C")
val = (val << 1) & 0xFFFF
cpu.mem.write(self.addr, val & 0xFF)
cpu.mem.write(nextAddr(self.addr), (val >> 8) & 0xFF)
if val == 0: cpu.set_flag("Z")
elif val & 0x8000: cpu.set_flag("N")
return cycles(self.opcode_info[self.opcode]['bc'], \
self.opcode_info[self.opcode]['timing'], cpu)
class BranchInstruction(Instruction):
# opcodes = [0x90],
# opcode_info = {
# 0x90: {'mode': 'rel', 'base-cycles': 2, 'width': 1, 'timing': [5, 6]}
# }
def __init__(self, opcode):
super().__init__(opcode)
self.addr = 0
self.op_literal = 0 # actual operand in code (not the value)
def _name(self):
return "[BRANCH]"
def _doBranch(self, cpu):
return False
def __repr__(self):
return self._name() + " " + (getAddrFormat('rel') % self.op_literal)
def fetch(self, cpu):
# always read this for the disasm
self.op_literal = cpu.mem.read(nextAddr(cpu.get_pc()))
if not self._doBranch(cpu):
return 1 # skip this branch
self.addr = getAddr(self.op_literal, 'rel', cpu, True) & 0xFFFF
return -1 # we are branching; don't advance the PC
def execute(self, cpu):
if not self._doBranch(cpu):
return 2 # no branch today
cpu.PC = self.addr # Branch
return 3
class BCC(BranchInstruction):
opcodes = [0x90]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BCC"
def _doBranch(self, cpu):
return not cpu.get_flag("C")
class BCS(BranchInstruction):
opcodes = [0xB0]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BCS"
def _doBranch(self, cpu):
return cpu.get_flag("C")
class BEQ(BranchInstruction):
opcodes = [0xF0]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BEQ"
def _doBranch(self, cpu):
return cpu.get_flag("Z")
class BIT(Instruction): # The weird one. People find this useful in all sorts of ways
opcodes = [0x24, 0x2C, 0x34, 0x3C, 0x89]
opcode_info = {
0x24: {'mode': 'dp', 'base-cycles': 3, 'width': 1, 'timing': [1, 2]},
0x2C: {'mode': 'abs', 'base-cycles': 4, 'width': 2, 'timing': [1]},
0x34: {'mode': 'dpx', 'base-cycles': 4, 'width': 1, 'timing': [1, 2]},
0x3C: {'mode': 'absx', 'base-cycles': 4, 'width': 2, 'timing': [1, 3]},
0x89: {'mode': 'imm', 'base-cycles': 2, 'width': 0, 'timing': [1]}
}
def __init__(self, opcode):
super().__init__(opcode)
self.addr = 0
self.op_literal = 0 # actual operand in code (not the value)
def __repr__(self):
return "BIT " + (getAddrFormat(self.opcode_info[self.opcode]['mode']) % self.op_literal)
def fetch(self, cpu):
off = nextAddr(cpu.get_pc())
inf = self.opcode_info[self.opcode]
self.operand, width, param = getParameter(off, inf['mode'], cpu, \
not cpu.get_flag("M"), False)
if mode == 'absx': # absx
self.bc = ((param & 0xFF) + cpu.X) & 0xFF00 != 0
self.op_literal = param
return width
def execute(self, cpu):
cpu.clear_flag("Z")
cpu.clear_flag("N")
cpu.clear_flag("V")
if self.operand & cpu.A == 0:
cpu.set_flag("Z")
if cpu.get_flag("M"):
if self.operand & 0x80:
cpu.set_flag("N")
if self.operand & 0x40:
cpu.set_flag("V")
else:
if self.operand & 0x8000:
cpu.set_flag("N")
if self.operand & 0x4000:
cpu.set_flag("V")
return cycles(self.opcode_info[self.opcode]['base-cycles'], \
self.opcode_info[self.opcode]['timing'], cpu, bound_cross=self.bc)
class BMI(BranchInstruction):
opcodes = [0x30]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BMI"
def _doBranch(self, cpu):
return cpu.get_flag("N")
class BNE(BranchInstruction):
opcodes = [0xD0]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BNE"
def _doBranch(self, cpu):
return not cpu.get_flag("Z")
class BPL(BranchInstruction):
opcodes = [0x10]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BPL"
def _doBranch(self, cpu):
return not cpu.get_flag("N")
class BRA(BranchInstruction):
opcodes = [0x80]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BRA"
def _doBranch(self, cpu):
return True
class BRK(Instruction):
#####################################################################################
# Unimplemented!
pass
class BRL(Instruction):
opcodes = [0x82]
def __init__(self, opcode):
super().__init__(opcode)
self.addr = 0
self.op_literal = 0 # actual operand in code (not the value)
def __repr__(self):
return "BRL " + (getAddrFormat('rell') % self.op_literal)
def fetch(self, cpu):
# always read this for the disasm
self.op_literal = read16(nextAddr(cpu.get_pc()), cpu)
self.addr = getAddr(self.op_literal, 'rell', cpu, True) & 0xFFFF
return -1 # we are branching; don't advance the PC
def execute(self, cpu):
cpu.PC = self.addr # Branch
return 4
class BVC(BranchInstruction):
opcodes = [0x50]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BVC"
def _doBranch(self, cpu):
return not cpu.get_flag("V")
class BVS(BranchInstruction):
opcodes = [0x70]
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "BVS"
def _doBranch(self, cpu):
return cpu.get_flag("V")
class ClearInst(Instruction):
opcodes = [0x18, 0xD8, 0x58, 0xB8]
opcode_info = {
0x18: {'name': "CLC", 'flag': "C"},
0xD8: {'name': "CLD", 'flag': "D"},
0x58: {'name': "CLI", 'flag': "I"},
0xB8: {'name': "CLV", 'flag': "V"}
}
def __init__(self, opcode):
super().__init__(opcode)
def __repr__(self):
return self.opcode_info[self.opcode]['name']
def fetch(self, cpu):
return 0
def execute(self, cpu):
cpu.clear_flag(self.opcode_info[self.opcode]['flag'])
return 2
class CMP(Instruction):
opcodes = [0xC1, 0xC3, 0xC5, 0xC7, 0xC9, 0xCD, 0xCF, 0xD1, 0xD2, 0xD3, 0xD5,
0xD7, 0xD9, 0xDD, 0xDF, 0xE0, 0xE4, 0xEC, 0xC0, 0xC4, 0xCC]
opcode_info = {
0xC1: {'name': 'CMP', 'mode': 'dpxi', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0xC3: {'name': 'CMP', 'mode': 'sr', 'bc': 4, 'width': 1, 'timing': [1]},
0xC5: {'name': 'CMP', 'mode': 'dp', 'bc': 3, 'width': 1, 'timing': [1, 2]},
0xC7: {'name': 'CMP', 'mode': 'dpil', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0xC9: {'name': 'CMP', 'mode': 'imm', 'bc': 2, 'width': 0, 'timing': [1]},
0xCD: {'name': 'CMP', 'mode': 'abs', 'bc': 4, 'width': 2, 'timing': [1]},
0xCF: {'name': 'CMP', 'mode': 'absl', 'bc': 5, 'width': 3, 'timing': [1]},
0xD1: {'name': 'CMP', 'mode': 'dpiy', 'bc': 5, 'width': 1, 'timing': [1, 2, 3]},
0xD2: {'name': 'CMP', 'mode': 'dpi', 'bc': 5, 'width': 1, 'timing': [1, 2]},
0xD3: {'name': 'CMP', 'mode': 'sriy', 'bc': 7, 'width': 1, 'timing': [1]},
0xD5: {'name': 'CMP', 'mode': 'dpx', 'bc': 4, 'width': 1, 'timing': [1, 2]},
0xD7: {'name': 'CMP', 'mode': 'dpiyl', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0xD9: {'name': 'CMP', 'mode': 'absy', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0xDD: {'name': 'CMP', 'mode': 'absx', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0xDF: {'name': 'CMP', 'mode': 'abslx', 'bc': 5, 'width': 3, 'timing': [1]},
0xE0: {'name': 'CPX', 'mode': 'imm', 'bc': 2, 'width': 0, 'timing': [8]},
0xE4: {'name': 'CPX', 'mode': 'dp', 'bc': 3, 'width': 1, 'timing': [2, 8]},
0xEC: {'name': 'CPX', 'mode': 'abs', 'bc': 4, 'width': 2, 'timing': [8]},
0xC0: {'name': 'CPY', 'mode': 'imm', 'bc': 2, 'width': 0, 'timing': [8]},
0xC4: {'name': 'CPY', 'mode': 'dp', 'bc': 3, 'width': 1, 'timing': [2, 8]},
0xCC: {'name': 'CPY', 'mode': 'abs', 'bc': 4, 'width': 2, 'timing': [8]}
}
def __init__(self, opcode):
super().__init__(opcode)
self.inf = self.opcode_info[self.opcode]
if self.inf['name'] == 'CMP':
self.reg = "A"
elif self.inf['name'] == 'CPX':
self.reg = "X"
else:
self.reg = "Y"
self.op_literal = 0
self.operand = 0
self.bc = False
def __repr__(self):
return self.inf['name'] + " " + (getAddrFormat(self.inf['mode']) % self.op_literal)
def fetch(self, cpu):
# def getParameter(addr, mode, cpu, two_byte, is_pb):
# return (cpu.mem.read(addr2), width, param)
off = nextAddr(cpu.get_pc())
if self.reg == "A":
tb = cpu.get_flag("M")
else:
tb = cpu.get_flag("X")
self.operand, width, param = getParameter(off, self.inf['mode'], cpu, tb, False)
if self.inf['mode'] == 'dpiy': # dpiy
addr = getAddr(param, self.inf['mode'], cpu, False)
self.bc = ((addr & 0xFF) - cpu.Y) & 0xFF00 != 0
elif self.inf['mode'] == 'absy': # absy
self.bc = ((param & 0xFF) + cpu.Y) & 0xFF00 != 0
elif self.inf['mode'] == 'absx': # absx
self.bc = ((param & 0xFF) + cpu.X) & 0xFF00 != 0
self.op_literal = param
return width
def execute(self, cpu):
# CMP acts exactly like SUB but without changing the accumulator
if self.reg == "A": w = not cpu.get_flag("M")
else: w = not cup.get_flag("X")
mask = 0xFFFF if w else 0xFF
hibit = 0x8000 if w else 0x80
if self.reg == "A": val = (cpu.A - self.operand)
elif self.reg == "X": val = (cpu.X - self.operand)
elif self.reg == "Y": val = (cpu.Y - self.operand)
cpu.clear_flag("N")
cpu.clear_flag("Z")
cpu.clear_flag("C")
if val > mask: cpu.set_flag("C")
val &= mask
if val & hibit: cpu.set_flag("N")
if val == 0: cpu.set_flag("Z")
return cycles(self.opcode_info[self.opcode]['bc'], \
self.opcode_info[self.opcode]['timing'], cpu, bound_cross=self.bc)
class COP(Instruction):
#################################################################################
# Unimplemented instruction!
pass
class DEC(Instruction):
opcodes = [0x3A, 0xC6, 0xCE, 0xD6, 0xDE, 0xCA, 0x88, 0x1A, 0xE6, 0xEE, 0xF6,
0xFE, 0xE8, 0xC8]
opcode_info = {
0x3A: {'name': 'DEA', 'mode': 'acc', 'bc': 2, 'width': 0, 'timing': []},
0xC6: {'name': 'DEC', 'mode': 'dp', 'bc': 5, 'width': 1, 'timing': [2, 4]},
0xCE: {'name': 'DEC', 'mode': 'abs', 'bc': 6, 'width': 2, 'timing': [4]},
0xD6: {'name': 'DEC', 'mode': 'dpx', 'bc': 6, 'width': 1, 'timing': [2, 4]},
0xDE: {'name': 'DEC', 'mode': 'absx', 'bc': 7, 'width': 2, 'timing': [4]},
0xCA: {'name': 'DEX', 'mode': 'imp', 'bc': 2, 'width': 0, 'timing': []},
0x88: {'name': 'DEY', 'mode': 'imp', 'bc': 2, 'width': 0, 'timing': []},
0x1A: {'name': 'INA', 'mode': 'acc', 'bc': 2, 'width': 0, 'timing': []},
0xE6: {'name': 'INC', 'mode': 'dp', 'bc': 5, 'width': 1, 'timing': [2, 4]},
0xEE: {'name': 'INC', 'mode': 'abs', 'bc': 6, 'width': 2, 'timing': [4]},
0xF6: {'name': 'INC', 'mode': 'dpx', 'bc': 6, 'width': 1, 'timing': [2, 4]},
0xFE: {'name': 'INC', 'mode': 'absx', 'bc': 7, 'width': 2, 'timing': [4]},
0xE8: {'name': 'INX', 'mode': 'imp', 'bc': 2, 'width': 0, 'timing': []},
0xC8: {'name': 'INY', 'mode': 'imp', 'bc': 2, 'width': 0, 'timing': []},
}
def __init__(self, opcode):
super().__init__(opcode)
self.inf = self.opcode_info[self.opcode]
self.op_literal = 0
self.addr = 0
def __repr__(self):
if self.inf['width'] == 0:
return self.inf['name']
else:
return self.inf['name'] + " " + (getAddrFormat(self.inf['mode']) % self.op_literal)
def fetch(self, cpu):
off = nextAddr(cpu.get_pc())
if self.inf['width'] == 0:
# Register operations don't need fetch
return 0
# non-register modes: [dp, dpx, abs, absx]
if self.inf['width'] == 1:
param = cpu.mem.read(off)
w = 1
else:
param = read16(off)
w = 2
self.addr = getAddr(param, self.inf['mode'], cpu, False)
self.op_literal = param
return w
def _op(self, a):
if 'IN' in self.inf['name']:
return a+1
else:
return a-1
def execute(self, cpu):
if self.inf['name'][2] == 'A': # DEA, INA
mask = 0xFF if cpu.get_flag("M") else 0xFFFF
cpu.A = self._op(cpu.A) & mask
val = cpu.A
elif self.inf['name'][2] == 'X': # DEX
mask = 0xFF if cpu.get_flag("X") else 0xFFFF
cpu.X = self._op(cpu.X) & mask
val = cpu.X
elif self.inf['name'][2] == 'Y': # DEY
mask = 0xFF if cpu.get_flag("X") else 0xFFFF
cpu.Y = self._op(cpu.Y) & mask
val = cpu.Y
else:
if cpu.get_flag("M"):
# 8-bit
mask = 0xFF
val = self._op(cpu.mem.read(self.addr)) & mask
cpu.mem.write(self.addr, val)
else:
mask = 0xFFFF
val = self._op(read16(self.addr, cpu)) & mask
cpu.mem.write(self.addr, val & 0xFF)
cpu.mem.write(self.addr+1, (val >> 8) & 0xFF)
cpu.clear_flag("N")
cpu.clear_flag("Z")
if val & (mask//2 + 1): # mask//2 + 1 => 0x80 or 0x8000
cpu.set_flag("N")
elif val == 0:
cpu.set_flag("Z")
return cycles(self.opcode_info[self.opcode]['bc'], \
self.opcode_info[self.opcode]['timing'], cpu)
class EOR(ArithmeticInstruction):
opcodes = [0x41, 0x43, 0x45, 0x47, 0x49, 0x4D, 0x4F, 0x51, 0x52, 0x53, 0x55,
0x57, 0x59, 0x5D, 0x5F]
opcode_info = {
0x41: {'name': 'EOR', 'mode': 'dpxi', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x43: {'name': 'EOR', 'mode': 'sr', 'bc': 4, 'width': 1, 'timing': [1]},
0x45: {'name': 'EOR', 'mode': 'dp', 'bc': 3, 'width': 1, 'timing': [1, 2]},
0x47: {'name': 'EOR', 'mode': 'dpil', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x49: {'name': 'EOR', 'mode': 'imm', 'bc': 2, 'width': 0, 'timing': [1]},
0x4D: {'name': 'EOR', 'mode': 'abs', 'bc': 4, 'width': 2, 'timing': [1]},
0x4F: {'name': 'EOR', 'mode': 'absl', 'bc': 5, 'width': 3, 'timing': [1]},
0x51: {'name': 'EOR', 'mode': 'dpiy', 'bc': 5, 'width': 1, 'timing': [1, 2, 3]},
0x52: {'name': 'EOR', 'mode': 'dpi', 'bc': 5, 'width': 1, 'timing': [1, 2]},
0x53: {'name': 'EOR', 'mode': 'sriy', 'bc': 7, 'width': 1, 'timing': [1]},
0x55: {'name': 'EOR', 'mode': 'dpx', 'bc': 4, 'width': 1, 'timing': [1, 2]},
0x57: {'name': 'EOR', 'mode': 'dpiyl', 'bc': 6, 'width': 1, 'timing': [1, 2]},
0x59: {'name': 'EOR', 'mode': 'absy', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0x5D: {'name': 'EOR', 'mode': 'absx', 'bc': 4, 'width': 2, 'timing': [1, 3]},
0x5F: {'name': 'EOR', 'mode': 'abslx', 'bc': 5, 'width': 3, 'timing': [1]},
}
def __init__(self, opcode):
super().__init__(opcode)
def _name(self):
return "EOR"
def _op(self, a, b):
return a ^ b
def _flags(self):
return ["N", "Z"]
class JMP(Instruction):
opcodes = [0x4C, 0x5C, 0x6C, 0x7C, 0xDC]
opcode_info = {
0x4C: {'name': 'JMP', 'mode': 'abs', 'bc': 3, 'width': 2, 'timing': []},
0x5C: {'name': 'JML', 'mode': 'absl', 'bc': 4, 'width': 3, 'timing': []},
0x6C: {'name': 'JMP', 'mode': 'absi', 'bc': 5, 'width': 2, 'timing': []},
0x7C: {'name': 'JMP', 'mode': 'absxi', 'bc': 6, 'width': 2, 'timing': []},
0xDC: {'name': 'JML', 'mode': 'absil', 'bc': 6, 'width': 2, 'timing': []},
}
def __init__(self, opcode):
super().__init__(opcode)
self.addr = 0
self.op_literal = 0
self.inf = self.opcode_info[self.opcode]
def __repr__(self):
return self.inf['name'] + " " + (getAddrFormat(self.inf['mode']) % self.op_literal)
def fetch(self, cpu):
off = nextAddr(cpu.get_pc())
if self.inf['width'] == 2:
self.op_literal = read16(off, cpu)
else:
self.op_literal = read24(off, cpu)
self.addr = getAddr(self.op_literal, self.inf['mode'], cpu, True)
return self.inf['width']
def execute(self, cpu):
cpu.PB = (self.addr >> 16) & 0xFF
cpu.PC = self.addr & 0xFFFF
return self.inf['bc']
class JSR(Instruction):
opcodes = [0x20, 0x22, 0xFC]
opcode_info = {
0x20: {'name': 'JSR', 'mode': 'abs', 'bc': 6, 'width': 2, 'timing': []},
0x22: {'name': 'JSL', 'mode': 'absl', 'bc': 8, 'width': 3, 'timing': []},
0xFC: {'name': 'JSR', 'mode': 'absxi', 'bc': 8, 'width': 2, 'timing': []},
}
def __init__(self, opcode):
super().__init__(opcode)
self.addr = 0
self.op_literal = 0
self.inf = self.opcode_info[self.opcode]
def __repr__(self):
return self.inf['name'] + " " + (getAddrFormat(self.inf['mode']) % self.op_literal)
def fetch(self, cpu):
off = nextAddr(cpu.get_pc())
if self.inf['width'] == 2:
self.op_literal = read16(off, cpu)
else:
self.op_literal = read24(off, cpu)
self.addr = getAddr(self.op_literal, self.inf['mode'], cpu, True)
return -1
def execute(self, cpu):