fixup! [TableGen] Support modelInaccessibleMemThroughRegs property fo…

…r TableGen.
Xilinx · Jun 19, 2024 · 1cfe273 · 1cfe273
1 parent 6d1f089
commit 1cfe273
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/llvm/test/TableGen/GlobalISelEmitterInaccessibleMem.td b/llvm/test/TableGen/GlobalISelEmitterInaccessibleMem.td
@@ -28,8 +28,8 @@ def : Pat<(int_intr_1 GPR32:$src),
 // CHECK-NEXT:       GIR_BuildMI, /*InsnID*/0, /*Opcode*/GIMT_Encode2(MyTarget::NOP),
 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/0, // DstI[dst]
 // CHECK-NEXT:       GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/0, /*OpIdx*/2, // src
-// CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       GIR_ConstrainSelectedInstOperands, /*InsnID*/0,
+// CHECK-NEXT:       GIR_EraseFromParent, /*InsnID*/0,
 // CHECK-NEXT:       // GIR_Coverage, 0,
 // CHECK-NEXT:       GIR_Done,
 // CHECK-NEXT:     // Label 0: @[[NEXT_OPCODE_LABEL]]