diff --git a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp
index 53791ad15929..45b940657114 100644
--- a/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp
+++ b/llvm/lib/Target/AIE/AIEInterBlockScheduling.cpp
@@ -830,6 +830,14 @@ void InterBlockScheduling::emitInterBlockTop(BlockState &BS) {
   if (LBS.isPipelined()) {
     auto *DedicatedExit = makeDedicatedLoopExit(Loop, BB);
     if (DedicatedExit == BB) {
+
+      // Trim excedent empty bundles.
+      int LastPosition = BS.TopInsert.size() - 1;
+      while (LastPosition >= 0 && BS.TopInsert[LastPosition].empty()) {
+        BS.TopInsert.pop_back();
+        LastPosition--;
+      }
+
       // If we are in the same BB, just emit.
       emitBundles(BS.TopInsert, DedicatedExit, DedicatedExit->begin(),
                   /*Move=*/false, /*EmitNops=*/false);
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir
index 2990b88b8dec..faf5d88fb6f9 100644
--- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir
+++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/bitwisexor.mir
@@ -51,7 +51,7 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; nopa ; vst wh6, [p2, #32]; nopx ; vbneg_ltz.s8 x3, r25:r24, x1; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    vst wl6, [p2], #64; nopx ; vband x4, x0, x3
+  ; CHECK-NEXT:    nopb ; nopa ; vst wl6, [p2], #64; nopx ; vband x4, x0, x3; nopv
   ; CHECK-NEXT:    vband x5, x1, x2
   ; CHECK-NEXT:    vbor x6, x4, x5
   ; CHECK-NEXT:    vbneg_ltz.s8 x2, r25:r24, x0
@@ -63,9 +63,6 @@
   ; CHECK-NEXT:    vst wh6, [p2, #32]
   ; CHECK-NEXT:    vst wl6, [p2], #64
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir
index 934ad5b340fc..793d9bb52aa2 100644
--- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir
+++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/large-II.mir
@@ -51,7 +51,7 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; lda r7, [p0], #4; st r0, [p1], #4; nopxm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r1, [p1], #4
+  ; CHECK-NEXT:    st r1, [p1], #4; nopx
   ; CHECK-NEXT:    st r2, [p1], #4
   ; CHECK-NEXT:    st r3, [p1], #4
   ; CHECK-NEXT:    st r4, [p1], #4
@@ -59,7 +59,6 @@
   ; CHECK-NEXT:    st r6, [p1], #4
   ; CHECK-NEXT:    st r7, [p1], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir
index e737ec549a59..236f58737c6a 100644
--- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir
+++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-add-store.mir
@@ -42,7 +42,7 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; nopa ; nops ; add r0, r0, #1; nopm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r0, [p0], #4
+  ; CHECK-NEXT:    st r0, [p0], #4; nopx
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    add r0, r0, #1
@@ -50,7 +50,6 @@
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir
index e737ec549a59..236f58737c6a 100644
--- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir
+++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/load-mac-store.mir
@@ -42,7 +42,7 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; nopa ; nops ; add r0, r0, #1; nopm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r0, [p0], #4
+  ; CHECK-NEXT:    st r0, [p0], #4; nopx
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    add r0, r0, #1
@@ -50,7 +50,6 @@
   ; CHECK-NEXT:    add r0, r0, #1
   ; CHECK-NEXT:    st r0, [p0], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr
diff --git a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir
index 5e32b1cb70b4..dd4da83e4766 100644
--- a/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir
+++ b/llvm/test/CodeGen/AIE/aie2/schedule/postpipeliner/small-II.mir
@@ -47,7 +47,7 @@
   ; CHECK-NEXT:  .L_LEnd0:
   ; CHECK-NEXT:    nopb ; lda r3, [p0], #4; st r0, [p1], #4; nopxm ; nopv
   ; CHECK-NEXT:  // %bb.3: // %for.cond.cleanup
-  ; CHECK-NEXT:    st r1, [p1], #4
+  ; CHECK-NEXT:    st r1, [p1], #4; nopx
   ; CHECK-NEXT:    st r2, [p1], #4
   ; CHECK-NEXT:    st r3, [p1], #4
   ; CHECK-NEXT:    st r0, [p1], #4
@@ -55,7 +55,6 @@
   ; CHECK-NEXT:    st r2, [p1], #4
   ; CHECK-NEXT:    st r3, [p1], #4
   ; CHECK-NEXT:    nop
-  ; CHECK-NEXT:    nop
   ; CHECK-NEXT:    .p2align 4
   ; CHECK-NEXT:  .LBB0_4: // %for.cond.cleanup
   ; CHECK-NEXT:    nopa ; ret lr