fixup! [MachinePipeliner] No default SwpMaxStages

Xilinx · Nov 14, 2024 · 547edf0 · 547edf0
1 parent 6b76c28
commit 547edf0
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll b/llvm/test/CodeGen/PowerPC/sms-cpy-1.ll
@@ -1,6 +1,6 @@
 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs\
-; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner 2>&1 | FileCheck %s
+; RUN:       -mcpu=pwr9 --ppc-enable-pipeliner --pipeliner-max-stages=3 2>&1 | FileCheck %s
 
 @.str.28 = external unnamed_addr constant [69 x i8], align 1