diff --git a/llvm/lib/Target/AIE/AIE2InstrPatterns.td b/llvm/lib/Target/AIE/AIE2InstrPatterns.td
index 2d9409264d24..6b78ff98f7b6 100644
--- a/llvm/lib/Target/AIE/AIE2InstrPatterns.td
+++ b/llvm/lib/Target/AIE/AIE2InstrPatterns.td
@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -1092,6 +1092,15 @@ def : PatInaccessibleMem<(int_aie2_v16bf16_to_v16i32 VEC256:$src, mSs:$shft),
 def : PatInaccessibleMem<(int_aie2_clr16f_conf),
           (VCLR_vclr_BF)>;
 
+// AIE does not have a native xor instruction for vector operands.
+// Res = A xor B --> Res = AB' || A'B
+foreach Ty = [v64i8, v32i16, v16i32] in {
+def : Pat<(xor Ty:$src1, Ty:$src2),
+          (VBOR
+            (VBAND (VBNEG_LTZ_S32 Ty:$src1), Ty:$src2),
+            (VBAND (VBNEG_LTZ_S32 Ty:$src2), Ty:$src1))>;
+}
+
 // DIVS
 def : Pat<(int_aie2_divs eR31:$sd_in, eR:$src0, eR:$src1),
           (DIVS eR31:$sd_in, eR:$src0, eR:$src1)>;
diff --git a/llvm/lib/Target/AIE/AIE2LegalizerInfo.cpp b/llvm/lib/Target/AIE/AIE2LegalizerInfo.cpp
index f8aedbfed171..eba6639908b0 100644
--- a/llvm/lib/Target/AIE/AIE2LegalizerInfo.cpp
+++ b/llvm/lib/Target/AIE/AIE2LegalizerInfo.cpp
@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 /// \file
@@ -73,6 +73,13 @@ static LegalityPredicate isValidVectorAIE2(const unsigned TypeIdx) {
   };
 }
 
+static LegalityPredicate vectorSmallerThan(unsigned TypeIdx, unsigned Size) {
+  return [=](const LegalityQuery &Query) {
+    const LLT QueryTy = Query.Types[TypeIdx];
+    return QueryTy.isVector() && QueryTy.getSizeInBits() < Size;
+  };
+}
+
 LegalityPredicate
 negatePredicate(const std::function<bool(const LegalityQuery &)> &Func) {
   return [=](const LegalityQuery &Query) { return !Func(Query); };
@@ -213,17 +220,6 @@ AIE2LegalizerInfo::AIE2LegalizerInfo(const AIE2Subtarget &ST) : AIEHelper(ST) {
       .clampScalar(0, S32, S32);
   // FIXME: (s|z|any)ext s20 to s64 is broken.
 
-  getActionDefinitionsBuilder({G_AND, G_OR})
-      .legalFor({S32})
-      .legalFor(AIE2VectorTypes)
-      .widenScalarToNextPow2(0)
-      .clampScalar(0, S32, S32);
-
-  getActionDefinitionsBuilder(G_XOR)
-      .legalFor({S32})
-      .widenScalarToNextPow2(0)
-      .clampScalar(0, S32, S32);
-
   getActionDefinitionsBuilder(G_SEXT_INREG).custom();
 
   getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
@@ -250,11 +246,34 @@ AIE2LegalizerInfo::AIE2LegalizerInfo(const AIE2Subtarget &ST) : AIEHelper(ST) {
       // patterns.
       .bitcastIf(typeInSet(0, AIE2AccumulatorTypes), bitcastAccToVectorType(0));
 
-  getActionDefinitionsBuilder({G_ADD, G_SUB})
+  getActionDefinitionsBuilder({G_ADD, G_SUB, G_XOR})
       .legalFor({S32})
       .legalFor({V16S32, V32S16, V64S8})
       .widenScalarToNextPow2(0)
-      .clampScalar(0, S32, S32);
+      .clampScalar(0, S32, S32)
+      // AIE ISA supports only 512-bit vector add/sub/xor
+      .clampMaxNumElements(0, S8, 64)
+      .clampMaxNumElements(0, S16, 32)
+      .clampMaxNumElements(0, S32, 16)
+      // moreElements action could have used here, but it generate code more
+      // like scalarization. We can use G_CONCAT_VECTORS and unmerge to do this
+      // more optimally.
+      .customIf(vectorSmallerThan(0, 512));
+
+  getActionDefinitionsBuilder({G_AND, G_OR})
+      .legalFor({S32})
+      .legalFor({V16S32, V32S16, V64S8})
+      .widenScalarToNextPow2(0)
+      .clampScalar(0, S32, S32)
+      // AIE ISA supports only 512-bit vector and/or
+      .clampMaxNumElements(0, S8, 64)
+      .clampMaxNumElements(0, S16, 32)
+      .clampMaxNumElements(0, S32, 16)
+      // moreElements action could have used here, but it generate code more
+      // like scalarization. We can use G_CONCAT_VECTORS and unmerge to do this
+      // more optimally.
+      .customIf(vectorSmallerThan(0, 512))
+      .bitcastIf(typeInSet(0, AIE2AccumulatorTypes), bitcastAccToVectorType(0));
 
   // FIXME: G_SADDE/G_SSUBE doesn't support lowering. To support this properly,
   // the action needs to be implemented
@@ -546,6 +565,12 @@ bool AIE2LegalizerInfo::legalizeCustom(
     return AIEHelper.legalizeG_SEXT_INREG(Helper, MI);
   case TargetOpcode::G_BITCAST:
     return AIEHelper.legalizeG_BITCAST(Helper, MI);
+  case TargetOpcode::G_ADD:
+  case TargetOpcode::G_SUB:
+  case TargetOpcode::G_XOR:
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_OR:
+    return AIEHelper.legalizeBinOp(Helper, MI);
   }
 
   llvm_unreachable("Un-expected custom legalization");
diff --git a/llvm/lib/Target/AIE/AIEBaseInstrPatterns.td b/llvm/lib/Target/AIE/AIEBaseInstrPatterns.td
index 3f12e1d3068f..1b55d703e529 100644
--- a/llvm/lib/Target/AIE/AIEBaseInstrPatterns.td
+++ b/llvm/lib/Target/AIE/AIEBaseInstrPatterns.td
@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 //
@@ -36,36 +36,8 @@ def frameindex_to_targetframeindex : SDNodeXForm<frameindex, [{
 def gi_frameindex_to_targetframeindex : GICustomOperandRenderer<"renderFrameIndex">,
   GISDNodeXFormEquiv<frameindex_to_targetframeindex>;
 
-// VBOR / VBAND
-foreach vec256Ty = [v32i8, v16i16, v8i32] in {
-  def : Pat<(vec256Ty (or VEC256:$src1, VEC256:$src2)),
-            (vec256Ty (EXTRACT_SUBREG (VBOR
-                        (v32i16 (REG_SEQUENCE VEC512, VEC256:$src1, sub_256_lo)),
-                        (v32i16 (REG_SEQUENCE VEC512, VEC256:$src2, sub_256_lo))),
-                       sub_256_lo))>;
-  def : Pat<(vec256Ty (and VEC256:$src1, VEC256:$src2)),
-            (vec256Ty (EXTRACT_SUBREG (VBAND
-                        (v32i16 (REG_SEQUENCE VEC512, VEC256:$src1, sub_256_lo)),
-                        (v32i16 (REG_SEQUENCE VEC512, VEC256:$src2, sub_256_lo))),
-                       sub_256_lo))>;
-}
+// VBOR / VBAND / XOR
 foreach vec512Ty = [v64i8, v32i16, v16i32] in {
   def : Pat<(vec512Ty (or VEC512:$src1, VEC512:$src2)), (VBOR VEC512:$src1, VEC512:$src2)>;
   def : Pat<(vec512Ty (and VEC512:$src1, VEC512:$src2)), (VBAND VEC512:$src1, VEC512:$src2)>;
 }
-foreach vec1024Ty = [v128i8, v64i16, v32i32] in {
-def : Pat<(vec1024Ty (or VEC1024:$src1, VEC1024:$src2)),
-          (REG_SEQUENCE VEC1024,
-                 (VBOR (v16i32 (EXTRACT_SUBREG VEC1024:$src1, sub_512_lo)),
-                       (v16i32 (EXTRACT_SUBREG VEC1024:$src2, sub_512_lo))), sub_512_lo,
-                 (VBOR (v16i32 (EXTRACT_SUBREG VEC1024:$src1, sub_512_hi)),
-                       (v16i32 (EXTRACT_SUBREG VEC1024:$src2, sub_512_hi))), sub_512_hi
-          )>;
-def : Pat<(vec1024Ty (and VEC1024:$src1, VEC1024:$src2)),
-          (REG_SEQUENCE VEC1024,
-                 (VBAND (v16i32 (EXTRACT_SUBREG VEC1024:$src1, sub_512_lo)),
-                        (v16i32 (EXTRACT_SUBREG VEC1024:$src2, sub_512_lo))), sub_512_lo,
-                 (VBAND (v16i32 (EXTRACT_SUBREG VEC1024:$src1, sub_512_hi)),
-                        (v16i32 (EXTRACT_SUBREG VEC1024:$src2, sub_512_hi))), sub_512_hi
-          )>;
-}
diff --git a/llvm/lib/Target/AIE/AIELegalizerHelper.cpp b/llvm/lib/Target/AIE/AIELegalizerHelper.cpp
index c4ffba6db09f..e71a06f1227d 100644
--- a/llvm/lib/Target/AIE/AIELegalizerHelper.cpp
+++ b/llvm/lib/Target/AIE/AIELegalizerHelper.cpp
@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 /// \file
@@ -1306,7 +1306,9 @@ bool AIELegalizerHelper::legalizeBinOp(LegalizerHelper &Helper,
                                        MachineInstr &MI) const {
   assert(MI.getOpcode() == TargetOpcode::G_ADD ||
          MI.getOpcode() == TargetOpcode::G_SUB ||
-         MI.getOpcode() == TargetOpcode::G_XOR);
+         MI.getOpcode() == TargetOpcode::G_XOR ||
+         MI.getOpcode() == TargetOpcode::G_AND ||
+         MI.getOpcode() == TargetOpcode::G_OR);
 
   MachineIRBuilder &MIRBuilder = Helper.MIRBuilder;
   MachineRegisterInfo &MRI = *MIRBuilder.getMRI();
@@ -1314,40 +1316,41 @@ bool AIELegalizerHelper::legalizeBinOp(LegalizerHelper &Helper,
   const Register DstReg = MI.getOperand(0).getReg();
   const LLT DstTy = MRI.getType(DstReg);
   const auto VectorSize = DstTy.getSizeInBits();
+
   assert(DstTy.isVector() && VectorSize < 512 &&
          "Expected vector size less than 512-bits");
   assert(!(512 % VectorSize) && "Vector size should be a multiple of 512");
 
   const Register Src1Reg = MI.getOperand(1).getReg();
   const Register Src2Reg = MI.getOperand(2).getReg();
+
   assert(DstTy == MRI.getType(Src1Reg));
-  Register UndefReg = MRI.createGenericVirtualRegister(DstTy);
-  MIRBuilder.buildUndef(UndefReg);
 
   auto NewVecTy = LLT::fixed_vector(
       512 / DstTy.getElementType().getSizeInBits(), DstTy.getElementType());
-  Register NewDstReg = MRI.createGenericVirtualRegister(NewVecTy);
-  Register NewSrc1Reg = MRI.createGenericVirtualRegister(NewVecTy);
-  Register NewSrc2Reg = MRI.createGenericVirtualRegister(NewVecTy);
 
-  unsigned NumberOfPadElts = (512 / VectorSize) - 1;
-  SmallVector<Register, 8> Regs;
+  const Register UndefReg = MRI.createGenericVirtualRegister(DstTy);
+  MIRBuilder.buildUndef(UndefReg);
 
-  Regs.push_back(Src1Reg);
-  for (unsigned i = 0; i < NumberOfPadElts; ++i)
-    Regs.push_back(UndefReg);
-  MIRBuilder.buildMergeLikeInstr(NewSrc1Reg, Regs);
+  const unsigned NumberOfPadElts = (512 / VectorSize) - 1;
+  auto buildMergeInstr = [&](const Register SrcReg) -> Register {
+    SmallVector<Register, 4> Regs;
+    Regs.push_back(SrcReg);
+    for (unsigned i = 0; i < NumberOfPadElts; i++)
+      Regs.push_back(UndefReg);
+    const Register NewSrcReg = MRI.createGenericVirtualRegister(NewVecTy);
+    MIRBuilder.buildMergeLikeInstr(NewSrcReg, Regs);
+    return NewSrcReg;
+  };
 
-  Regs.clear();
-  Regs.push_back(Src2Reg);
-  for (unsigned i = 0; i < NumberOfPadElts; ++i)
-    Regs.push_back(UndefReg);
-  MIRBuilder.buildMergeLikeInstr(NewSrc2Reg, Regs);
+  const Register NewSrc1Reg = buildMergeInstr(Src1Reg);
+  const Register NewSrc2Reg = buildMergeInstr(Src2Reg);
 
+  const Register NewDstReg = MRI.createGenericVirtualRegister(NewVecTy);
   MIRBuilder.buildInstr(MI.getOpcode(), {NewDstReg}, {NewSrc1Reg, NewSrc2Reg},
                         MI.getFlags());
 
-  Regs.clear();
+  SmallVector<Register, 4> Regs;
   Regs.push_back(DstReg);
   for (unsigned i = 0; i < NumberOfPadElts; ++i)
     Regs.push_back(MRI.createGenericVirtualRegister(DstTy));
diff --git a/llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp b/llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp
index fd29f6369496..e0b423d6ef7f 100644
--- a/llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp
+++ b/llvm/lib/Target/AIE/aie2p/AIE2PLegalizerInfo.cpp
@@ -4,7 +4,7 @@
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
-// (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+// (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
 //
 //===----------------------------------------------------------------------===//
 /// \file
@@ -252,12 +252,6 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST)
       .clampScalar(0, S32, S32);
   // FIXME: (s|z|any)ext s20 to s64 is broken.
 
-  getActionDefinitionsBuilder({G_AND, G_OR})
-      .legalFor({S32})
-      .legalFor(AIE2PVectorTypes)
-      .widenScalarToNextPow2(0)
-      .clampScalar(0, S32, S32);
-
   getActionDefinitionsBuilder(G_SEXT_INREG).custom();
 
   getActionDefinitionsBuilder({G_ASHR, G_LSHR, G_SHL})
@@ -305,7 +299,7 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST)
       .legalFor({V16S32, V32S16, V64S8})
       .widenScalarToNextPow2(0)
       .clampScalar(0, S32, S32)
-      // AIE ISA supports only 512-bit vector add/sub/xor
+      // AIE ISA supports only 512-bit vector add/sub/xor/and/or
       .clampMaxNumElements(0, S8, 64)
       .clampMaxNumElements(0, S16, 32)
       .clampMaxNumElements(0, S32, 16)
@@ -314,6 +308,22 @@ AIE2PLegalizerInfo::AIE2PLegalizerInfo(const AIE2PSubtarget &ST)
       // more optimally.
       .customIf(vectorSmallerThan(0, 512));
 
+  getActionDefinitionsBuilder({G_AND, G_OR})
+      .legalFor({S32})
+      .legalFor({V16S32, V32S16, V64S8})
+      .widenScalarToNextPow2(0)
+      .clampScalar(0, S32, S32)
+      // AIE ISA supports only 512-bit vector and/or
+      .clampMaxNumElements(0, S8, 64)
+      .clampMaxNumElements(0, S16, 32)
+      .clampMaxNumElements(0, S32, 16)
+      // moreElements action could have used here, but it generate code more
+      // like scalarization. We can use G_CONCAT_VECTORS and unmerge to do this
+      // more optimally.
+      .customIf(vectorSmallerThan(0, 512))
+      .bitcastIf(typeInSet(0, {AccV4S64, AccV8S64, AccV16S64}),
+                 bitcastAccToVectorType(0));
+
   // FIXME: G_SADDE/G_SSUBE doesn't support lowering. To support this properly,
   // the action needs to be implemented
   // FIXME: AIE2 has ADC and SBC operations to read the carry.
@@ -668,6 +678,8 @@ bool AIE2PLegalizerInfo::legalizeCustom(
   case TargetOpcode::G_ADD:
   case TargetOpcode::G_SUB:
   case TargetOpcode::G_XOR:
+  case TargetOpcode::G_AND:
+  case TargetOpcode::G_OR:
     return AIEHelper.legalizeBinOp(Helper, MI);
   }
   llvm_unreachable("Un-expected custom legalization");
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vand.mir b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vand.mir
index 81a7d1e45571..e0e1c0112c4f 100644
--- a/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vand.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vand.mir
@@ -4,99 +4,79 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
+
 # RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
----
-name: and_vec_256
-legalized: true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $wl0, $wh1
-    ; CHECK-LABEL: name: and_vec_256
-    ; CHECK: liveins: $wl0, $wh1
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:ewl = COPY $wl0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ewl = COPY $wh1
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec512 = REG_SEQUENCE [[COPY1]], %subreg.sub_256_lo
-    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vec512 = REG_SEQUENCE [[COPY]], %subreg.sub_256_lo
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:mxm = VBAND [[REG_SEQUENCE1]], [[REG_SEQUENCE]]
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ewl = COPY [[VBAND]].sub_256_lo
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY2]]
-    %0:vregbank(<32 x s8>) = COPY $wl0
-    %1:vregbank(<32 x s8>) = COPY $wh1
-    %2:vregbank(<32 x s8>) = G_AND %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<32 x s8>)
-...
 
 ---
-name: and_vec_512
-legalized: true
+name:            test_and_v64s8
+alignment:       16
+legalized:       true
 regBankSelected: true
-body: |
+body:             |
   bb.0:
-    liveins: $x0, $x1
-    ; CHECK-LABEL: name: and_vec_512
-    ; CHECK: liveins: $x0, $x1
+    liveins: $x2, $x4
+
+    ; CHECK-LABEL: name: test_and_v64s8
+    ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x1
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBAND]]
-    %0:vregbank(<64 x s8>) = COPY $x0
-    %1:vregbank(<64 x s8>) = COPY $x1
-    %2:vregbank(<64 x s8>) = G_AND %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<64 x s8>)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x0 = COPY [[VBAND]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<64 x s8>) = COPY $x2
+    %1:vregbank(<64 x s8>) = COPY $x4
+    %2:vregbank(<64 x s8>) = G_AND %1, %0
+    $x0 = COPY %2(<64 x s8>)
+    PseudoRET implicit $lr, implicit $x0
 ...
 
 ---
-name: and_vec_1024
-legalized: true
+name:            test_and_v32s16
+alignment:       16
+legalized:       true
 regBankSelected: true
-body: |
+body:             |
   bb.0:
-    liveins: $y2, $y3
-    ; CHECK-LABEL: name: and_vec_1024
-    ; CHECK: liveins: $y2, $y3
+    liveins: $x2, $x4
+
+    ; CHECK-LABEL: name: test_and_v32s16
+    ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec1024 = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec1024 = COPY $y3
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:exo = COPY [[COPY1]].sub_512_hi
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:exo = COPY [[COPY]].sub_512_hi
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:exo = VBAND [[COPY3]], [[COPY2]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:exe = COPY [[COPY1]].sub_512_lo
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:exe = COPY [[COPY]].sub_512_lo
-    ; CHECK-NEXT: [[VBAND1:%[0-9]+]]:exe = VBAND [[COPY5]], [[COPY4]]
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VBAND1]], %subreg.sub_512_lo, [[VBAND]], %subreg.sub_512_hi
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
-    %0:vregbank(<64 x s16>) = COPY $y2
-    %1:vregbank(<64 x s16>) = COPY $y3
-    %2:vregbank(<64 x s16>) = G_AND %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<64 x s16>)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x0 = COPY [[VBAND]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<32 x s16>) = COPY $x2
+    %1:vregbank(<32 x s16>) = COPY $x4
+    %2:vregbank(<32 x s16>) = G_AND %1, %0
+    $x0 = COPY %2(<32 x s16>)
+    PseudoRET implicit $lr, implicit $x0
 ...
+
 ---
-name: and_vec_1024_v32s32
-legalized: true
+name:            test_and_v16s32
+alignment:       16
+legalized:       true
 regBankSelected: true
-body: |
+body:             |
   bb.0:
-    liveins: $y2, $y3
-    ; CHECK-LABEL: name: and_vec_1024_v32s32
-    ; CHECK: liveins: $y2, $y3
+    liveins: $x2, $x4
+
+    ; CHECK-LABEL: name: test_and_v16s32
+    ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec1024 = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec1024 = COPY $y3
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:exo = COPY [[COPY1]].sub_512_hi
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:exo = COPY [[COPY]].sub_512_hi
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:exo = VBAND [[COPY3]], [[COPY2]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:exe = COPY [[COPY1]].sub_512_lo
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:exe = COPY [[COPY]].sub_512_lo
-    ; CHECK-NEXT: [[VBAND1:%[0-9]+]]:exe = VBAND [[COPY5]], [[COPY4]]
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VBAND1]], %subreg.sub_512_lo, [[VBAND]], %subreg.sub_512_hi
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
-    %0:vregbank(<32 x s32>) = COPY $y2
-    %1:vregbank(<32 x s32>) = COPY $y3
-    %2:vregbank(<32 x s32>) = G_AND %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<32 x s32>)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x0 = COPY [[VBAND]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<16 x s32>) = COPY $x2
+    %1:vregbank(<16 x s32>) = COPY $x4
+    %2:vregbank(<16 x s32>) = G_AND %1, %0
+    $x0 = COPY %2(<16 x s32>)
+    PseudoRET implicit $lr, implicit $x0
 ...
diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-vector-add.mir b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vector-add.mir
similarity index 97%
rename from llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-vector-add.mir
rename to llvm/test/CodeGen/AIE/GlobalISel/inst-select-vector-add.mir
index b348308b5ae7..a276a4f4bb42 100644
--- a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-vector-add.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vector-add.mir
@@ -4,7 +4,7 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 
diff --git a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-vector-sub.mir b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vector-sub.mir
similarity index 97%
rename from llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-vector-sub.mir
rename to llvm/test/CodeGen/AIE/GlobalISel/inst-select-vector-sub.mir
index 3947fdddcef4..6b4a2bb39dbb 100644
--- a/llvm/test/CodeGen/AIE/aie2/GlobalISel/inst-select-vector-sub.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vector-sub.mir
@@ -4,7 +4,7 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vor.mir b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vor.mir
index d674522282d8..b2518e3f4661 100644
--- a/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vor.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vor.mir
@@ -4,100 +4,78 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
 
 ---
-name: or_vec_256
-legalized: true
+name:            test_or_v64s8
+alignment:       16
+legalized:       true
 regBankSelected: true
-body: |
+body:             |
   bb.0:
-    liveins: $wl0, $wh1
-    ; CHECK-LABEL: name: or_vec_256
-    ; CHECK: liveins: $wl0, $wh1
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:ewl = COPY $wl0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:ewl = COPY $wh1
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec512 = REG_SEQUENCE [[COPY1]], %subreg.sub_256_lo
-    ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vec512 = REG_SEQUENCE [[COPY]], %subreg.sub_256_lo
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:mxm = VBOR [[REG_SEQUENCE1]], [[REG_SEQUENCE]]
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:ewl = COPY [[VBOR]].sub_256_lo
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[COPY2]]
-    %0:vregbank(<32 x s8>) = COPY $wl0
-    %1:vregbank(<32 x s8>) = COPY $wh1
-    %2:vregbank(<32 x s8>) = G_OR %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<32 x s8>)
-...
+    liveins: $x2, $x4
 
----
-name: or_vec_512
-legalized: true
-regBankSelected: true
-body: |
-  bb.0:
-    liveins: $x0, $x1
-    ; CHECK-LABEL: name: or_vec_512
-    ; CHECK: liveins: $x0, $x1
+    ; CHECK-LABEL: name: test_or_v64s8
+    ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x0
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x1
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[VBOR]]
-    %0:vregbank(<64 x s8>) = COPY $x0
-    %1:vregbank(<64 x s8>) = COPY $x1
-    %2:vregbank(<64 x s8>) = G_OR %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<64 x s8>)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x0 = COPY [[VBOR]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<64 x s8>) = COPY $x2
+    %1:vregbank(<64 x s8>) = COPY $x4
+    %2:vregbank(<64 x s8>) = G_OR %1, %0
+    $x0 = COPY %2(<64 x s8>)
+    PseudoRET implicit $lr, implicit $x0
 ...
 
 ---
-name: or_vec_1024
-legalized: true
+name:            test_or_v32s16
+alignment:       16
+legalized:       true
 regBankSelected: true
-body: |
+body:             |
   bb.0:
-    liveins: $y2, $y3
-    ; CHECK-LABEL: name: or_vec_1024
-    ; CHECK: liveins: $y2, $y3
+    liveins: $x2, $x4
+
+    ; CHECK-LABEL: name: test_or_v32s16
+    ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec1024 = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec1024 = COPY $y3
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:exo = COPY [[COPY1]].sub_512_hi
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:exo = COPY [[COPY]].sub_512_hi
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:exo = VBOR [[COPY3]], [[COPY2]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:exe = COPY [[COPY1]].sub_512_lo
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:exe = COPY [[COPY]].sub_512_lo
-    ; CHECK-NEXT: [[VBOR1:%[0-9]+]]:exe = VBOR [[COPY5]], [[COPY4]]
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VBOR1]], %subreg.sub_512_lo, [[VBOR]], %subreg.sub_512_hi
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
-    %0:vregbank(<64 x s16>) = COPY $y2
-    %1:vregbank(<64 x s16>) = COPY $y3
-    %2:vregbank(<64 x s16>) = G_OR %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<64 x s16>)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x0 = COPY [[VBOR]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<32 x s16>) = COPY $x2
+    %1:vregbank(<32 x s16>) = COPY $x4
+    %2:vregbank(<32 x s16>) = G_OR %1, %0
+    $x0 = COPY %2(<32 x s16>)
+    PseudoRET implicit $lr, implicit $x0
 ...
+
 ---
-name: or_vec_1024_v32s32
-legalized: true
+name:            test_or_v16s32
+alignment:       16
+legalized:       true
 regBankSelected: true
-body: |
+body:             |
   bb.0:
-    liveins: $y2, $y3
-    ; CHECK-LABEL: name: or_vec_1024_v32s32
-    ; CHECK: liveins: $y2, $y3
+    liveins: $x2, $x4
+
+    ; CHECK-LABEL: name: test_or_v16s32
+    ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec1024 = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec1024 = COPY $y3
-    ; CHECK-NEXT: [[COPY2:%[0-9]+]]:exo = COPY [[COPY1]].sub_512_hi
-    ; CHECK-NEXT: [[COPY3:%[0-9]+]]:exo = COPY [[COPY]].sub_512_hi
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:exo = VBOR [[COPY3]], [[COPY2]]
-    ; CHECK-NEXT: [[COPY4:%[0-9]+]]:exe = COPY [[COPY1]].sub_512_lo
-    ; CHECK-NEXT: [[COPY5:%[0-9]+]]:exe = COPY [[COPY]].sub_512_lo
-    ; CHECK-NEXT: [[VBOR1:%[0-9]+]]:exe = VBOR [[COPY5]], [[COPY4]]
-    ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vec1024 = REG_SEQUENCE [[VBOR1]], %subreg.sub_512_lo, [[VBOR]], %subreg.sub_512_hi
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[REG_SEQUENCE]]
-    %0:vregbank(<32 x s32>) = COPY $y2
-    %1:vregbank(<32 x s32>) = COPY $y3
-    %2:vregbank(<32 x s32>) = G_OR %0:vregbank, %1:vregbank
-    PseudoRET implicit $lr, implicit %2:vregbank(<32 x s32>)
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[COPY1]], [[COPY]]
+    ; CHECK-NEXT: $x0 = COPY [[VBOR]]
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<16 x s32>) = COPY $x2
+    %1:vregbank(<16 x s32>) = COPY $x4
+    %2:vregbank(<16 x s32>) = G_OR %1, %0
+    $x0 = COPY %2(<16 x s32>)
+    PseudoRET implicit $lr, implicit $x0
 ...
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vxor.mir b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vxor.mir
new file mode 100644
index 000000000000..ec692f8488ab
--- /dev/null
+++ b/llvm/test/CodeGen/AIE/GlobalISel/inst-select-vxor.mir
@@ -0,0 +1,133 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+#
+# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
+# See https://llvm.org/LICENSE.txt for license information.
+# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+#
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
+
+# RUN: llc -mtriple aie2 -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck --check-prefix=AIE2 %s
+# RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck --check-prefix=AIE2P %s
+
+---
+name:            test_xor_v64s8
+alignment:       16
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0:
+    liveins: $x2, $x4
+
+    ; AIE2-LABEL: name: test_xor_v64s8
+    ; AIE2: liveins: $x2, $x4
+    ; AIE2-NEXT: {{  $}}
+    ; AIE2-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2-NEXT: [[VBNEG_LTZ_S32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_S32_1:%[0-9]+]]:ers8 = VBNEG_LTZ_S32 [[COPY]]
+    ; AIE2-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_S32_]], [[COPY1]]
+    ; AIE2-NEXT: [[VBNEG_LTZ_S32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_S32_3:%[0-9]+]]:ers8 = VBNEG_LTZ_S32 [[COPY1]]
+    ; AIE2-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_S32_2]], [[COPY]]
+    ; AIE2-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
+    ; AIE2-NEXT: $x0 = COPY [[VBOR]]
+    ; AIE2-NEXT: PseudoRET implicit $lr, implicit $x0
+    ;
+    ; AIE2P-LABEL: name: test_xor_v64s8
+    ; AIE2P: liveins: $x2, $x4
+    ; AIE2P-NEXT: {{  $}}
+    ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2P-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2P-NEXT: [[VBNEG_LTZ_s32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_1:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY]]
+    ; AIE2P-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_s32_]], [[COPY1]]
+    ; AIE2P-NEXT: [[VBNEG_LTZ_s32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_3:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY1]]
+    ; AIE2P-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_s32_2]], [[COPY]]
+    ; AIE2P-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
+    ; AIE2P-NEXT: $x0 = COPY [[VBOR]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<64 x s8>) = COPY $x2
+    %1:vregbank(<64 x s8>) = COPY $x4
+    %2:vregbank(<64 x s8>) = G_XOR %1, %0
+    $x0 = COPY %2(<64 x s8>)
+    PseudoRET implicit $lr, implicit $x0
+...
+
+---
+name:            test_xor_v32s16
+alignment:       16
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0:
+    liveins: $x2, $x4
+
+    ; AIE2-LABEL: name: test_xor_v32s16
+    ; AIE2: liveins: $x2, $x4
+    ; AIE2-NEXT: {{  $}}
+    ; AIE2-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2-NEXT: [[VBNEG_LTZ_S32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_S32_1:%[0-9]+]]:ers8 = VBNEG_LTZ_S32 [[COPY]]
+    ; AIE2-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_S32_]], [[COPY1]]
+    ; AIE2-NEXT: [[VBNEG_LTZ_S32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_S32_3:%[0-9]+]]:ers8 = VBNEG_LTZ_S32 [[COPY1]]
+    ; AIE2-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_S32_2]], [[COPY]]
+    ; AIE2-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
+    ; AIE2-NEXT: $x0 = COPY [[VBOR]]
+    ; AIE2-NEXT: PseudoRET implicit $lr, implicit $x0
+    ;
+    ; AIE2P-LABEL: name: test_xor_v32s16
+    ; AIE2P: liveins: $x2, $x4
+    ; AIE2P-NEXT: {{  $}}
+    ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2P-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2P-NEXT: [[VBNEG_LTZ_s32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_1:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY]]
+    ; AIE2P-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_s32_]], [[COPY1]]
+    ; AIE2P-NEXT: [[VBNEG_LTZ_s32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_3:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY1]]
+    ; AIE2P-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_s32_2]], [[COPY]]
+    ; AIE2P-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
+    ; AIE2P-NEXT: $x0 = COPY [[VBOR]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<32 x s16>) = COPY $x2
+    %1:vregbank(<32 x s16>) = COPY $x4
+    %2:vregbank(<32 x s16>) = G_XOR %1, %0
+    $x0 = COPY %2(<32 x s16>)
+    PseudoRET implicit $lr, implicit $x0
+...
+
+---
+name:            test_xor_v16s32
+alignment:       16
+legalized:       true
+regBankSelected: true
+body:             |
+  bb.0:
+    liveins: $x2, $x4
+
+    ; AIE2-LABEL: name: test_xor_v16s32
+    ; AIE2: liveins: $x2, $x4
+    ; AIE2-NEXT: {{  $}}
+    ; AIE2-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2-NEXT: [[VBNEG_LTZ_S32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_S32_1:%[0-9]+]]:ers8 = VBNEG_LTZ_S32 [[COPY]]
+    ; AIE2-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_S32_]], [[COPY1]]
+    ; AIE2-NEXT: [[VBNEG_LTZ_S32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_S32_3:%[0-9]+]]:ers8 = VBNEG_LTZ_S32 [[COPY1]]
+    ; AIE2-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_S32_2]], [[COPY]]
+    ; AIE2-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
+    ; AIE2-NEXT: $x0 = COPY [[VBOR]]
+    ; AIE2-NEXT: PseudoRET implicit $lr, implicit $x0
+    ;
+    ; AIE2P-LABEL: name: test_xor_v16s32
+    ; AIE2P: liveins: $x2, $x4
+    ; AIE2P-NEXT: {{  $}}
+    ; AIE2P-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
+    ; AIE2P-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
+    ; AIE2P-NEXT: [[VBNEG_LTZ_s32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_1:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY]]
+    ; AIE2P-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_s32_]], [[COPY1]]
+    ; AIE2P-NEXT: [[VBNEG_LTZ_s32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_3:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY1]]
+    ; AIE2P-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_s32_2]], [[COPY]]
+    ; AIE2P-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
+    ; AIE2P-NEXT: $x0 = COPY [[VBOR]]
+    ; AIE2P-NEXT: PseudoRET implicit $lr, implicit $x0
+    %0:vregbank(<16 x s32>) = COPY $x2
+    %1:vregbank(<16 x s32>) = COPY $x4
+    %2:vregbank(<16 x s32>) = G_XOR %1, %0
+    $x0 = COPY %2(<16 x s32>)
+    PseudoRET implicit $lr, implicit $x0
+...
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-and.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-and.mir
index 57fea3b5f57f..b1c3eb64d884 100644
--- a/llvm/test/CodeGen/AIE/GlobalISel/legalize-and.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/legalize-and.mir
@@ -4,7 +4,7 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 
@@ -172,14 +172,41 @@ body:             |
     ; CHECK-LABEL: name: and_vec_256
     ; CHECK: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wl0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $wh3
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<32 x s8>) = G_AND [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AND]](<32 x s8>)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY1]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<64 x s8>) = G_AND [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[AND]](<64 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[UV]](<32 x s8>)
     %0:_(<32 x s8>) = COPY $wl0
     %1:_(<32 x s8>) = COPY $wh3
     %2:_(<32 x s8>) = G_AND %0(<32 x s8>), %1(<32 x s8>)
     PseudoRET implicit $lr, implicit %2
 ...
 
+---
+name:            and_vec_4xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: and_vec_4xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $wh0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s64>) = COPY $wh1
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY]](<4 x s64>), [[DEF]](<4 x s64>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY1]](<4 x s64>), [[DEF]](<4 x s64>)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[CONCAT_VECTORS]](<8 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[CONCAT_VECTORS1]](<8 x s64>)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<8 x s64>) = G_BITCAST [[AND]](<16 x s32>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[BITCAST2]](<8 x s64>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[UV]](<4 x s64>)
+    %0:_(<4 x s64>) = COPY $wh0
+    %1:_(<4 x s64>) = COPY $wh1
+    %2:_(<4 x s64>) = G_AND %0(<4 x s64>), %1(<4 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
+
+
 ---
 name:            and_vec_512
 body:             |
@@ -195,6 +222,24 @@ body:             |
     PseudoRET implicit $lr, implicit %2
 ...
 
+---
+name:            and_vec_8xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: and_vec_8xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s64>) = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s64>) = COPY $x1
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[COPY]](<8 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[COPY1]](<8 x s64>)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<8 x s64>) = G_BITCAST [[AND]](<16 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST2]](<8 x s64>)
+    %0:_(<8 x s64>) = COPY $x0
+    %1:_(<8 x s64>) = COPY $x1
+    %2:_(<8 x s64>) = G_AND %0(<8 x s64>), %1(<8 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
+
 ---
 name:            and_vec_1024
 body:             |
@@ -202,10 +247,36 @@ body:             |
     ; CHECK-LABEL: name: and_vec_1024
     ; CHECK: [[COPY:%[0-9]+]]:_(<64 x s16>) = COPY $y5
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<64 x s16>) = COPY $y2
-    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<64 x s16>) = G_AND [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[AND]](<64 x s16>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s16>), [[UV1:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY]](<64 x s16>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<32 x s16>), [[UV3:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY1]](<64 x s16>)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<32 x s16>) = G_AND [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<32 x s16>) = G_AND [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[AND]](<32 x s16>), [[AND1]](<32 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[CONCAT_VECTORS]](<64 x s16>)
     %0:_(<64 x s16>) = COPY $y5
     %1:_(<64 x s16>) = COPY $y2
     %2:_(<64 x s16>) = G_AND %0(<64 x s16>), %1(<64 x s16>)
     PseudoRET implicit $lr, implicit %2
 ...
+
+---
+name:            and_vec_16xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: and_vec_16xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s64>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s64>) = COPY $y3
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<32 x s32>) = G_BITCAST [[COPY]](<16 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<32 x s32>) = G_BITCAST [[COPY1]](<16 x s64>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[BITCAST]](<32 x s32>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[BITCAST1]](<32 x s32>)
+    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(<16 x s32>) = G_AND [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[AND1:%[0-9]+]]:_(<16 x s32>) = G_AND [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[AND]](<16 x s32>), [[AND1]](<16 x s32>)
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<16 x s64>) = G_BITCAST [[CONCAT_VECTORS]](<32 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST2]](<16 x s64>)
+    %0:_(<16 x s64>) = COPY $y2
+    %1:_(<16 x s64>) = COPY $y3
+    %2:_(<16 x s64>) = G_AND %0(<16 x s64>), %1(<16 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-or.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-or.mir
index 1240f8835524..da8d5fdcbadd 100644
--- a/llvm/test/CodeGen/AIE/GlobalISel/legalize-or.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/legalize-or.mir
@@ -4,7 +4,7 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
 # RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 
@@ -172,14 +172,39 @@ body:             |
     ; CHECK-LABEL: name: or_vec_256
     ; CHECK: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wl0
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $wh3
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<32 x s8>) = G_OR [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[OR]](<32 x s8>)
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY1]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<64 x s8>) = G_OR [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[OR]](<64 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[UV]](<32 x s8>)
     %0:_(<32 x s8>) = COPY $wl0
     %1:_(<32 x s8>) = COPY $wh3
     %2:_(<32 x s8>) = G_OR %0(<32 x s8>), %1(<32 x s8>)
     PseudoRET implicit $lr, implicit %2
 ...
 
+---
+name:            or_vec_4xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: or_vec_4xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s64>) = COPY $wh0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<4 x s64>) = COPY $wh1
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<4 x s64>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY]](<4 x s64>), [[DEF]](<4 x s64>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<8 x s64>) = G_CONCAT_VECTORS [[COPY1]](<4 x s64>), [[DEF]](<4 x s64>)
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[CONCAT_VECTORS]](<8 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[CONCAT_VECTORS1]](<8 x s64>)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s32>) = G_OR [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<8 x s64>) = G_BITCAST [[OR]](<16 x s32>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<4 x s64>), [[UV1:%[0-9]+]]:_(<4 x s64>) = G_UNMERGE_VALUES [[BITCAST2]](<8 x s64>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[UV]](<4 x s64>)
+    %0:_(<4 x s64>) = COPY $wh0
+    %1:_(<4 x s64>) = COPY $wh1
+    %2:_(<4 x s64>) = G_OR %0(<4 x s64>), %1(<4 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
 
 ---
 name:            or_vec_512
@@ -196,6 +221,24 @@ body:             |
     PseudoRET implicit $lr, implicit %2
 ...
 
+---
+name:            or_vec_8xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: or_vec_8xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s64>) = COPY $x0
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s64>) = COPY $x1
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[COPY]](<8 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<16 x s32>) = G_BITCAST [[COPY1]](<8 x s64>)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s32>) = G_OR [[BITCAST]], [[BITCAST1]]
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<8 x s64>) = G_BITCAST [[OR]](<16 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST2]](<8 x s64>)
+    %0:_(<8 x s64>) = COPY $x0
+    %1:_(<8 x s64>) = COPY $x1
+    %2:_(<8 x s64>) = G_OR %0(<8 x s64>), %1(<8 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
+
 ---
 name:            or_vec_1024
 body:             |
@@ -203,10 +246,36 @@ body:             |
     ; CHECK-LABEL: name: or_vec_1024
     ; CHECK: [[COPY:%[0-9]+]]:_(<64 x s16>) = COPY $y5
     ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<64 x s16>) = COPY $y2
-    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<64 x s16>) = G_OR [[COPY]], [[COPY1]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[OR]](<64 x s16>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s16>), [[UV1:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY]](<64 x s16>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<32 x s16>), [[UV3:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY1]](<64 x s16>)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<32 x s16>) = G_OR [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<32 x s16>) = G_OR [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[OR]](<32 x s16>), [[OR1]](<32 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[CONCAT_VECTORS]](<64 x s16>)
     %0:_(<64 x s16>) = COPY $y5
     %1:_(<64 x s16>) = COPY $y2
     %2:_(<64 x s16>) = G_OR %0(<64 x s16>), %1(<64 x s16>)
     PseudoRET implicit $lr, implicit %2
 ...
+
+---
+name:            or_vec_16xs64
+body:             |
+  bb.1.entry:
+    ; CHECK-LABEL: name: or_vec_16xs64
+    ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s64>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s64>) = COPY $y3
+    ; CHECK-NEXT: [[BITCAST:%[0-9]+]]:_(<32 x s32>) = G_BITCAST [[COPY]](<16 x s64>)
+    ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<32 x s32>) = G_BITCAST [[COPY1]](<16 x s64>)
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[BITCAST]](<32 x s32>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[BITCAST1]](<32 x s32>)
+    ; CHECK-NEXT: [[OR:%[0-9]+]]:_(<16 x s32>) = G_OR [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[OR1:%[0-9]+]]:_(<16 x s32>) = G_OR [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[OR]](<16 x s32>), [[OR1]](<16 x s32>)
+    ; CHECK-NEXT: [[BITCAST2:%[0-9]+]]:_(<16 x s64>) = G_BITCAST [[CONCAT_VECTORS]](<32 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit [[BITCAST2]](<16 x s64>)
+    %0:_(<16 x s64>) = COPY $y2
+    %1:_(<16 x s64>) = COPY $y3
+    %2:_(<16 x s64>) = G_OR %0(<16 x s64>), %1(<16 x s64>)
+    PseudoRET implicit $lr, implicit %2
+...
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-add.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-add.mir
index 2e44618f6f48..7beab36c457c 100644
--- a/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-add.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-add.mir
@@ -4,18 +4,45 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
+
 # RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 
 ---
-name:            test_add_v64s8
+name:            test_add_s8_1024
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $y2, $y4
+
+    ; CHECK-LABEL: name: test_add_s8_1024
+    ; CHECK: liveins: $y2, $y4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<128 x s8>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<128 x s8>) = COPY $y4
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<64 x s8>), [[UV1:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY1]](<128 x s8>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<64 x s8>), [[UV3:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY]](<128 x s8>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<64 x s8>) = G_ADD [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<128 x s8>) = G_CONCAT_VECTORS [[ADD]](<64 x s8>), [[ADD1]](<64 x s8>)
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<128 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
+    %1:_(<128 x s8>) = COPY $y2
+    %2:_(<128 x s8>) = COPY $y4
+    %0:_(<128 x s8>) = G_ADD %2, %1
+    $y3 = COPY %0(<128 x s8>)
+    PseudoRET implicit $lr, implicit $y3
+...
+
+---
+name:            test_add_s8_512
 alignment:       16
 body:             |
   bb.1:
     liveins: $x2, $x4
 
-    ; CHECK-LABEL: name: test_add_v64s8
+    ; CHECK-LABEL: name: test_add_s8_512
     ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<64 x s8>) = COPY $x2
@@ -28,17 +55,65 @@ body:             |
     %0:_(<64 x s8>) = G_ADD %2, %1
     $x0 = COPY %0(<64 x s8>)
     PseudoRET implicit $lr, implicit $x0
+...
 
+---
+name:            test_add_s8_256
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $wh2, $wh4
+    ; CHECK-LABEL: name: test_add_s8_256
+    ; CHECK: liveins: $wh2, $wh4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wh2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $wh4
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY1]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[ADD]](<64 x s8>)
+    ; CHECK-NEXT: $wh0 = COPY [[UV]](<32 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
+    %1:_(<32 x s8>) = COPY $wh2
+    %2:_(<32 x s8>) = COPY $wh4
+    %0:_(<32 x s8>) = G_ADD %2, %1
+    $wh0 = COPY %0(<32 x s8>)
+    PseudoRET implicit $lr, implicit $wh0
 ...
 
 ---
-name:            test_add_v32s16
+name:            test_add_s16_1024
 alignment:       16
 body:             |
   bb.1:
-    liveins: $x2, $x4
+    liveins: $y2, $y4
+    ; CHECK-LABEL: name: test_add_s16_1024
+    ; CHECK: liveins: $y2, $y4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<64 x s16>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<64 x s16>) = COPY $y4
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s16>), [[UV1:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY1]](<64 x s16>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<32 x s16>), [[UV3:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY]](<64 x s16>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<32 x s16>) = G_ADD [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<32 x s16>) = G_ADD [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[ADD]](<32 x s16>), [[ADD1]](<32 x s16>)
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<64 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
+    %1:_(<64 x s16>) = COPY $y2
+    %2:_(<64 x s16>) = COPY $y4
+    %0:_(<64 x s16>) = G_ADD %2, %1
+    $y3 = COPY %0(<64 x s16>)
+    PseudoRET implicit $lr, implicit $y3
+...
 
-    ; CHECK-LABEL: name: test_add_v32s16
+---
+name:            test_add_s16_512
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $x2, $x4
+    ; CHECK-LABEL: name: test_add_s16_512
     ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s16>) = COPY $x2
@@ -51,16 +126,65 @@ body:             |
     %0:_(<32 x s16>) = G_ADD %2, %1
     $x0 = COPY %0(<32 x s16>)
     PseudoRET implicit $lr, implicit $x0
+...
 
+---
+name:            test_add_s16_256
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $wh2, $wh4
+    ; CHECK-LABEL: name: test_add_s16_256
+    ; CHECK: liveins: $wh2, $wh4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wh2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s16>) = COPY $wh4
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY1]](<16 x s16>), [[DEF]](<16 x s16>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY]](<16 x s16>), [[DEF]](<16 x s16>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<32 x s16>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[ADD]](<32 x s16>)
+    ; CHECK-NEXT: $wh0 = COPY [[UV]](<16 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
+    %1:_(<16 x s16>) = COPY $wh2
+    %2:_(<16 x s16>) = COPY $wh4
+    %0:_(<16 x s16>) = G_ADD %2, %1
+    $wh0 = COPY %0(<16 x s16>)
+    PseudoRET implicit $lr, implicit $wh0
 ...
+
 ---
-name:            test_add_v16s32
+name:            test_add_s32_1024
 alignment:       16
 body:             |
   bb.1:
-    liveins: $x2, $x4
+    liveins: $y2, $y4
+    ; CHECK-LABEL: name: test_add_s32_1024
+    ; CHECK: liveins: $y2, $y4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s32>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s32>) = COPY $y4
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY1]](<32 x s32>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY]](<32 x s32>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s32>) = G_ADD [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[ADD]](<16 x s32>), [[ADD1]](<16 x s32>)
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<32 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
+    %1:_(<32 x s32>) = COPY $y2
+    %2:_(<32 x s32>) = COPY $y4
+    %0:_(<32 x s32>) = G_ADD %2, %1
+    $y3 = COPY %0(<32 x s32>)
+    PseudoRET implicit $lr, implicit $y3
+...
 
-    ; CHECK-LABEL: name: test_add_v16s32
+---
+name:            test_add_s32_512
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $x2, $x4
+    ; CHECK-LABEL: name: test_add_s32_512
     ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $x2
@@ -73,5 +197,29 @@ body:             |
     %0:_(<16 x s32>) = G_ADD %2, %1
     $x0 = COPY %0(<16 x s32>)
     PseudoRET implicit $lr, implicit $x0
+...
 
+---
+name:            test_add_s32_256
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $wh2, $wh4
+    ; CHECK-LABEL: name: test_add_s32_256
+    ; CHECK: liveins: $wh2, $wh4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $wh2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $wh4
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY1]](<8 x s32>), [[DEF]](<8 x s32>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY]](<8 x s32>), [[DEF]](<8 x s32>)
+    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[ADD]](<16 x s32>)
+    ; CHECK-NEXT: $wh0 = COPY [[UV]](<8 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
+    %1:_(<8 x s32>) = COPY $wh2
+    %2:_(<8 x s32>) = COPY $wh4
+    %0:_(<8 x s32>) = G_ADD %2, %1
+    $wh0 = COPY %0(<8 x s32>)
+    PseudoRET implicit $lr, implicit $wh0
 ...
diff --git a/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-sub.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-sub.mir
index 9fd714859518..99ce4b3874de 100644
--- a/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-sub.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-sub.mir
@@ -4,18 +4,45 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2023-2025 Advanced Micro Devices, Inc. or its affiliates
+
 # RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 
 ---
-name:            test_sub_v64s8
+name:            test_sub_s8_1024
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $y2, $y4
+
+    ; CHECK-LABEL: name: test_sub_s8_1024
+    ; CHECK: liveins: $y2, $y4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<128 x s8>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<128 x s8>) = COPY $y4
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<64 x s8>), [[UV1:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY1]](<128 x s8>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<64 x s8>), [[UV3:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY]](<128 x s8>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<64 x s8>) = G_SUB [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<128 x s8>) = G_CONCAT_VECTORS [[SUB]](<64 x s8>), [[SUB1]](<64 x s8>)
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<128 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
+    %1:_(<128 x s8>) = COPY $y2
+    %2:_(<128 x s8>) = COPY $y4
+    %0:_(<128 x s8>) = G_SUB %2, %1
+    $y3 = COPY %0(<128 x s8>)
+    PseudoRET implicit $lr, implicit $y3
+...
+
+---
+name:            test_sub_s8_512
 alignment:       16
 body:             |
   bb.1:
     liveins: $x2, $x4
 
-    ; CHECK-LABEL: name: test_sub_v64s8
+    ; CHECK-LABEL: name: test_sub_s8_512
     ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<64 x s8>) = COPY $x2
@@ -28,17 +55,65 @@ body:             |
     %0:_(<64 x s8>) = G_SUB %2, %1
     $x0 = COPY %0(<64 x s8>)
     PseudoRET implicit $lr, implicit $x0
+...
 
+---
+name:            test_sub_s8_256
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $wh2, $wh4
+    ; CHECK-LABEL: name: test_sub_s8_256
+    ; CHECK: liveins: $wh2, $wh4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wh2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $wh4
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY1]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[DEF]](<32 x s8>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[SUB]](<64 x s8>)
+    ; CHECK-NEXT: $wh0 = COPY [[UV]](<32 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
+    %1:_(<32 x s8>) = COPY $wh2
+    %2:_(<32 x s8>) = COPY $wh4
+    %0:_(<32 x s8>) = G_SUB %2, %1
+    $wh0 = COPY %0(<32 x s8>)
+    PseudoRET implicit $lr, implicit $wh0
 ...
 
 ---
-name:            test_sub_v32s16
+name:            test_sub_s16_1024
 alignment:       16
 body:             |
   bb.1:
-    liveins: $x2, $x4
+    liveins: $y2, $y4
+    ; CHECK-LABEL: name: test_sub_s16_1024
+    ; CHECK: liveins: $y2, $y4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<64 x s16>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<64 x s16>) = COPY $y4
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s16>), [[UV1:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY1]](<64 x s16>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<32 x s16>), [[UV3:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY]](<64 x s16>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<32 x s16>) = G_SUB [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[SUB]](<32 x s16>), [[SUB1]](<32 x s16>)
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<64 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
+    %1:_(<64 x s16>) = COPY $y2
+    %2:_(<64 x s16>) = COPY $y4
+    %0:_(<64 x s16>) = G_SUB %2, %1
+    $y3 = COPY %0(<64 x s16>)
+    PseudoRET implicit $lr, implicit $y3
+...
 
-    ; CHECK-LABEL: name: test_sub_v32s16
+---
+name:            test_sub_s16_512
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $x2, $x4
+    ; CHECK-LABEL: name: test_sub_s16_512
     ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s16>) = COPY $x2
@@ -51,16 +126,65 @@ body:             |
     %0:_(<32 x s16>) = G_SUB %2, %1
     $x0 = COPY %0(<32 x s16>)
     PseudoRET implicit $lr, implicit $x0
+...
 
+---
+name:            test_sub_s16_256
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $wh2, $wh4
+    ; CHECK-LABEL: name: test_sub_s16_256
+    ; CHECK: liveins: $wh2, $wh4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wh2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s16>) = COPY $wh4
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY1]](<16 x s16>), [[DEF]](<16 x s16>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY]](<16 x s16>), [[DEF]](<16 x s16>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[SUB]](<32 x s16>)
+    ; CHECK-NEXT: $wh0 = COPY [[UV]](<16 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
+    %1:_(<16 x s16>) = COPY $wh2
+    %2:_(<16 x s16>) = COPY $wh4
+    %0:_(<16 x s16>) = G_SUB %2, %1
+    $wh0 = COPY %0(<16 x s16>)
+    PseudoRET implicit $lr, implicit $wh0
 ...
+
 ---
-name:            test_sub_v16s32
+name:            test_sub_s32_1024
 alignment:       16
 body:             |
   bb.1:
-    liveins: $x2, $x4
+    liveins: $y2, $y4
+    ; CHECK-LABEL: name: test_sub_s32_1024
+    ; CHECK: liveins: $y2, $y4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s32>) = COPY $y2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s32>) = COPY $y4
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY1]](<32 x s32>)
+    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY]](<32 x s32>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[UV]], [[UV2]]
+    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s32>) = G_SUB [[UV1]], [[UV3]]
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[SUB]](<16 x s32>), [[SUB1]](<16 x s32>)
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<32 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
+    %1:_(<32 x s32>) = COPY $y2
+    %2:_(<32 x s32>) = COPY $y4
+    %0:_(<32 x s32>) = G_SUB %2, %1
+    $y3 = COPY %0(<32 x s32>)
+    PseudoRET implicit $lr, implicit $y3
+...
 
-    ; CHECK-LABEL: name: test_sub_v16s32
+---
+name:            test_sub_s32_512
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $x2, $x4
+    ; CHECK-LABEL: name: test_sub_s32_512
     ; CHECK: liveins: $x2, $x4
     ; CHECK-NEXT: {{  $}}
     ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s32>) = COPY $x2
@@ -73,5 +197,29 @@ body:             |
     %0:_(<16 x s32>) = G_SUB %2, %1
     $x0 = COPY %0(<16 x s32>)
     PseudoRET implicit $lr, implicit $x0
+...
 
+---
+name:            test_sub_s32_256
+alignment:       16
+body:             |
+  bb.1:
+    liveins: $wh2, $wh4
+    ; CHECK-LABEL: name: test_sub_s32_256
+    ; CHECK: liveins: $wh2, $wh4
+    ; CHECK-NEXT: {{  $}}
+    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $wh2
+    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $wh4
+    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
+    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY1]](<8 x s32>), [[DEF]](<8 x s32>)
+    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY]](<8 x s32>), [[DEF]](<8 x s32>)
+    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
+    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[SUB]](<16 x s32>)
+    ; CHECK-NEXT: $wh0 = COPY [[UV]](<8 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
+    %1:_(<8 x s32>) = COPY $wh2
+    %2:_(<8 x s32>) = COPY $wh4
+    %0:_(<8 x s32>) = G_SUB %2, %1
+    $wh0 = COPY %0(<8 x s32>)
+    PseudoRET implicit $lr, implicit $wh0
 ...
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-xor.mir b/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-xor.mir
similarity index 92%
rename from llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-xor.mir
rename to llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-xor.mir
index cebbe168e264..c726094a9bab 100644
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-xor.mir
+++ b/llvm/test/CodeGen/AIE/GlobalISel/legalize-vector-xor.mir
@@ -4,7 +4,9 @@
 # See https://llvm.org/LICENSE.txt for license information.
 # SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 #
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
+# (c) Copyright 2024-2025 Advanced Micro Devices, Inc. or its affiliates
+
+# RUN: llc -mtriple aie2 -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 # RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
 
 ---
@@ -91,13 +93,13 @@ body:             |
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<64 x s8>) = G_XOR [[UV]], [[UV2]]
     ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<64 x s8>) = G_XOR [[UV1]], [[UV3]]
     ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<128 x s8>) = G_CONCAT_VECTORS [[XOR]](<64 x s8>), [[XOR1]](<64 x s8>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<128 x s8>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<128 x s8>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
     %1:_(<128 x s8>) = COPY $y2
     %2:_(<128 x s8>) = COPY $y4
     %0:_(<128 x s8>) = G_XOR %2, %1
-    $y0 = COPY %0(<128 x s8>)
-    PseudoRET implicit $lr, implicit $y0
+    $y3 = COPY %0(<128 x s8>)
+    PseudoRET implicit $lr, implicit $y3
 
 ...
 
@@ -141,13 +143,13 @@ body:             |
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<32 x s16>) = G_XOR [[UV]], [[UV2]]
     ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<32 x s16>) = G_XOR [[UV1]], [[UV3]]
     ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[XOR]](<32 x s16>), [[XOR1]](<32 x s16>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<64 x s16>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<64 x s16>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
     %1:_(<64 x s16>) = COPY $y2
     %2:_(<64 x s16>) = COPY $y4
     %0:_(<64 x s16>) = G_XOR %2, %1
-    $y0 = COPY %0(<64 x s16>)
-    PseudoRET implicit $lr, implicit $y0
+    $y3 = COPY %0(<64 x s16>)
+    PseudoRET implicit $lr, implicit $y3
 
 ...
 ---
@@ -191,13 +193,13 @@ body:             |
     ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(<16 x s32>) = G_XOR [[UV]], [[UV2]]
     ; CHECK-NEXT: [[XOR1:%[0-9]+]]:_(<16 x s32>) = G_XOR [[UV1]], [[UV3]]
     ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[XOR]](<16 x s32>), [[XOR1]](<16 x s32>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<32 x s32>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
+    ; CHECK-NEXT: $y3 = COPY [[CONCAT_VECTORS]](<32 x s32>)
+    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y3
     %1:_(<32 x s32>) = COPY $y2
     %2:_(<32 x s32>) = COPY $y4
     %0:_(<32 x s32>) = G_XOR %2, %1
-    $y0 = COPY %0(<32 x s32>)
-    PseudoRET implicit $lr, implicit $y0
+    $y3 = COPY %0(<32 x s32>)
+    PseudoRET implicit $lr, implicit $y3
 
 ...
 ---
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-vector-xor.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-vector-xor.mir
deleted file mode 100644
index d74ce4b1896d..000000000000
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/inst-select-vector-xor.mir
+++ /dev/null
@@ -1,93 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-#
-# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
-# See https://llvm.org/LICENSE.txt for license information.
-# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-#
-# (c) Copyright 2023-2024 Advanced Micro Devices, Inc. or its affiliates
-# RUN: llc -mtriple aie2p -run-pass=instruction-select %s -verify-machineinstrs -o - | FileCheck %s
-
----
-name:            test_xor_v64s8
-alignment:       16
-legalized:       true
-regBankSelected: true
-body:             |
-  bb.0:
-    liveins: $x2, $x4
-
-    ; CHECK-LABEL: name: test_xor_v64s8
-    ; CHECK: liveins: $x2, $x4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
-    ; CHECK-NEXT: [[VBNEG_LTZ_s32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_1:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY]]
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_s32_]], [[COPY1]]
-    ; CHECK-NEXT: [[VBNEG_LTZ_s32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_3:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY1]]
-    ; CHECK-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_s32_2]], [[COPY]]
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
-    ; CHECK-NEXT: $x0 = COPY [[VBOR]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
-    %0:vregbank(<64 x s8>) = COPY $x2
-    %1:vregbank(<64 x s8>) = COPY $x4
-    %2:vregbank(<64 x s8>) = G_XOR %1, %0
-    $x0 = COPY %2(<64 x s8>)
-    PseudoRET implicit $lr, implicit $x0
-
-...
----
-name:            test_xor_v32s16
-alignment:       16
-legalized:       true
-regBankSelected: true
-body:             |
-  bb.0:
-    liveins: $x2, $x4
-
-    ; CHECK-LABEL: name: test_xor_v32s16
-    ; CHECK: liveins: $x2, $x4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
-    ; CHECK-NEXT: [[VBNEG_LTZ_s32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_1:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY]]
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_s32_]], [[COPY1]]
-    ; CHECK-NEXT: [[VBNEG_LTZ_s32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_3:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY1]]
-    ; CHECK-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_s32_2]], [[COPY]]
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
-    ; CHECK-NEXT: $x0 = COPY [[VBOR]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
-    %0:vregbank(<32 x s16>) = COPY $x2
-    %1:vregbank(<32 x s16>) = COPY $x4
-    %2:vregbank(<32 x s16>) = G_XOR %1, %0
-    $x0 = COPY %2(<32 x s16>)
-    PseudoRET implicit $lr, implicit $x0
-
-...
----
-name:            test_xor_v16s32
-alignment:       16
-legalized:       true
-regBankSelected: true
-body:             |
-  bb.0:
-    liveins: $x2, $x4
-
-    ; CHECK-LABEL: name: test_xor_v16s32
-    ; CHECK: liveins: $x2, $x4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:vec512 = COPY $x2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vec512 = COPY $x4
-    ; CHECK-NEXT: [[VBNEG_LTZ_s32_:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_1:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY]]
-    ; CHECK-NEXT: [[VBAND:%[0-9]+]]:vec512 = VBAND [[VBNEG_LTZ_s32_]], [[COPY1]]
-    ; CHECK-NEXT: [[VBNEG_LTZ_s32_2:%[0-9]+]]:mxm, dead [[VBNEG_LTZ_s32_3:%[0-9]+]]:mr16_vcompare = VBNEG_LTZ_s32 [[COPY1]]
-    ; CHECK-NEXT: [[VBAND1:%[0-9]+]]:mxm = VBAND [[VBNEG_LTZ_s32_2]], [[COPY]]
-    ; CHECK-NEXT: [[VBOR:%[0-9]+]]:vec512 = VBOR [[VBAND1]], [[VBAND]]
-    ; CHECK-NEXT: $x0 = COPY [[VBOR]]
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $x0
-    %0:vregbank(<16 x s32>) = COPY $x2
-    %1:vregbank(<16 x s32>) = COPY $x4
-    %2:vregbank(<16 x s32>) = G_XOR %1, %0
-    $x0 = COPY %2(<16 x s32>)
-    PseudoRET implicit $lr, implicit $x0
-
-...
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-add.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-add.mir
deleted file mode 100644
index 89f983d8d0bf..000000000000
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-add.mir
+++ /dev/null
@@ -1,160 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-#
-# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
-# See https://llvm.org/LICENSE.txt for license information.
-# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-#
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
-# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
-
----
-name:            test_add_s8_1024
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $y2, $y4
-
-    ; CHECK-LABEL: name: test_add_s8_1024
-    ; CHECK: liveins: $y2, $y4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<128 x s8>) = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<128 x s8>) = COPY $y4
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<64 x s8>), [[UV1:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY1]](<128 x s8>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<64 x s8>), [[UV3:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY]](<128 x s8>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<64 x s8>) = G_ADD [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<128 x s8>) = G_CONCAT_VECTORS [[ADD]](<64 x s8>), [[ADD1]](<64 x s8>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<128 x s8>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
-    %1:_(<128 x s8>) = COPY $y2
-    %2:_(<128 x s8>) = COPY $y4
-    %0:_(<128 x s8>) = G_ADD %2, %1
-    $y0 = COPY %0(<128 x s8>)
-    PseudoRET implicit $lr, implicit $y0
-
-...
-
----
-name:            test_add_s8_256
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $wh2, $wh4
-    ; CHECK-LABEL: name: test_add_s8_256
-    ; CHECK: liveins: $wh2, $wh4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wh2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $wh4
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY1]](<32 x s8>), [[DEF]](<32 x s8>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[DEF]](<32 x s8>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<64 x s8>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[ADD]](<64 x s8>)
-    ; CHECK-NEXT: $wh0 = COPY [[UV]](<32 x s8>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
-    %1:_(<32 x s8>) = COPY $wh2
-    %2:_(<32 x s8>) = COPY $wh4
-    %0:_(<32 x s8>) = G_ADD %2, %1
-    $wh0 = COPY %0(<32 x s8>)
-    PseudoRET implicit $lr, implicit $wh0
-...
----
-name:            test_add_s16_1024
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $y2, $y4
-    ; CHECK-LABEL: name: test_add_s16_1024
-    ; CHECK: liveins: $y2, $y4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<64 x s16>) = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<64 x s16>) = COPY $y4
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s16>), [[UV1:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY1]](<64 x s16>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<32 x s16>), [[UV3:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY]](<64 x s16>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<32 x s16>) = G_ADD [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<32 x s16>) = G_ADD [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[ADD]](<32 x s16>), [[ADD1]](<32 x s16>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<64 x s16>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
-    %1:_(<64 x s16>) = COPY $y2
-    %2:_(<64 x s16>) = COPY $y4
-    %0:_(<64 x s16>) = G_ADD %2, %1
-    $y0 = COPY %0(<64 x s16>)
-    PseudoRET implicit $lr, implicit $y0
-
-...
----
-name:            test_add_s16_256
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $wh2, $wh4
-    ; CHECK-LABEL: name: test_add_s16_256
-    ; CHECK: liveins: $wh2, $wh4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wh2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s16>) = COPY $wh4
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY1]](<16 x s16>), [[DEF]](<16 x s16>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY]](<16 x s16>), [[DEF]](<16 x s16>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<32 x s16>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[ADD]](<32 x s16>)
-    ; CHECK-NEXT: $wh0 = COPY [[UV]](<16 x s16>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
-    %1:_(<16 x s16>) = COPY $wh2
-    %2:_(<16 x s16>) = COPY $wh4
-    %0:_(<16 x s16>) = G_ADD %2, %1
-    $wh0 = COPY %0(<16 x s16>)
-    PseudoRET implicit $lr, implicit $wh0
-
-...
----
-name:            test_add_s32_1024
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $y2, $y4
-    ; CHECK-LABEL: name: test_add_s32_1024
-    ; CHECK: liveins: $y2, $y4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s32>) = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s32>) = COPY $y4
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY1]](<32 x s32>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY]](<32 x s32>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[ADD1:%[0-9]+]]:_(<16 x s32>) = G_ADD [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[ADD]](<16 x s32>), [[ADD1]](<16 x s32>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<32 x s32>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
-    %1:_(<32 x s32>) = COPY $y2
-    %2:_(<32 x s32>) = COPY $y4
-    %0:_(<32 x s32>) = G_ADD %2, %1
-    $y0 = COPY %0(<32 x s32>)
-    PseudoRET implicit $lr, implicit $y0
-
-...
----
-name:            test_add_s32_256
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $wh2, $wh4
-    ; CHECK-LABEL: name: test_add_s32_256
-    ; CHECK: liveins: $wh2, $wh4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $wh2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $wh4
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY1]](<8 x s32>), [[DEF]](<8 x s32>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY]](<8 x s32>), [[DEF]](<8 x s32>)
-    ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(<16 x s32>) = G_ADD [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[ADD]](<16 x s32>)
-    ; CHECK-NEXT: $wh0 = COPY [[UV]](<8 x s32>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
-    %1:_(<8 x s32>) = COPY $wh2
-    %2:_(<8 x s32>) = COPY $wh4
-    %0:_(<8 x s32>) = G_ADD %2, %1
-    $wh0 = COPY %0(<8 x s32>)
-    PseudoRET implicit $lr, implicit $wh0
-
-...
diff --git a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-sub.mir b/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-sub.mir
deleted file mode 100644
index c9eeb4827ad2..000000000000
--- a/llvm/test/CodeGen/AIE/aie2p/GlobalIsel/legalize-vector-sub.mir
+++ /dev/null
@@ -1,160 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
-#
-# This file is licensed under the Apache License v2.0 with LLVM Exceptions.
-# See https://llvm.org/LICENSE.txt for license information.
-# SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
-#
-# (c) Copyright 2024 Advanced Micro Devices, Inc. or its affiliates
-# RUN: llc -mtriple aie2p -run-pass=legalizer %s -verify-machineinstrs -o - | FileCheck %s
-
----
-name:            test_sub_s8_1024
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $y2, $y4
-
-    ; CHECK-LABEL: name: test_sub_s8_1024
-    ; CHECK: liveins: $y2, $y4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<128 x s8>) = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<128 x s8>) = COPY $y4
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<64 x s8>), [[UV1:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY1]](<128 x s8>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<64 x s8>), [[UV3:%[0-9]+]]:_(<64 x s8>) = G_UNMERGE_VALUES [[COPY]](<128 x s8>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<64 x s8>) = G_SUB [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<128 x s8>) = G_CONCAT_VECTORS [[SUB]](<64 x s8>), [[SUB1]](<64 x s8>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<128 x s8>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
-    %1:_(<128 x s8>) = COPY $y2
-    %2:_(<128 x s8>) = COPY $y4
-    %0:_(<128 x s8>) = G_SUB %2, %1
-    $y0 = COPY %0(<128 x s8>)
-    PseudoRET implicit $lr, implicit $y0
-
-...
-
----
-name:            test_sub_s8_256
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $wh2, $wh4
-    ; CHECK-LABEL: name: test_sub_s8_256
-    ; CHECK: liveins: $wh2, $wh4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s8>) = COPY $wh2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s8>) = COPY $wh4
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<32 x s8>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY1]](<32 x s8>), [[DEF]](<32 x s8>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<64 x s8>) = G_CONCAT_VECTORS [[COPY]](<32 x s8>), [[DEF]](<32 x s8>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<64 x s8>) = G_SUB [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s8>), [[UV1:%[0-9]+]]:_(<32 x s8>) = G_UNMERGE_VALUES [[SUB]](<64 x s8>)
-    ; CHECK-NEXT: $wh0 = COPY [[UV]](<32 x s8>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
-    %1:_(<32 x s8>) = COPY $wh2
-    %2:_(<32 x s8>) = COPY $wh4
-    %0:_(<32 x s8>) = G_SUB %2, %1
-    $wh0 = COPY %0(<32 x s8>)
-    PseudoRET implicit $lr, implicit $wh0
-...
----
-name:            test_sub_s16_1024
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $y2, $y4
-    ; CHECK-LABEL: name: test_sub_s16_1024
-    ; CHECK: liveins: $y2, $y4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<64 x s16>) = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<64 x s16>) = COPY $y4
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<32 x s16>), [[UV1:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY1]](<64 x s16>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<32 x s16>), [[UV3:%[0-9]+]]:_(<32 x s16>) = G_UNMERGE_VALUES [[COPY]](<64 x s16>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<32 x s16>) = G_SUB [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<64 x s16>) = G_CONCAT_VECTORS [[SUB]](<32 x s16>), [[SUB1]](<32 x s16>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<64 x s16>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
-    %1:_(<64 x s16>) = COPY $y2
-    %2:_(<64 x s16>) = COPY $y4
-    %0:_(<64 x s16>) = G_SUB %2, %1
-    $y0 = COPY %0(<64 x s16>)
-    PseudoRET implicit $lr, implicit $y0
-
-...
----
-name:            test_sub_s16_256
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $wh2, $wh4
-    ; CHECK-LABEL: name: test_sub_s16_256
-    ; CHECK: liveins: $wh2, $wh4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s16>) = COPY $wh2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<16 x s16>) = COPY $wh4
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<16 x s16>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY1]](<16 x s16>), [[DEF]](<16 x s16>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<32 x s16>) = G_CONCAT_VECTORS [[COPY]](<16 x s16>), [[DEF]](<16 x s16>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<32 x s16>) = G_SUB [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s16>), [[UV1:%[0-9]+]]:_(<16 x s16>) = G_UNMERGE_VALUES [[SUB]](<32 x s16>)
-    ; CHECK-NEXT: $wh0 = COPY [[UV]](<16 x s16>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
-    %1:_(<16 x s16>) = COPY $wh2
-    %2:_(<16 x s16>) = COPY $wh4
-    %0:_(<16 x s16>) = G_SUB %2, %1
-    $wh0 = COPY %0(<16 x s16>)
-    PseudoRET implicit $lr, implicit $wh0
-
-...
----
-name:            test_sub_s32_1024
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $y2, $y4
-    ; CHECK-LABEL: name: test_sub_s32_1024
-    ; CHECK: liveins: $y2, $y4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<32 x s32>) = COPY $y2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<32 x s32>) = COPY $y4
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<16 x s32>), [[UV1:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY1]](<32 x s32>)
-    ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<16 x s32>), [[UV3:%[0-9]+]]:_(<16 x s32>) = G_UNMERGE_VALUES [[COPY]](<32 x s32>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[UV]], [[UV2]]
-    ; CHECK-NEXT: [[SUB1:%[0-9]+]]:_(<16 x s32>) = G_SUB [[UV1]], [[UV3]]
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<32 x s32>) = G_CONCAT_VECTORS [[SUB]](<16 x s32>), [[SUB1]](<16 x s32>)
-    ; CHECK-NEXT: $y0 = COPY [[CONCAT_VECTORS]](<32 x s32>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $y0
-    %1:_(<32 x s32>) = COPY $y2
-    %2:_(<32 x s32>) = COPY $y4
-    %0:_(<32 x s32>) = G_SUB %2, %1
-    $y0 = COPY %0(<32 x s32>)
-    PseudoRET implicit $lr, implicit $y0
-
-...
----
-name:            test_sub_s32_256
-alignment:       16
-body:             |
-  bb.1:
-    liveins: $wh2, $wh4
-    ; CHECK-LABEL: name: test_sub_s32_256
-    ; CHECK: liveins: $wh2, $wh4
-    ; CHECK-NEXT: {{  $}}
-    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s32>) = COPY $wh2
-    ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<8 x s32>) = COPY $wh4
-    ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(<8 x s32>) = G_IMPLICIT_DEF
-    ; CHECK-NEXT: [[CONCAT_VECTORS:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY1]](<8 x s32>), [[DEF]](<8 x s32>)
-    ; CHECK-NEXT: [[CONCAT_VECTORS1:%[0-9]+]]:_(<16 x s32>) = G_CONCAT_VECTORS [[COPY]](<8 x s32>), [[DEF]](<8 x s32>)
-    ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(<16 x s32>) = G_SUB [[CONCAT_VECTORS]], [[CONCAT_VECTORS1]]
-    ; CHECK-NEXT: [[UV:%[0-9]+]]:_(<8 x s32>), [[UV1:%[0-9]+]]:_(<8 x s32>) = G_UNMERGE_VALUES [[SUB]](<16 x s32>)
-    ; CHECK-NEXT: $wh0 = COPY [[UV]](<8 x s32>)
-    ; CHECK-NEXT: PseudoRET implicit $lr, implicit $wh0
-    %1:_(<8 x s32>) = COPY $wh2
-    %2:_(<8 x s32>) = COPY $wh4
-    %0:_(<8 x s32>) = G_SUB %2, %1
-    $wh0 = COPY %0(<8 x s32>)
-    PseudoRET implicit $lr, implicit $wh0
-
-...
diff --git a/llvm/test/CodeGen/AIE/vector_and_or.ll b/llvm/test/CodeGen/AIE/vector_and_or.ll
index 5f351d4aaa56..e3f316ff9a23 100644
--- a/llvm/test/CodeGen/AIE/vector_and_or.ll
+++ b/llvm/test/CodeGen/AIE/vector_and_or.ll
@@ -65,8 +65,8 @@ define dso_local noundef <32 x i32> @_Z8test_andDv32_iS_(<32 x i32> noundef %a,
 ; AIE2-NEXT:    nopb ; nopa ; nops ; ret lr ; nopm ; nopv
 ; AIE2-NEXT:    nopx // Delay Slot 5
 ; AIE2-NEXT:    nop // Delay Slot 4
-; AIE2-NEXT:    vband x5, x9, x7 // Delay Slot 3
-; AIE2-NEXT:    vband x4, x8, x6 // Delay Slot 2
+; AIE2-NEXT:    vband x4, x8, x6 // Delay Slot 3
+; AIE2-NEXT:    vband x5, x9, x7 // Delay Slot 2
 ; AIE2-NEXT:    nop // Delay Slot 1
 ;
 ; AIE2P-LABEL: _Z8test_andDv32_iS_:
@@ -75,8 +75,8 @@ define dso_local noundef <32 x i32> @_Z8test_andDv32_iS_(<32 x i32> noundef %a,
 ; AIE2P-NEXT:    nopa ; nopb ; nops ; ret lr; nopm ; nopv
 ; AIE2P-NEXT:    nopx // Delay Slot 5
 ; AIE2P-NEXT:    nop // Delay Slot 4
-; AIE2P-NEXT:    vband x5, x9, x7 // Delay Slot 3
-; AIE2P-NEXT:    vband x4, x8, x6 // Delay Slot 2
+; AIE2P-NEXT:    vband x4, x8, x6 // Delay Slot 3
+; AIE2P-NEXT:    vband x5, x9, x7 // Delay Slot 2
 ; AIE2P-NEXT:    nop // Delay Slot 1
 entry:
   %and = and <32 x i32> %b, %a
@@ -140,8 +140,8 @@ define dso_local noundef <32 x i32> @_Z7test_orDv32_iS_(<32 x i32> noundef %a, <
 ; AIE2-NEXT:    nopb ; nopa ; nops ; ret lr ; nopm ; nopv
 ; AIE2-NEXT:    nopx // Delay Slot 5
 ; AIE2-NEXT:    nop // Delay Slot 4
-; AIE2-NEXT:    vbor x5, x9, x7 // Delay Slot 3
-; AIE2-NEXT:    vbor x4, x8, x6 // Delay Slot 2
+; AIE2-NEXT:    vbor x4, x8, x6 // Delay Slot 3
+; AIE2-NEXT:    vbor x5, x9, x7 // Delay Slot 2
 ; AIE2-NEXT:    nop // Delay Slot 1
 ;
 ; AIE2P-LABEL: _Z7test_orDv32_iS_:
@@ -150,8 +150,8 @@ define dso_local noundef <32 x i32> @_Z7test_orDv32_iS_(<32 x i32> noundef %a, <
 ; AIE2P-NEXT:    nopa ; nopb ; nops ; ret lr; nopm ; nopv
 ; AIE2P-NEXT:    nopx // Delay Slot 5
 ; AIE2P-NEXT:    nop // Delay Slot 4
-; AIE2P-NEXT:    vbor x5, x9, x7 // Delay Slot 3
-; AIE2P-NEXT:    vbor x4, x8, x6 // Delay Slot 2
+; AIE2P-NEXT:    vbor x4, x8, x6 // Delay Slot 3
+; AIE2P-NEXT:    vbor x5, x9, x7 // Delay Slot 2
 ; AIE2P-NEXT:    nop // Delay Slot 1
 entry:
   %or = or <32 x i32> %b, %a