GitHub - YibaiMeng/pyinhdl: Embedded Python snippets in VHDL/Verilog

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Embedded Python snippets in VHDL/Verilog

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
README		README
pyinhdl.py		pyinhdl.py

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See the source code for detailed docs.


TODO:

1. Makefile like checking timestamps of files, so that unchanged files aren't regenerated?
2. A sensible way of sharing context between files?
3. Useful utilities?
4. Deal with "`"s that have possible legitimate use?