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### Plugins | ||
* [GHDL plugin](https://github.com/ghdl/ghdl-yosys-plugin) VHDL synthesis based on GHDL (linux-x64, darwin-x64 and darwin-arm64 platforms only) | ||
* [Slang plugin](https://github.com/povik/yosys-slang) SystemVerilog synthesis based on Slang | ||
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### Formal Tools | ||
* [sby (formerly SymbiYosys)](https://github.com/YosysHQ/sby) a front-end driver program for Yosys-based formal hardware verification flows. | ||
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