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Per IRC discussion, we've figured out (the hard way!) that the format of opcodes you upload directly to the JTAG port of ECP5/MachXO2 are different from what's listed in the datasheet. The programming manual descriptions (at least for MachXO2 programming, page 51-52) appear to be for SPI/I2C primary and secondary formats, not for JTAG programming. Specifically:
Opcode parameters (the 24-bit info field after the opcode) may or may not be transferred. If they are transferred over JTAG, only the bytes that vary appear to be transferred. Constant values, like 00 00 00 for many opcodes, or 00 00 01, for LSC_PROG_INCR_NV, are not sent.
Some commands have undocumented parameters corresponding to the 24-bit info field when sent over JTAG (ISC_ENABLE/LSC_INIT_ADDRESS).
There exists an LSC_BITSTREAM_BURST opcode which encapsulates a bitstream and commands in the SPI/I2C format.
In the medium term, it would be nice to document the differences in format (and make more clear that semantics of bitstream opcodes themselves are a mix of IEEE 1532 (ISC_) and Lattice extensions to 1532 (LSC_); note that ISC_ENABLE is permitted by the spec to target a data register, but doesn't have to.
The text was updated successfully, but these errors were encountered:
Per IRC discussion, we've figured out (the hard way!) that the format of opcodes you upload directly to the JTAG port of ECP5/MachXO2 are different from what's listed in the datasheet. The programming manual descriptions (at least for MachXO2 programming, page 51-52) appear to be for SPI/I2C primary and secondary formats, not for JTAG programming. Specifically:
00 00 00
for many opcodes, or00 00 01
, forLSC_PROG_INCR_NV
, are not sent.ISC_ENABLE
/LSC_INIT_ADDRESS
).LSC_BITSTREAM_BURST
opcode which encapsulates a bitstream and commands in the SPI/I2C format.In the medium term, it would be nice to document the differences in format (and make more clear that semantics of bitstream opcodes themselves are a mix of IEEE 1532 (
ISC_
) and Lattice extensions to 1532 (LSC_
); note thatISC_ENABLE
is permitted by the spec to target a data register, but doesn't have to.The text was updated successfully, but these errors were encountered: