From 0f13fc6bc771b5ac8908414a4db2e4c22bc29def Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@yosyshq.com>
Date: Wed, 16 Oct 2024 13:55:50 +0200
Subject: [PATCH 1/3] fix lookup of mangled path names

---
 sbysrc/sby_design.py                |  4 +-
 tests/regression/vhdl_hier_path.sby | 96 +++++++++++++++++++++++++++++
 2 files changed, 98 insertions(+), 2 deletions(-)
 create mode 100644 tests/regression/vhdl_hier_path.sby

diff --git a/sbysrc/sby_design.py b/sbysrc/sby_design.py
index 185ed449..ffb827c1 100644
--- a/sbysrc/sby_design.py
+++ b/sbysrc/sby_design.py
@@ -146,12 +146,12 @@ def find_property(self, path, cell_name, trans_dict=dict()):
         path_iter = iter(path)
 
         mod = next(path_iter).translate(trans)
-        if self.name != mod:
+        if self.name.translate(trans) != mod:
             raise ValueError(f"{self.name} is not the first module in hierarchical path {pretty_path(path)}.")
 
         mod_hier = self
         for mod in path_iter:
-            mod_hier = next((v for k, v in mod_hier.submodules.items() if mod == k.translate(trans)), None)
+            mod_hier = next((v for k, v in mod_hier.submodules.items() if mod.translate(trans) == k.translate(trans)), None)
             if not mod_hier:
                 raise KeyError(f"Could not find {pretty_path(path)} in design hierarchy!")
 
diff --git a/tests/regression/vhdl_hier_path.sby b/tests/regression/vhdl_hier_path.sby
new file mode 100644
index 00000000..cbc78908
--- /dev/null
+++ b/tests/regression/vhdl_hier_path.sby
@@ -0,0 +1,96 @@
+[options]
+mode bmc
+depth 1
+expect fail
+
+[engines]
+smtbmc
+
+[script]
+verific -vhdl subsub.vhd
+verific -vhdl sub.vhd
+verific -vhdl top.vhd
+hierarchy -top top
+hierarchy -top \\sub(p=41)\(rtl)
+
+[file top.vhd]
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity top is
+  port (
+    a : in integer
+  );
+end entity;
+
+architecture rtl of top is
+component sub is
+  generic (
+    p : integer
+  );
+  port (
+    a : in integer
+  );
+end component;
+begin
+  sub_i: sub
+    generic map (
+      p => 41
+    )
+    port map (
+      a => a
+    );
+end architecture;
+
+[file sub.vhd]
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity sub is
+  generic (
+    p : integer := 99
+  );
+  port (
+    a : in integer
+  );
+end entity;
+
+architecture rtl of sub is
+component subsub is
+  generic (
+    p : integer
+  );
+  port (
+    a : in integer
+  );
+end component;
+begin
+  subsub_i: subsub
+    generic map (
+      p => p + 1
+    )
+    port map (
+      a => a
+    );
+end architecture;
+
+[file subsub.vhd]
+library ieee;
+use ieee.std_logic_1164.all;
+use ieee.numeric_std.all;
+
+entity subsub is
+  generic (
+    p : integer := 99
+  );
+  port (
+    a : in integer
+  );
+end entity;
+
+architecture rtl of subsub is
+begin
+  assert (p > a);
+end architecture;

From e84cc443bd4e73b939fd7818b6dcc8521bac44f8 Mon Sep 17 00:00:00 2001
From: "N. Engelhardt" <nak@yosyshq.com>
Date: Wed, 16 Oct 2024 15:05:02 +0200
Subject: [PATCH 2/3] add non-verific name mangling regression test

---
 tests/regression/verilog_hier_path.sby | 27 ++++++++++++++++++++++++++
 tests/regression/vhdl_hier_path.sby    |  1 +
 2 files changed, 28 insertions(+)
 create mode 100644 tests/regression/verilog_hier_path.sby

diff --git a/tests/regression/verilog_hier_path.sby b/tests/regression/verilog_hier_path.sby
new file mode 100644
index 00000000..fcb45c74
--- /dev/null
+++ b/tests/regression/verilog_hier_path.sby
@@ -0,0 +1,27 @@
+[options]
+mode bmc
+depth 1
+expect fail
+
+[engines]
+smtbmc
+
+[script]
+read_verilog -formal sub.v
+read_verilog -formal top.v
+prep -top \\(foo)
+
+[file top.v]
+module \\(foo) (input a);
+    always @* begin
+        assert_foo: assert (a);
+    end
+    \\(bar) \\(bar)=i= (.a(a));
+endmodule
+
+[file sub.v]
+module \\(bar) (input a);
+    always @* begin
+        assert_bar: assert (a);
+    end
+endmodule
diff --git a/tests/regression/vhdl_hier_path.sby b/tests/regression/vhdl_hier_path.sby
index cbc78908..7b8c64ca 100644
--- a/tests/regression/vhdl_hier_path.sby
+++ b/tests/regression/vhdl_hier_path.sby
@@ -12,6 +12,7 @@ verific -vhdl sub.vhd
 verific -vhdl top.vhd
 hierarchy -top top
 hierarchy -top \\sub(p=41)\(rtl)
+prep
 
 [file top.vhd]
 library ieee;

From 94d1d0aa2f9a8432269571c321cacf0b8a4c78db Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 16 Oct 2024 17:14:42 +0200
Subject: [PATCH 3/3] enable extensions

---
 .github/workflows/ci.yml | 1 +
 1 file changed, 1 insertion(+)

diff --git a/.github/workflows/ci.yml b/.github/workflows/ci.yml
index 4ea7a442..ebb11f5a 100644
--- a/.github/workflows/ci.yml
+++ b/.github/workflows/ci.yml
@@ -44,6 +44,7 @@ jobs:
           echo "ENABLE_VERIFIC := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_EDIF := 1" >> Makefile.conf
           echo "ENABLE_VERIFIC_LIBERTY := 1" >> Makefile.conf
+          echo "ENABLE_VERIFIC_YOSYSHQ_EXTENSIONS := 1" >> Makefile.conf
           echo "ENABLE_CCACHE := 1" >> Makefile.conf
           make -j${{ env.procs }}
           make install DESTDIR=${GITHUB_WORKSPACE}/.local PREFIX=