From 09f01168fb4ea1219505fd58169a6a965382ade3 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Mon, 18 Sep 2023 21:38:50 +0000 Subject: [PATCH] rtlil: Speeds up Yosys by 17% This PR speeds up by roughly 17% across a wide spectrum of designs tested at Google. Particularly for the mux generation pass. Co-authored-by: Rasmus Larsen Signed-off-by: Ethan Mahintorabi --- kernel/rtlil.cc | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-) diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc index 51d02091308..1b57af60acb 100644 --- a/kernel/rtlil.cc +++ b/kernel/rtlil.cc @@ -4031,16 +4031,20 @@ void RTLIL::SigSpec::replace(const RTLIL::SigSpec &pattern, const RTLIL::SigSpec unpack(); other->unpack(); + dict pattern_to_with; for (int i = 0; i < GetSize(pattern.bits_); i++) { if (pattern.bits_[i].wire != NULL) { - for (int j = 0; j < GetSize(bits_); j++) { - if (bits_[j] == pattern.bits_[i]) { - other->bits_[j] = with.bits_[i]; - } - } + pattern_to_with.emplace(pattern.bits_[i], i); } } + for (int j = 0; j < GetSize(bits_); j++) { + auto it = pattern_to_with.find(bits_[j]); + if (it != pattern_to_with.end()) { + other->bits_[j] = with.bits_[it->second]; + } + } + other->check(); }