From 0a37c2a301f3518df0d3a9ced7b2b9477b4fe9a0 Mon Sep 17 00:00:00 2001
From: Rasmus Munk Larsen <rmlarsen@google.com>
Date: Thu, 5 Oct 2023 17:01:42 -0700
Subject: [PATCH] Fix translation bug: The old code really checks for the
 presense of a node, not an edge in glift and flatten. Add back statement that
 inserts nodes in order in opt_expr.cc.

---
 kernel/utils.h            | 8 +-------
 passes/cmds/glift.cc      | 2 +-
 passes/opt/opt_expr.cc    | 1 +
 passes/techmap/flatten.cc | 2 +-
 4 files changed, 4 insertions(+), 9 deletions(-)

diff --git a/kernel/utils.h b/kernel/utils.h
index 255f875c3f8..5a1279ef01c 100644
--- a/kernel/utils.h
+++ b/kernel/utils.h
@@ -174,11 +174,7 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
 
 	void edge(T left, T right) { edge(node(left), node(right)); }
 
-	bool has_edges(const T &node)
-	{
-		auto it = node_to_index.find(node);
-		return it == node_to_index.end() || !edges[it->second].empty();
-	}
+	bool has_node(const T &node) { return node_to_index.find(node) != node_to_index.end(); }
 
 	bool sort()
 	{
@@ -192,8 +188,6 @@ template <typename T, typename C = std::less<T>, typename OPS = hash_ops<T>> cla
 		std::vector<bool> marked_cells(edges.size(), false);
 		std::vector<bool> active_cells(edges.size(), false);
 		std::vector<int> active_stack;
-
-		marked_cells.reserve(edges.size());
 		sorted.reserve(edges.size());
 
 		for (const auto &it : node_to_index)
diff --git a/passes/cmds/glift.cc b/passes/cmds/glift.cc
index faa4289e3a9..8553b02a541 100644
--- a/passes/cmds/glift.cc
+++ b/passes/cmds/glift.cc
@@ -582,7 +582,7 @@ struct GliftPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (!topo_modules.has_edges(tpl))
+					if (!topo_modules.has_node(tpl))
 						worklist.push_back(tpl);
 					topo_modules.edge(tpl, module);
 					non_top_modules.insert(cell->type);
diff --git a/passes/opt/opt_expr.cc b/passes/opt/opt_expr.cc
index 7331d72a6fd..3eadd35c6af 100644
--- a/passes/opt/opt_expr.cc
+++ b/passes/opt/opt_expr.cc
@@ -424,6 +424,7 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
 						for (auto &bit : sig)
 							outbit_to_cell[bit].insert(cell);
 				}
+                        cells.node(cell);
 		}
 
         // Build the graph for the topological sort.
diff --git a/passes/techmap/flatten.cc b/passes/techmap/flatten.cc
index f49589b826c..4ddc4aff1fa 100644
--- a/passes/techmap/flatten.cc
+++ b/passes/techmap/flatten.cc
@@ -312,7 +312,7 @@ struct FlattenPass : public Pass {
 			for (auto cell : module->selected_cells()) {
 				RTLIL::Module *tpl = design->module(cell->type);
 				if (tpl != nullptr) {
-					if (!topo_modules.has_edges(tpl))
+                                        if (!topo_modules.has_node(tpl))
 						worklist.insert(tpl);
 					topo_modules.edge(tpl, module);
 				}