diff --git a/tests/functional_backend/simple.v b/tests/functional_backend/simple.v
deleted file mode 100644
index 3d55842945b..00000000000
--- a/tests/functional_backend/simple.v
+++ /dev/null
@@ -1,10 +0,0 @@
-// Simple pass-through Verilog module
-module PassThrough(
-    input wire in,    // Input wire
-    output wire out   // Output wire connected directly to input
-);
-
-// Connect the input directly to the output
-assign out = in;
-
-endmodule