diff --git a/passes/pmgen/peepopt_muxadd.pmg b/passes/pmgen/peepopt_muxadd.pmg
index f534dd42df5..f9c23882adf 100644
--- a/passes/pmgen/peepopt_muxadd.pmg
+++ b/passes/pmgen/peepopt_muxadd.pmg
@@ -65,12 +65,16 @@ code add_y add_a add_b add_a_ext add_a_id add_b_id  mux_y mux_a mux_b mux_a_id m
 	// Adder output could be assigned...
 	for (auto it = module->connections().begin(); it != module->connections().end(); ++it) {
 		RTLIL::SigSpec rhs = it->second;
-		const std::string& rhs_name = rhs.as_wire()->name.c_str();
-		if (rhs_name == adder_y_name) {
-			RTLIL::SigSpec lhs = it->first;
-			const std::string& lhs_name =  lhs.as_wire()->name.c_str();
-			module->rename(lhs_name, module->uniquify("$" + lhs_name));
-			break;
+		if (rhs.is_wire()) {
+			const std::string& rhs_name = rhs.as_wire()->name.c_str();
+			if (rhs_name == adder_y_name) {
+				RTLIL::SigSpec lhs = it->first;
+				if (lhs.is_wire()) {
+					const std::string& lhs_name =  lhs.as_wire()->name.c_str();
+					module->rename(lhs_name, module->uniquify("$" + lhs_name));
+					break;
+				}
+			}
 		}
 	}
 	// ...or the port name could be a wire name