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Include x bits in test of lhs dynamic part-select
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daglem committed Dec 12, 2023
1 parent 9c3b4d7 commit 1ee0fe4
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Showing 2 changed files with 5 additions and 5 deletions.
2 changes: 1 addition & 1 deletion tests/verilog/dynamic_range_lhs.sh
Original file line number Diff line number Diff line change
Expand Up @@ -15,7 +15,7 @@ run() {
-p "read_verilog dynamic_range_lhs.v" \
-p "proc" \
-p "equiv_make gold gate equiv" \
-p "equiv_simple" \
-p "equiv_simple -undef" \
-p "equiv_status -assert"
}

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8 changes: 4 additions & 4 deletions tests/verilog/dynamic_range_lhs.v
Original file line number Diff line number Diff line change
Expand Up @@ -5,8 +5,8 @@ module gate(
input wire [1:0] sel1, sel2
);
always @* begin
out_u = 0;
out_s = 0;
out_u = 'x;
out_s = 'x;
case (`SPAN)
1: begin
out_u[sel1*sel2] = data;
Expand Down Expand Up @@ -43,8 +43,8 @@ task set;
out_s[b] = data;
endtask
always @* begin
out_u = 0;
out_s = 0;
out_u = 'x;
out_s = 'x;
case (sel1*sel2)
2'b00: set(0, 0);
2'b01: set(1, 1);
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