diff --git a/tests/verilog/dynamic_range_lhs.sh b/tests/verilog/dynamic_range_lhs.sh
index 618204aed5f..e8f6f924320 100755
--- a/tests/verilog/dynamic_range_lhs.sh
+++ b/tests/verilog/dynamic_range_lhs.sh
@@ -15,7 +15,7 @@ run() {
         -p "read_verilog dynamic_range_lhs.v" \
         -p "proc" \
         -p "equiv_make gold gate equiv" \
-        -p "equiv_simple" \
+        -p "equiv_simple -undef" \
         -p "equiv_status -assert"
 }
 
diff --git a/tests/verilog/dynamic_range_lhs.v b/tests/verilog/dynamic_range_lhs.v
index 56fe3ef3b32..6eb95216571 100644
--- a/tests/verilog/dynamic_range_lhs.v
+++ b/tests/verilog/dynamic_range_lhs.v
@@ -5,8 +5,8 @@ module gate(
     input wire [1:0] sel1, sel2
 );
 always @* begin
-    out_u = 0;
-    out_s = 0;
+    out_u = 'x;
+    out_s = 'x;
     case (`SPAN)
     1: begin
         out_u[sel1*sel2] = data;
@@ -43,8 +43,8 @@ task set;
         out_s[b] = data;
 endtask
 always @* begin
-    out_u = 0;
-    out_s = 0;
+    out_u = 'x;
+    out_s = 'x;
     case (sel1*sel2)
         2'b00: set(0, 0);
         2'b01: set(1, 1);