diff --git a/docs/source/cell/gate_other.rst b/docs/source/cell/gate_other.rst
new file mode 100644
index 00000000000..bac26094e8e
--- /dev/null
+++ b/docs/source/cell/gate_other.rst
@@ -0,0 +1,8 @@
+Other gate-level cells
+----------------------
+
+.. autocellgroup:: gate_other
+   :caption: Other gate-level cells
+   :members:
+   :source:
+   :linenos:
diff --git a/docs/source/cell_gate.rst b/docs/source/cell_gate.rst
index e6fab4c1f5f..4ff38ec5e3b 100644
--- a/docs/source/cell_gate.rst
+++ b/docs/source/cell_gate.rst
@@ -23,14 +23,4 @@ file via ABC using the abc pass.
    /cell/gate_comb_combined
    /cell/gate_reg_ff
    /cell/gate_reg_latch
-
-.. TODO:: Find a home for `$_TBUF_`
-
-.. this should raise a warning, otherwise there are gate-level cells without a
-   'group' tag
-
-.. autocellgroup:: gate_other
-   :caption: Other gate-level cells
-   :members:
-   :source:
-   :linenos:
+   /cell/gate_other
diff --git a/docs/source/cell_word.rst b/docs/source/cell_word.rst
index ac3314d13a6..0d1f91cd6e0 100644
--- a/docs/source/cell_word.rst
+++ b/docs/source/cell_word.rst
@@ -30,11 +30,4 @@ Simulation models for the RTL cells can be found in the file
    /cell/word_debug
    /cell/word_wire
 
-.. this should raise a warning, otherwise there are word-level cells without a
-   'group' tag
-
-.. autocellgroup:: word_other
-   :caption: Other word-level cells
-   :members:
-   :source:
-   :linenos:
+.. todo:: Add check for unexpected ``word_other`` cells