From 2893938355d786a0188753272cef5d95c3e10ccb Mon Sep 17 00:00:00 2001 From: Richard Herveille Date: Tue, 19 Mar 2024 01:31:36 +0100 Subject: [PATCH] Removed SystemVerilog module end label --- techlibs/intel/max10/cells_sim.v | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/techlibs/intel/max10/cells_sim.v b/techlibs/intel/max10/cells_sim.v index fe8c92b0afe..b163aac401f 100644 --- a/techlibs/intel/max10/cells_sim.v +++ b/techlibs/intel/max10/cells_sim.v @@ -322,7 +322,7 @@ module fiftyfivenm_mac_mult ( input aclr; input clk; input ena; -endmodule : fiftyfivenm_mac_mult +endmodule //fiftyfivenm_mac_mult module fiftyfivenm_mac_out ( dataa, @@ -342,4 +342,4 @@ module fiftyfivenm_mac_out ( input aclr; input clk; input ena; -endmodule : fiftyfivenm_mac_out +endmodule //fiftyfivenm_mac_out