From 3076875fffb5fd29ca177bc9a4245f05d3636099 Mon Sep 17 00:00:00 2001 From: Ethan Mahintorabi Date: Tue, 30 Jan 2024 00:56:07 +0000 Subject: [PATCH] removing call to dump_attributes to remove possibility of generating invalid verilog Signed-off-by: Ethan Mahintorabi --- backends/verilog/verilog_backend.cc | 1 - 1 file changed, 1 deletion(-) diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc index 51ea14bf4c7..41e51f3289b 100644 --- a/backends/verilog/verilog_backend.cc +++ b/backends/verilog/verilog_backend.cc @@ -1058,7 +1058,6 @@ bool dump_cell_expr(std::ostream &f, std::string indent, RTLIL::Cell *cell) f << stringf("%s" "assign ", indent.c_str()); dump_sigspec(f, cell->getPort(ID::Y)); f << stringf(" = "); - dump_attributes(f, "", cell->attributes, " "); dump_cell_expr_port(f, cell, "A", false); f << stringf(";\n"); return true;