read_verilog: Add missing defaults for flags

Fix for YosysHQ/sby#103
YosysHQ · Apr 6, 2024 · 30f7d37 · 30f7d37
1 parent 22c5ab9
commit 30f7d37
Showing 1 changed file with 3 additions and 0 deletions.
diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
@@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
 		frontend_verilog_yydebug = false;
 		sv_mode = false;
 		formal_mode = false;
+		noassert_mode = false;
+		noassume_mode = false;
 		norestrict_mode = false;
 		assume_asserts_mode = false;
+		assert_assumes_mode = false;
 		lib_mode = false;
 		specify_mode = false;
 		default_nettype_wire = true;