From 30f7d3715d06c8be7ea883d2adcb3bbd53b69fbc Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Sat, 6 Apr 2024 14:24:34 +1300
Subject: [PATCH] read_verilog: Add missing defaults for flags

Fix for YosysHQ/sby#103
---
 frontends/verilog/verilog_frontend.cc | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/frontends/verilog/verilog_frontend.cc b/frontends/verilog/verilog_frontend.cc
index 5c59fe3afac..d363d71fb9a 100644
--- a/frontends/verilog/verilog_frontend.cc
+++ b/frontends/verilog/verilog_frontend.cc
@@ -270,8 +270,11 @@ struct VerilogFrontend : public Frontend {
 		frontend_verilog_yydebug = false;
 		sv_mode = false;
 		formal_mode = false;
+		noassert_mode = false;
+		noassume_mode = false;
 		norestrict_mode = false;
 		assume_asserts_mode = false;
+		assert_assumes_mode = false;
 		lib_mode = false;
 		specify_mode = false;
 		default_nettype_wire = true;