Merge pull request #4500 from YosysHQ/micko/vhdl_mixcase

VHDL is case insensitive, make sure netlist name is proper
YosysHQ · Jul 29, 2024 · 3e14e67 · 3e14e67
2 parents 92cac63 + 405897a
commit 3e14e67
Showing 1 changed file with 9 additions and 2 deletions.
diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
@@ -58,6 +58,7 @@ USING_YOSYS_NAMESPACE
 
 #ifdef VERIFIC_VHDL_SUPPORT
 #include "vhdl_file.h"
+#include "VhdlIdDef.h"
 #include "VhdlUnits.h"
 #include "NameSpace.h"
 #endif
@@ -2759,7 +2760,7 @@ void import_all(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *
 #endif
 }
 
-std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops)
+std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist*> *nl_todo, Map *parameters, bool show_message, std::string ppfile YS_MAYBE_UNUSED, std::vector<std::string> &tops, std::string *top = nullptr)
 {
 	std::set<std::string> top_mod_names;
 	Array *netlists = nullptr;
@@ -2817,6 +2818,12 @@ std::set<std::string> import_tops(const char* work, std::map<std::string,Netlist
 				if (show_message)
 					log("Adding VHDL unit '%s' to elaboration queue.\n", name);
 				vhdl_units.InsertLast(vhdl_unit);
+				if (strcmp(name, vhdl_unit->Id()->OrigName()) != 0) {
+					top_mod_names.erase(name);
+					top_mod_names.insert(vhdl_unit->Id()->OrigName());
+					if (top && *top == name)
+						*top = vhdl_unit->Id()->OrigName();
+				}
 				continue;
 			}
 #endif
@@ -2957,7 +2964,7 @@ std::string verific_import(Design *design, const std::map<std::string,std::strin
 		veri_file::RemoveAllLOptions();
 		veri_file::AddLOption("work");
 #endif
-		top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops) ;
+		top_mod_names = import_tops("work", &nl_todo, &verific_params, false, "", tops, &top) ;
 	}
 
 	if (!verific_error_msg.empty())