diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index fe67f00c692..e1cf6fb573a 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -2224,7 +2224,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 				else
 					input_error("FATAL.\n");
 			} else {
-				input_error("Unknown elabortoon system task '%s'.\n", str.c_str());
+				input_error("Unknown elaboration system task '%s'.\n", str.c_str());
 			}
 		} break;
 
diff --git a/kernel/driver.cc b/kernel/driver.cc
index 58da1bc32e3..79dff7ddabe 100644
--- a/kernel/driver.cc
+++ b/kernel/driver.cc
@@ -356,7 +356,7 @@ int main(int argc, char **argv)
 		printf("    -V\n");
 		printf("        print version information and exit\n");
 		printf("\n");
-		printf("The option -S is an shortcut for calling the \"synth\" command, a default\n");
+		printf("The option -S is a shortcut for calling the \"synth\" command, a default\n");
 		printf("script for transforming the Verilog input to a gate-level netlist. For example:\n");
 		printf("\n");
 		printf("    yosys -o output.blif -S input.v\n");
diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
index 24134b1fb1f..5720c9b1e7a 100644
--- a/passes/pmgen/ice40_dsp.cc
+++ b/passes/pmgen/ice40_dsp.cc
@@ -289,7 +289,7 @@ struct Ice40DspPass : public Pass {
 		log("\n");
 		log("Pack input registers (A, B, {C,D}; with optional hold), pipeline registers\n");
 		log("({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with\n");
-		log("optional hold), and post-adder into into the SB_MAC16 resource.\n");
+		log("optional hold), and post-adder into the SB_MAC16 resource.\n");
 		log("\n");
 		log("Multiply-accumulate operations using the post-adder with feedback on the {C,D}\n");
 		log("input will be folded into the DSP. In this scenario only, resetting the\n");