Create vcd file from sim if -sim-cmp fails

tests/functional/single_bit/run-test.sh

@@ -25,9 +25,9 @@ run_test() {
 
 	    # Run yosys to process each Verilog file
 	    if ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -r ${base_name}_functional_cxx.vcd -scope my_module -vcd ${base_name}_yosys_sim.vcd -timescale 1us -sim-cmp"; then
-		# ${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us"
 		echo "Yosys sim $verilog_file successfully."
 	    else
+		${BASE_PATH}yosys -p "read_verilog $verilog_file; sim -vcd ${base_name}_yosys_sim.vcd -r ${base_name}_functional_cxx.vcd -scope my_module -timescale 1us"
 		echo "Yosys simulation of $verilog_file failed. There is a discrepancy with functional cxx"
 		failing_files["$verilog_file"]="Yosys sim failure"
 	    fi