From 4715f9cc2dfd6b402aa3f0b8703efe2b6a445c51 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 29 May 2024 19:28:53 +0200
Subject: [PATCH] Fix wire detection

---
 techlibs/nanoxplore/nx_carry.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/techlibs/nanoxplore/nx_carry.cc b/techlibs/nanoxplore/nx_carry.cc
index aec2d1a3c97..93541c0c096 100644
--- a/techlibs/nanoxplore/nx_carry.cc
+++ b/techlibs/nanoxplore/nx_carry.cc
@@ -80,7 +80,7 @@ static void nx_carry_chain(Module *module)
 		IdString names_A[] = { ID(A1), ID(A2), ID(A3), ID(A4) };
 		IdString names_B[] = { ID(B1), ID(B2), ID(B3), ID(B4) };
 		IdString names_S[] = { ID(S1), ID(S2), ID(S3), ID(S4) };
-		if (c.second.at(0)->getPort(ID(CI)).is_wire()) {
+		if (c.second.at(0)->getPort(ID(CI)).as_bit().is_wire()) {
 			cell = module->addCell(NEW_ID, ID(NX_CY));
 			cell->setPort(ID(CI), State::S0);