diff --git a/kernel/celledges.cc b/kernel/celledges.cc
index dab38443184..c70211ad303 100644
--- a/kernel/celledges.cc
+++ b/kernel/celledges.cc
@@ -225,6 +225,34 @@ void mem_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
 		log_abort();
 }
 
+void ff_op(AbstractCellEdgesDatabase *db, RTLIL::Cell *cell)
+{
+	int width = cell->getPort(ID::Q).size();
+
+	if (cell->type.in(ID($dlatch), ID($adlatch), ID($dlatchsr))) {
+		for (int k = 0; k < width; k++) {
+			db->add_edge(cell, ID::D, k, ID::Q, k, -1);
+			db->add_edge(cell, ID::EN, 0, ID::Q, k, -1);
+		}
+	}
+
+	if (cell->hasPort(ID::CLR))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::CLR, 0, ID::Q, k, -1);
+	if (cell->hasPort(ID::SET))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::SET, 0, ID::Q, k, -1);
+	if (cell->hasPort(ID::ALOAD))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::ALOAD, 0, ID::Q, k, -1);
+	if (cell->hasPort(ID::AD))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::AD, k, ID::Q, k, -1);
+	if (cell->hasPort(ID::ARST))
+		for (int k = 0; k < width; k++)
+			db->add_edge(cell, ID::ARST, 0, ID::Q, k, -1);
+}
+
 PRIVATE_NAMESPACE_END
 
 bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL::Cell *cell)
@@ -285,6 +313,11 @@ bool YOSYS_NAMESPACE_PREFIX AbstractCellEdgesDatabase::add_edges_from_cell(RTLIL
 		return true;
 	}
 
+	if (RTLIL::builtin_ff_cell_types().count(cell->type)) {
+		ff_op(this, cell);
+		return true;
+	}
+
 	// FIXME: $mul $div $mod $divfloor $modfloor $slice $concat
 	// FIXME: $lut $sop $alu $lcu $macc $fa
 
diff --git a/passes/cmds/check.cc b/passes/cmds/check.cc
index bb169b4f965..23e4e7c927c 100644
--- a/passes/cmds/check.cc
+++ b/passes/cmds/check.cc
@@ -224,7 +224,8 @@ struct CheckPass : public Pass {
 					}
 				}
 
-				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)))
+				if (yosys_celltypes.cell_evaluable(cell->type) || cell->type.in(ID($mem_v2), ID($memrd), ID($memrd_v2)) \
+						|| RTLIL::builtin_ff_cell_types().count(cell->type))
 					edges_db.add_edges_from_cell(cell);
 			}