verilog_parser: silence yynerrs warning

YosysHQ · Oct 15, 2024 · 81bbde6 · 81bbde6
1 parent adb6cdb
commit 81bbde6
Showing 1 changed file with 1 addition and 0 deletions.
diff --git a/frontends/verilog/verilog_parser.y b/frontends/verilog/verilog_parser.y
@@ -464,6 +464,7 @@ static const AstNode *addAsgnBinopStmt(dict<IdString, AstNode*> *attr, AstNode *
 %%
 
 input: {
+	(void)frontend_verilog_yynerrs;
 	ast_stack.clear();
 	ast_stack.push_back(current_ast);
 } design {