From 84862e39073874d0b8ac0c77f6c1767cff3a888b Mon Sep 17 00:00:00 2001
From: Krystine Sherwin <93062060+KrystalDelusion@users.noreply.github.com>
Date: Tue, 14 May 2024 12:10:38 +1200
Subject: [PATCH] Docs: Add note on verific

Having a verific license does not provide access to the verific frontend.
---
 docs/source/using_yosys/more_scripting/load_design.rst | 8 ++++++++
 docs/source/using_yosys/synthesis/memory.rst           | 3 +++
 2 files changed, 11 insertions(+)

diff --git a/docs/source/using_yosys/more_scripting/load_design.rst b/docs/source/using_yosys/more_scripting/load_design.rst
index d64c50959bd..07c2bd8e58e 100644
--- a/docs/source/using_yosys/more_scripting/load_design.rst
+++ b/docs/source/using_yosys/more_scripting/load_design.rst
@@ -27,6 +27,14 @@ keyword: Frontends
 .. todo:: more info on other ``read_*`` commands, also is this the first time we
    mention verific?
 
+.. note::
+
+   The Verific frontend for Yosys, which provides the :cmd:ref:`verific`
+   command, requires the commercial `Tabby CAD Suite`_.  This is not the same as
+   simply having a Verific license when using Yosys.
+
+.. _Tabby CAD Suite: https://www.yosyshq.com/tabby-cad-datasheet
+
 Others:
 
 - :doc:`/cmd/read`
diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst
index 0f5e1bd3010..8306c82b9fb 100644
--- a/docs/source/using_yosys/synthesis/memory.rst
+++ b/docs/source/using_yosys/synthesis/memory.rst
@@ -697,6 +697,9 @@ TDP with multiple read ports
 Patterns only supported with Verific
 ------------------------------------
 
+The following patterns are only supported when Yosys is built with the Verific
+front-end.
+
 Synchronous SDP with write-first behavior via blocking assignments
 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~