test_cell: bloat $sop depth too

YosysHQ · May 9, 2024 · 8ea285e · 8ea285e
1 parent 9e67d5c
commit 8ea285e
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/passes/tests/test_cell.cc b/passes/tests/test_cell.cc
@@ -238,7 +238,7 @@ static RTLIL::Cell* create_gold_module(RTLIL::Design *design, RTLIL::IdString ce
 	if (cell_type == ID($sop))
 	{
 		int width = 1 + xorshift32(8 * bloat_factor);
-		int depth = 1 + xorshift32(8);
+		int depth = 1 + xorshift32(8 * bloat_factor);
 
 		wire = module->addWire(ID::A);
 		wire->width = width;