diff --git a/.github/ISSUE_TEMPLATE/bug_report.yml b/.github/ISSUE_TEMPLATE/bug_report.yml index 66c0b19715a..e4c776ed914 100644 --- a/.github/ISSUE_TEMPLATE/bug_report.yml +++ b/.github/ISSUE_TEMPLATE/bug_report.yml @@ -43,7 +43,7 @@ body: attributes: value: > When providing steps to reproduce the issue, please ensure that the issue - is reproducible in the current git master of Yosys. Also ensure to + is reproducible in the current git main of Yosys. Also ensure to provide all necessary source files needed. diff --git a/.github/workflows/test-docs.yml b/.github/workflows/test-docs.yml index e8064e485ae..00e5309bfbe 100644 --- a/.github/workflows/test-docs.yml +++ b/.github/workflows/test-docs.yml @@ -3,7 +3,7 @@ name: Build and test doc code samples on: pull_request: branches: - - master + - main jobs: test-docs: diff --git a/backends/jny/jny.cc b/backends/jny/jny.cc index 9989feed599..1c163dba52e 100644 --- a/backends/jny/jny.cc +++ b/backends/jny/jny.cc @@ -124,7 +124,7 @@ struct JnyWriter design->sort(); f << "{\n"; - f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json\",\n"; + f << " \"$schema\": \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\",\n"; f << stringf(" \"generator\": \"%s\",\n", escape_string(yosys_version_str).c_str()); f << " \"version\": \"0.0.1\",\n"; f << " \"invocation\": \"" << escape_string(invk) << "\",\n"; @@ -426,7 +426,7 @@ struct JnyBackend : public Backend { log(" Don't include property information in the netlist output.\n"); log("\n"); log("The JSON schema for JNY output files is located in the \"jny.schema.json\" file\n"); - log("which is located at \"https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json\"\n"); + log("which is located at \"https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json\"\n"); log("\n"); } diff --git a/docs/source/getting_started/example_synth.rst b/docs/source/getting_started/example_synth.rst index 799b4ec48b4..916bef9fabd 100644 --- a/docs/source/getting_started/example_synth.rst +++ b/docs/source/getting_started/example_synth.rst @@ -633,9 +633,9 @@ with the mapping to ``SB_RAM40_4K`` done by :cmd:ref:`techmap` using into flip flops (the ``logic fallback``) with :cmd:ref:`memory_map`. .. |techlibs/ice40/brams.txt| replace:: :file:`techlibs/ice40/brams.txt` -.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/master/techlibs/ice40/brams.txt +.. _techlibs/ice40/brams.txt: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams.txt .. |techlibs/ice40/brams_map.v| replace:: :file:`techlibs/ice40/brams_map.v` -.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/master/techlibs/ice40/brams_map.v +.. _techlibs/ice40/brams_map.v: https://github.com/YosysHQ/yosys/tree/main/techlibs/ice40/brams_map.v .. literalinclude:: /cmd/synth_ice40.rst :language: yoscrypt diff --git a/docs/source/test_suites.rst b/docs/source/test_suites.rst index 2edb0e67d1a..7a6b7497774 100644 --- a/docs/source/test_suites.rst +++ b/docs/source/test_suites.rst @@ -16,8 +16,8 @@ Automatic testing .. _Yosys Git repo: https://github.com/YosysHQ/yosys -.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=master -.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=master +.. |test-linux| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-linux.yml/badge.svg?branch=main +.. |test-macos| image:: https://github.com/YosysHQ/yosys/actions/workflows/test-macos.yml/badge.svg?branch=main For up to date information, including OS versions, refer to `the git actions page`_. diff --git a/docs/source/using_yosys/more_scripting/interactive_investigation.rst b/docs/source/using_yosys/more_scripting/interactive_investigation.rst index ed798d6b694..a7ec4411351 100644 --- a/docs/source/using_yosys/more_scripting/interactive_investigation.rst +++ b/docs/source/using_yosys/more_scripting/interactive_investigation.rst @@ -18,7 +18,7 @@ in the circuit diagrams generated by it. The code used is included in the Yosys code base under |code_examples/show|_. .. |code_examples/show| replace:: :file:`docs/source/code_examples/show` -.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/show +.. _code_examples/show: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/show A simple circuit ^^^^^^^^^^^^^^^^ @@ -168,7 +168,7 @@ mapped to a cell library: :class: width-helper :name: first_pitfall - A half-adder built from simple CMOS gates, demonstrating common pitfalls when + A half-adder built from simple CMOS gates, demonstrating common pitfalls when using :cmd:ref:`show` .. literalinclude:: /code_examples/show/cmos.ys @@ -332,12 +332,12 @@ tools). - :doc:`/cmd/dump`. - :doc:`/cmd/add` and :doc:`/cmd/delete` can be used to modify and reorganize a design dynamically. - + The code used is included in the Yosys code base under |code_examples/scrambler|_. .. |code_examples/scrambler| replace:: :file:`docs/source/code_examples/scrambler` -.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/scrambler +.. _code_examples/scrambler: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/scrambler Changing design hierarchy ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/source/using_yosys/more_scripting/model_checking.rst b/docs/source/using_yosys/more_scripting/model_checking.rst index 0b97d384e63..92a9d85ce67 100644 --- a/docs/source/using_yosys/more_scripting/model_checking.rst +++ b/docs/source/using_yosys/more_scripting/model_checking.rst @@ -29,7 +29,7 @@ Let's take a look at an example included in the Yosys code base under |code_examples/synth_flow|_: .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow` -.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow +.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow .. literalinclude:: /code_examples/synth_flow/techmap_01_map.v :language: verilog @@ -81,7 +81,7 @@ The code used in this section is included in the Yosys code base under |code_examples/axis|_. .. |code_examples/axis| replace:: :file:`docs/source/code_examples/axis` -.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/axis +.. _code_examples/axis: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/axis The following AXI4 Stream Master has a bug. But the bug is not exposed if the slave keeps ``tready`` asserted all the time. (Something a test bench might do.) diff --git a/docs/source/using_yosys/more_scripting/selections.rst b/docs/source/using_yosys/more_scripting/selections.rst index d4def881cc9..6aa3465cc99 100644 --- a/docs/source/using_yosys/more_scripting/selections.rst +++ b/docs/source/using_yosys/more_scripting/selections.rst @@ -405,7 +405,7 @@ those cases selection variables must be used to capture more complex selections. Example code from |code_examples/selections|_: .. |code_examples/selections| replace:: :file:`docs/source/code_examples/selections` -.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/selections +.. _code_examples/selections: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/selections .. literalinclude:: /code_examples/selections/select.v :language: verilog diff --git a/docs/source/using_yosys/synthesis/cell_libs.rst b/docs/source/using_yosys/synthesis/cell_libs.rst index a723845379a..0546d27546d 100644 --- a/docs/source/using_yosys/synthesis/cell_libs.rst +++ b/docs/source/using_yosys/synthesis/cell_libs.rst @@ -18,10 +18,10 @@ detail in the :doc:`/getting_started/example_synth` document. The :file:`counter.ys` script includes the commands used to generate the images in this document. Code snippets in this document skip these commands; including line numbers to allow the reader to follow along with the source. - + To learn more about these commands, check out :ref:`interactive_show`. -.. _example project: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/intro +.. _example project: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/intro A simple counter ~~~~~~~~~~~~~~~~ diff --git a/docs/source/using_yosys/synthesis/extract.rst b/docs/source/using_yosys/synthesis/extract.rst index 678efba868e..bbe1870dfb3 100644 --- a/docs/source/using_yosys/synthesis/extract.rst +++ b/docs/source/using_yosys/synthesis/extract.rst @@ -15,7 +15,7 @@ The extract pass Example code can be found in |code_examples/macc|_. .. |code_examples/macc| replace:: :file:`docs/source/code_examples/macc` -.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/macc +.. _code_examples/macc: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/macc .. literalinclude:: /code_examples/macc/macc_simple_test.ys diff --git a/docs/source/using_yosys/synthesis/memory.rst b/docs/source/using_yosys/synthesis/memory.rst index 7df75fb8809..3dbafeaab7e 100644 --- a/docs/source/using_yosys/synthesis/memory.rst +++ b/docs/source/using_yosys/synthesis/memory.rst @@ -36,7 +36,7 @@ Example |code_examples/synth_flow|_. .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow` -.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow +.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow .. figure:: /_images/code_examples/synth_flow/memory_01.* :class: width-helper @@ -92,7 +92,7 @@ leftover memory cells unable to be converted are then picked up by For more on the lib format for :cmd:ref:`memory_libmap`, see `passes/memory/memlib.md -`_ +`_ Supported memory patterns ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/docs/source/using_yosys/synthesis/proc.rst b/docs/source/using_yosys/synthesis/proc.rst index 785be7adc7c..b4983438021 100644 --- a/docs/source/using_yosys/synthesis/proc.rst +++ b/docs/source/using_yosys/synthesis/proc.rst @@ -31,7 +31,7 @@ Example |code_examples/synth_flow|_. .. |code_examples/synth_flow| replace:: :file:`docs/source/code_examples/synth_flow` -.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/synth_flow +.. _code_examples/synth_flow: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/synth_flow .. literalinclude:: /code_examples/synth_flow/proc_01.v :language: verilog diff --git a/docs/source/yosys_internals/extending_yosys/extensions.rst b/docs/source/yosys_internals/extending_yosys/extensions.rst index 2c159e3f089..68e1740be4a 100644 --- a/docs/source/yosys_internals/extending_yosys/extensions.rst +++ b/docs/source/yosys_internals/extending_yosys/extensions.rst @@ -24,7 +24,7 @@ Code examples from this section are included in the |code_examples/extensions|_ directory of the Yosys source code. .. |code_examples/extensions| replace:: :file:`docs/source/code_examples/extensions` -.. _code_examples/extensions: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/extensions +.. _code_examples/extensions: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/extensions Program components and data formats @@ -254,7 +254,7 @@ The following is the complete code of the "stubnets" example module. It is included in the Yosys source distribution under |code_examples/stubnets|_. .. |code_examples/stubnets| replace:: :file:`docs/source/code_examples/stubnets` -.. _code_examples/stubnets: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/stubnets +.. _code_examples/stubnets: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/stubnets .. literalinclude:: /code_examples/stubnets/stubnets.cc :language: c++ diff --git a/docs/source/yosys_internals/techmap.rst b/docs/source/yosys_internals/techmap.rst index ef2bbd87a28..ab161ed92d3 100644 --- a/docs/source/yosys_internals/techmap.rst +++ b/docs/source/yosys_internals/techmap.rst @@ -16,7 +16,7 @@ Code examples used in this document are included in the Yosys code base under |code_examples/techmap|_. .. |code_examples/techmap| replace:: :file:`docs/source/code_examples/techmap` -.. _code_examples/techmap: https://github.com/YosysHQ/yosys/tree/master/docs/source/code_examples/techmap +.. _code_examples/techmap: https://github.com/YosysHQ/yosys/tree/main/docs/source/code_examples/techmap Mapping OR3X1 diff --git a/guidelines/Windows b/guidelines/Windows index 2af0620fae9..9e242dadd60 100644 --- a/guidelines/Windows +++ b/guidelines/Windows @@ -44,12 +44,12 @@ Visual Studio builds are not directly supported by build scripts, but they are s 1. Easy way - - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amaster + - Go to https://github.com/YosysHQ/yosys/actions/workflows/vs.yml?query=branch%3Amain - Click on the most recent completed run - In Artifacts region find vcxsrc and click on it to download - Unpack downloaded ZIP file - Open YosysVS.sln with Visual Studio - + 2. Using WSL or MSYS2 - Make sure to have make, python3 and git available diff --git a/misc/create_vcxsrc.sh b/misc/create_vcxsrc.sh index 8b39d59e30e..eee215015b5 100644 --- a/misc/create_vcxsrc.sh +++ b/misc/create_vcxsrc.sh @@ -46,7 +46,7 @@ Open "Git Bash" in this directory and run: mv yosys yosys.bak git clone https://github.com/YosysHQ/yosys.git yosys cd yosys - git checkout -B master $(git rev-parse HEAD | cut -c1-10) + git checkout -B main $(git rev-parse HEAD | cut -c1-10) unzip ../genfiles.zip EOT diff --git a/misc/jny.schema.json b/misc/jny.schema.json index 0fff8ee57d8..278b1a55f63 100644 --- a/misc/jny.schema.json +++ b/misc/jny.schema.json @@ -1,6 +1,6 @@ { "$schema": "https://json-schema.org/draft/2020-12/schema", - "$id": "https://raw.githubusercontent.com/YosysHQ/yosys/master/misc/jny.schema.json", + "$id": "https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json", "title": "Yosys JSON Netlist metadata", "description": "Yosys JSON Netlist", "type": "object",