From 91e41d8c803562d43e2debe30677a86d55035357 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Mon, 8 Apr 2024 12:44:37 +0200
Subject: [PATCH] Move parameters to module declaration

---
 tests/memlib/memlib_9b1B.v  | 20 +++++++++++---------
 tests/memlib/memlib_wren.v  | 16 ++++++++--------
 tests/memories/issue00335.v |  6 ++++--
 3 files changed, 23 insertions(+), 19 deletions(-)

diff --git a/tests/memlib/memlib_9b1B.v b/tests/memlib/memlib_9b1B.v
index 55545ebd4db..9a8246c9f19 100644
--- a/tests/memlib/memlib_9b1B.v
+++ b/tests/memlib/memlib_9b1B.v
@@ -1,4 +1,14 @@
-module RAM_9b1B (
+module RAM_9b1B 
+#(
+	parameter INIT = 0,
+	parameter OPTION_INIT = "UNDEFINED",
+	parameter PORT_R_WIDTH = 9,
+	parameter PORT_W_WIDTH = 9,
+	parameter PORT_R_CLK_POL = 0,
+	parameter PORT_W_CLK_POL = 0,
+	parameter PORT_W_WR_EN_WIDTH = 1
+)
+(
 	input PORT_R_CLK,
 	input [6:0] PORT_R_ADDR,
 	output reg [PORT_R_WIDTH-1:0] PORT_R_RD_DATA,
@@ -8,14 +18,6 @@ module RAM_9b1B (
 	input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA
 );
 
-parameter INIT = 0;
-parameter OPTION_INIT = "UNDEFINED";
-parameter PORT_R_WIDTH = 9;
-parameter PORT_W_WIDTH = 9;
-parameter PORT_R_CLK_POL = 0;
-parameter PORT_W_CLK_POL = 0;
-parameter PORT_W_WR_EN_WIDTH = 1;
-
 reg [8:0] mem [0:15];
 
 integer i;
diff --git a/tests/memlib/memlib_wren.v b/tests/memlib/memlib_wren.v
index b9433d42e66..c687184bdca 100644
--- a/tests/memlib/memlib_wren.v
+++ b/tests/memlib/memlib_wren.v
@@ -1,4 +1,11 @@
-module RAM_WREN (
+module RAM_WREN #(
+	parameter ABITS=4,
+	parameter WIDTH=8,
+	parameter PORT_A_WR_EN_WIDTH=1,
+	parameter PORT_A_WR_BE_WIDTH=0,
+	parameter OPTION_BYTESIZE=WIDTH,
+	parameter WB=OPTION_BYTESIZE
+)(
 	input PORT_A_CLK,
 	input [ABITS-1:0] PORT_A_ADDR,
 	input [WIDTH-1:0] PORT_A_WR_DATA,
@@ -7,13 +14,6 @@ module RAM_WREN (
 	input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE
 );
 
-parameter ABITS=4;
-parameter WIDTH=8;
-parameter PORT_A_WR_EN_WIDTH=1;
-parameter PORT_A_WR_BE_WIDTH=0;
-parameter OPTION_BYTESIZE=WIDTH;
-parameter WB=OPTION_BYTESIZE;
-
 reg [WIDTH-1:0] mem [0:2**ABITS-1];
 
 integer i;
diff --git a/tests/memories/issue00335.v b/tests/memories/issue00335.v
index f3b6e5dfe28..305339dd959 100644
--- a/tests/memories/issue00335.v
+++ b/tests/memories/issue00335.v
@@ -2,13 +2,15 @@
 // expect-rd-ports 1
 // expect-rd-clk \clk
 
-module ram2 (input clk,
+module ram2 #(
+             parameter  SIZE = 5 // Address size
+          ) (input clk,
              input             sel,
              input             we, 
              input [SIZE-1:0]  adr, 
              input [63:0]      dat_i, 
              output reg [63:0] dat_o);
-   parameter  SIZE = 5; // Address size
+   
 
    reg [63:0] mem [0:(1 << SIZE)-1];
    integer    i;