diff --git a/docs/source/yosys_internals/formats/cell_library.rst b/docs/source/yosys_internals/formats/cell_library.rst
index a4e5adfb70a..1e0012f461d 100644
--- a/docs/source/yosys_internals/formats/cell_library.rst
+++ b/docs/source/yosys_internals/formats/cell_library.rst
@@ -632,8 +632,9 @@ If the second signal in such a pair is zero length, no multiplication is necessa
 
 In this pseudocode, ``u(foo)`` means an unsigned int that's foo bits long.
 The CONFIG parameter carries the following information:
+
 .. code-block::
-	:force:
+
 	struct CONFIG {
 		u4 num_bits;
 		struct port_field {
@@ -645,8 +646,9 @@ The CONFIG parameter carries the following information:
 	};
 
 The A cell port carries the following information:
+
 .. code-block::
-	:force:
+
 	struct A {
 		u(CONFIG.port_field[0].factor1_len) port0factor1;
 		u(CONFIG.port_field[0].factor2_len) port0factor2;
@@ -660,10 +662,11 @@ A factor2 having a zero length implies factor2 is replaced with a constant 1.
 
 Additionally, B is an array of 1-bit-wide unsigned integers to also be summed up.
 Finally, we have:
+
 .. code-block::
-	:force:
+
 	Y = port0factor1 * port0factor2 + port1factor1 * port1factor2 + ...
-		* B[0] + B[1] + ...
+	     + B[0] + B[1] + ...
 
 Specify rules
 ~~~~~~~~~~~~~
diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index 1383a2a1374..7dc03da6d2d 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -907,8 +907,13 @@ endmodule
 //-     $macc (A, B, Y)
 //-
 //- Multiply and accumulate.
-//- A building block for summing any number of negated and unnegated signals and arithmetic products of pairs of signals. Cell port A concatenates pairs of signals to be multiplied together. When the second signal in a pair is zero length, a constant 1 is used instead as the second factor. Cell port B concatenates 1-bit-wide signals to also be summed, such as "carry in" in adders.
-//- Typically created by the `alumacc` pass, which transforms $add and $mul into $macc cells.
+//- A building block for summing any number of negated and unnegated signals
+//- and arithmetic products of pairs of signals. Cell port A concatenates pairs
+//- of signals to be multiplied together. When the second signal in a pair is zero
+//- length, a constant 1 is used instead as the second factor. Cell port B
+//- concatenates 1-bit-wide signals to also be summed, such as "carry in" in adders.
+//- Typically created by the `alumacc` pass, which transforms $add and $mul
+//- into $macc cells.
 module \$macc (A, B, Y);
 
 parameter A_WIDTH = 0;