diff --git a/frontends/ast/simplify.cc b/frontends/ast/simplify.cc
index 380a1bff493..91497ef1da5 100644
--- a/frontends/ast/simplify.cc
+++ b/frontends/ast/simplify.cc
@@ -1260,6 +1260,8 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 	}
 
 	if (type == AST_CELL) {
+		// when a module lookup is suggested, any port connection that is not a
+		// plain identifier will be indirected through a new wire
 		bool lookup_suggested = false;
 
 		for (AstNode *child : children) {
@@ -1282,7 +1284,7 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 							continue;
 					}
 					if (elem->type == AST_MEMORY)
-						// need to determine is the is a read or wire
+						// need to determine is the is a read or write
 						lookup_suggested = true;
 					else if (elem->type == AST_WIRE && elem->is_signed && !value->children.empty())
 						// this may be a fully sliced signed wire which needs
@@ -1295,9 +1297,12 @@ bool AstNode::simplify(bool const_fold, int stage, int width_hint, bool sign_hin
 				else if (value->type == AST_TO_UNSIGNED)
 					// inner expression may be signed by default
 					lookup_suggested = true;
-				else if (value->type == AST_CONCAT && value->children.size() == 1)
-					// concat of a single expression is equivalent to $unsigned
+				else if (value->type == AST_CONCAT) {
+					// concat of a single expression is equivalent to $unsigned;
+					// concats could also contain one or references to memories,
+					// which may ambiguously be reads or writes
 					lookup_suggested = true;
+				}
 			}
 		}
 
diff --git a/tests/simple/memwr_port_connection.sv b/tests/simple/memwr_port_connection.sv
index bc60d7e52a9..3ee26c01674 100644
--- a/tests/simple/memwr_port_connection.sv
+++ b/tests/simple/memwr_port_connection.sv
@@ -5,11 +5,17 @@ module producer(
 endmodule
 
 module top(
-    output logic [3:0] out0, out1
+    output logic [3:0] out0, out1, out2, out3
 );
     logic [3:0] v[1:0];
+    logic [1:0] u[1:0];
+    logic [1:0] t[1:0];
     producer p0(v[0]);
     producer p1({v[1]});
+    producer p2({u[1], u[0]});
+    producer p3({{t[1]}, {t[0]}});
     assign out0 = v[0];
     assign out1 = v[1];
+    assign out2 = {u[1], u[0]};
+    assign out3 = {t[1], t[0]};
 endmodule