Merge pull request #4625 from povik/cellmatch-lut

cellmatch: Size the `lut` attribute
YosysHQ · Oct 11, 2024 · a00137c · a00137c
2 parents 0200a76 + ec42b42
commit a00137c
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/passes/techmap/cellmatch.cc b/passes/techmap/cellmatch.cc
@@ -223,7 +223,7 @@ struct CellmatchPass : Pass {
 				for (auto bit : outputs) {
 					log_assert(bit.is_wire());
 					bit.wire->attributes[ID(p_class)] = p_class(inputs.size(), luts[no]);
-					bit.wire->attributes[ID(lut)] = luts[no++];
+					bit.wire->attributes[ID(lut)] = Const(luts[no++], 1 << inputs.size());
 				}
 			}