diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index 8b32982038b..3614bc900ed 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -1,7 +1,7 @@
 module $__NX_RAM_ (...);
 
 parameter INIT = 0;
-parameter OPTION_STD_MODE = "";
+parameter OPTION_STD_MODE = "NOECC_24kx2";
 
 parameter WIDTH = 24;
 parameter PORT_A_CLK_POL = 1;
@@ -24,6 +24,35 @@ input [WIDTH-1:0] PORT_B_WR_DATA;
 wire [24-1:0] B_DATA;
 output [WIDTH-1:0] PORT_B_RD_DATA;
 
+function [15:0] raw_config1_func;
+begin
+    if (OPTION_STD_MODE == "NOECC_48kx1") begin
+        raw_config1_func = 16'b0000000000000000;
+    end
+    else if (OPTION_STD_MODE == "NOECC_24kx2") begin
+        raw_config1_func = 16'b0000001001001001;
+    end
+    else if (OPTION_STD_MODE == "NOECC_16kx3") begin
+        raw_config1_func = 16'b0000111111111111;
+    end
+    else if (OPTION_STD_MODE == "NOECC_12kx4") begin
+        raw_config1_func = 16'b0000010010010010;
+    end
+    else if (OPTION_STD_MODE == "NOECC_8kx6") begin
+        raw_config1_func = 16'b0000110110110110;
+    end
+    else if (OPTION_STD_MODE == "NOECC_6kx8") begin
+        raw_config1_func = 16'b0000011011011011;
+    end
+    else if (OPTION_STD_MODE == "NOECC_4kx12") begin
+        raw_config1_func = 16'b0000100100100100;
+    end
+    else if (OPTION_STD_MODE == "NOECC_2kx24") begin
+        raw_config1_func = 16'b0000101101101101;
+    end
+end
+endfunction
+
 generate
     if (OPTION_STD_MODE == "NOECC_48kx1") begin
         assign A_DATA = {24{PORT_A_WR_DATA[WIDTH-1:0]}};
@@ -57,12 +86,19 @@ generate
         assign A_DATA = PORT_A_WR_DATA;
         assign B_DATA = PORT_B_WR_DATA;
     end
+    else
+        $error("Unknown NX_RAM mode");
 endgenerate
 
 NX_RAM_WRAP #(
     .std_mode(OPTION_STD_MODE),
     .mcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
     .mckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .pcka_edge(PORT_A_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .pckb_edge(PORT_B_CLK_POL == 1 ? 1'b0 : 1'b1),
+    .raw_config0(4'b0000),
+    .raw_config1(raw_config1_func()),
+    .mem_ctxt("")
 ) _TECHMAP_REPLACE_ (
     .ACK(PORT_A_CLK),
     //.ACKS(PORT_A_CLK),