From c36cf9c5ac26ff6bdad8c505e0bcac677af25938 Mon Sep 17 00:00:00 2001
From: Wanda <wanda@phinode.net>
Date: Sun, 8 Oct 2023 01:11:30 +0200
Subject: [PATCH] write_verilog: avoid emitting empty cases.

The Verilog grammar does not allow an empty case.  Most synthesis tools
are quite permissive about this, but Quartus is not.  This causes
problems for amaranth with Quartus (see amaranth-lang/amaranth#931).
---
 backends/verilog/verilog_backend.cc | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 7099c18c349..735672a43b4 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2008,6 +2008,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		dump_case_body(f, indent + "    ", *it);
 	}
 
+	if (sw->cases.empty()) {
+		// Verilog does not allow empty cases.
+		f << stringf("%s  default: ;\n", indent.c_str());
+	}
+
 	f << stringf("%s" "endcase\n", indent.c_str());
 }