From b71219b0b9de61fd75d9575bc4106d7deffbb6f6 Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Mon, 2 Sep 2024 18:08:51 +0200
Subject: [PATCH] wip

---
 passes/techmap/Makefile.inc  |  1 +
 passes/techmap/clock_gate.cc | 62 ++++++++++++++++++++++++++++++++++++
 2 files changed, 63 insertions(+)
 create mode 100644 passes/techmap/clock_gate.cc

diff --git a/passes/techmap/Makefile.inc b/passes/techmap/Makefile.inc
index 74813bca93f..e0c7858f995 100644
--- a/passes/techmap/Makefile.inc
+++ b/passes/techmap/Makefile.inc
@@ -49,6 +49,7 @@ OBJS += passes/techmap/dffunmap.o
 OBJS += passes/techmap/flowmap.o
 OBJS += passes/techmap/extractinv.o
 OBJS += passes/techmap/cellmatch.o
+OBJS += passes/techmap/clock_gate.o
 endif
 
 ifeq ($(DISABLE_SPAWN),0)
diff --git a/passes/techmap/clock_gate.cc b/passes/techmap/clock_gate.cc
new file mode 100644
index 00000000000..26179f99694
--- /dev/null
+++ b/passes/techmap/clock_gate.cc
@@ -0,0 +1,62 @@
+#include "kernel/yosys.h"
+#include "kernel/ff.h"
+
+USING_YOSYS_NAMESPACE
+PRIVATE_NAMESPACE_BEGIN
+
+struct ClockgatePass : public Pass {
+	ClockgatePass() : Pass("clock_gate", "extract clock gating out of flip flops") { }
+	void help() override
+	{
+		// TODO
+	}
+
+	SigMap sigmap;
+	FfInitVals initvals;
+
+	void execute(std::vector<std::string> args, RTLIL::Design *design) override
+	{
+		log_header(design, "Executing CLOCK_GATE pass (extract clock gating out of flip flops).\n");
+
+        std::string pos_icg_cell;
+        std::string neg_icg_cell;
+		size_t argidx;
+		for (argidx = 1; argidx < args.size(); argidx++)
+		{
+			if (args[argidx] == "-pos" && argidx+1 < args.size()) {
+				pos_icg_cell = args[++argidx];
+			}
+			if (args[argidx] == "-neg" && argidx+1 < args.size()) {
+				neg_icg_cell = args[++argidx];
+			}
+			break;
+		}
+
+
+		extra_args(args, argidx, design);
+
+		for (auto module : design->selected_whole_modules()) {
+            sigmap.set(module);
+			initvals.set(&sigmap, module);
+            for (auto cell : module->cells()) {
+                if (!RTLIL::builtin_ff_cell_types().count(cell->type))
+                    continue;
+                FfData ff(&initvals, cell);
+                if (ff.has_ce) {
+
+                    // TODO do stuff
+                    
+
+                    bool ce_pol = ff.pol_ce;
+                    if (!ce_pol) {
+                        //TODO invert CE
+                    }
+                }
+            }
+        }
+
+    }
+} ClockgatePass;
+
+
+PRIVATE_NAMESPACE_END