cleanup: extra_args and argidx

YosysHQ · Apr 2, 2024 · b790d8e · b790d8e
1 parent b9d3bff
commit b790d8e
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Showing 39 changed files with 56 additions and 328 deletions.
diff --git a/passes/cmds/autoname.cc b/passes/cmds/autoname.cc
@@ -101,15 +101,7 @@ struct AutonamePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// if (args[argidx] == "-foo") {
-			// 	foo = true;
-			// 	continue;
-			// }
-			break;
-		}
+		extra_args(args, 1, design);
 
 		log_header(design, "Executing AUTONAME pass.\n");
 

diff --git a/passes/cmds/blackbox.cc b/passes/cmds/blackbox.cc
@@ -36,15 +36,7 @@ struct BlackboxPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// if (args[argidx] == "-???") {
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_whole_modules_warn(true))
 		{

diff --git a/passes/cmds/clean_zerowidth.cc b/passes/cmds/clean_zerowidth.cc
@@ -52,12 +52,7 @@ struct CleanZeroWidthPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		CellTypes ct;
 		ct.setup();

diff --git a/passes/cmds/edgetypes.cc b/passes/cmds/edgetypes.cc
@@ -37,15 +37,7 @@ struct EdgetypePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-ltr") {
-			// 	config.ltr = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		pool<string> edge_cache;
 

diff --git a/passes/cmds/future.cc b/passes/cmds/future.cc
@@ -122,14 +122,7 @@ struct FuturePass : public Pass {
 		FutureOptions options;
 
 		log_header(design, "Executing FUTURE pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-
-			break;
-		}
-
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules()) {
 			FutureWorker worker(module, options);

diff --git a/passes/cmds/printattrs.cc b/passes/cmds/printattrs.cc
@@ -50,8 +50,7 @@ struct PrintAttrsPass : public Pass {
 
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx = 1;
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		unsigned int indent = 0;
 		for (auto mod : design->selected_modules())

diff --git a/passes/cmds/select.cc b/passes/cmds/select.cc
@@ -1713,8 +1713,7 @@ struct LsPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx = 1;
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		if (design->selected_active_module.empty())
 		{

diff --git a/passes/cmds/setattr.cc b/passes/cmds/setattr.cc
@@ -140,17 +140,7 @@ struct WbflipPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			std::string arg = args[argidx];
-			// if (arg == "-mod") {
-			// 	flag_mod = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (Module *module : design->modules())
 		{

diff --git a/passes/cmds/sta.cc b/passes/cmds/sta.cc
@@ -289,16 +289,7 @@ struct StaPass : public Pass {
 	{
 		log_header(design, "Executing STA pass (static timing analysis).\n");
 
-		/*
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			if (args[argidx] == "-TODO") {
-				continue;
-			}
-			break;
-		}
-		*/
-
+		// TODO: there was a commented out -TODO argument
 		extra_args(args, 1, design);
 
 		for (Module *module : design->selected_modules())

diff --git a/passes/cmds/trace.cc b/passes/cmds/trace.cc
@@ -72,13 +72,7 @@ struct TracePass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// .. parse options ..
-			break;
-		}
-
+		size_t argidx = 1;
 		TraceMonitor monitor;
 		design->monitors.insert(&monitor);
 
@@ -107,12 +101,7 @@ struct DebugPass : public Pass {
 	}
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// .. parse options ..
-			break;
-		}
+		size_t argidx = 1;
 
 		log_force_debug++;
 

diff --git a/passes/equiv/equiv_mark.cc b/passes/equiv/equiv_mark.cc
@@ -219,15 +219,7 @@ struct EquivMarkPass : public Pass {
 	void execute(std::vector<std::string> args, Design *design) override
 	{
 		log_header(design, "Executing EQUIV_MARK pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-foobar") {
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_whole_modules_warn()) {
 			EquivMarkWorker worker(module);

diff --git a/passes/equiv/equiv_purge.cc b/passes/equiv/equiv_purge.cc
@@ -190,15 +190,7 @@ struct EquivPurgePass : public Pass {
 	void execute(std::vector<std::string> args, Design *design) override
 	{
 		log_header(design, "Executing EQUIV_PURGE pass.\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-foobar") {
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_whole_modules_warn()) {
 			EquivPurgeWorker worker(module);

diff --git a/passes/hierarchy/uniquify.cc b/passes/hierarchy/uniquify.cc
@@ -44,17 +44,7 @@ struct UniquifyPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing UNIQUIFY pass (creating unique copies of modules).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// if (args[argidx] == "-check") {
-			// 	flag_check = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		bool did_something = true;
 		int count = 0;

diff --git a/passes/memory/memory_bmux2rom.cc b/passes/memory/memory_bmux2rom.cc
@@ -38,12 +38,7 @@ struct MemoryBmux2RomPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules()) {
 			for (auto cell : module->selected_cells()) {

diff --git a/passes/memory/memory_narrow.cc b/passes/memory/memory_narrow.cc
@@ -38,12 +38,7 @@ struct MemoryNarrowPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing MEMORY_NARROW pass (splitting up wide memory ports).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules()) {
 			if (module->has_processes_warn())

diff --git a/passes/opt/muxpack.cc b/passes/opt/muxpack.cc
@@ -344,13 +344,7 @@ struct MuxpackPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing MUXPACK pass ($mux cell cascades to $pmux).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		int mux_count = 0;
 		int pmux_count = 0;

diff --git a/passes/opt/opt_demorgan.cc b/passes/opt/opt_demorgan.cc
@@ -182,9 +182,7 @@ struct OptDemorganPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing OPT_DEMORGAN pass (push inverters through $reduce_* cells).\n");
-
-		int argidx = 0;
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		unsigned int cells_changed = 0;
 		for (auto module : design->selected_modules())

diff --git a/passes/opt/opt_ffinv.cc b/passes/opt/opt_ffinv.cc
@@ -246,13 +246,7 @@ struct OptFfInvPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing OPT_FFINV pass (push inverters through FFs).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		int total_count = 0;
 		for (auto module : design->selected_modules())

diff --git a/passes/opt/opt_mem.cc b/passes/opt/opt_mem.cc
@@ -39,16 +39,7 @@ struct OptMemPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing OPT_MEM pass (optimize memories).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-nomux") {
-			// 	mode_nomux = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		int total_count = 0;
 		for (auto module : design->selected_modules()) {

diff --git a/passes/opt/opt_mem_widen.cc b/passes/opt/opt_mem_widen.cc
@@ -38,16 +38,7 @@ struct OptMemWidenPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++) {
-			// if (args[argidx] == "-nomux") {
-			// 	mode_nomux = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		int total_count = 0;
 		for (auto module : design->selected_modules()) {

diff --git a/passes/opt/rmports.cc b/passes/opt/rmports.cc
@@ -42,9 +42,7 @@ struct RmportsPassPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing RMPORTS pass (remove ports with no connections).\n");
-
-		size_t argidx = 1;
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		// The set of ports we removed
 		dict<IdString, pool<IdString>> removed_ports;

diff --git a/passes/pmgen/ice40_dsp.cc b/passes/pmgen/ice40_dsp.cc
@@ -299,17 +299,7 @@ struct Ice40DspPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing ICE40_DSP pass (map multipliers).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			// if (args[argidx] == "-singleton") {
-			// 	singleton_mode = true;
-			// 	continue;
-			// }
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules())
 			ice40_dsp_pm(module, module->selected_cells()).run_ice40_dsp(create_ice40_dsp);

diff --git a/passes/pmgen/peepopt.cc b/passes/pmgen/peepopt.cc
@@ -55,13 +55,7 @@ struct PeepoptPass : public Pass {
 	void execute(std::vector<std::string> args, RTLIL::Design *design) override
 	{
 		log_header(design, "Executing PEEPOPT pass (run peephole optimizers).\n");
-
-		size_t argidx;
-		for (argidx = 1; argidx < args.size(); argidx++)
-		{
-			break;
-		}
-		extra_args(args, argidx, design);
+		extra_args(args, 1, design);
 
 		for (auto module : design->selected_modules())
 		{