From b85062fcecf59040068c6503334bc4d2556262ff Mon Sep 17 00:00:00 2001
From: "Emil J. Tywoniak" <emil@tywoniak.eu>
Date: Wed, 5 Jun 2024 22:21:31 +0200
Subject: [PATCH] fix stuff, don't strip

---
 flake.nix       | 3 ++-
 kernel/rtlil.cc | 8 --------
 2 files changed, 2 insertions(+), 9 deletions(-)

diff --git a/flake.nix b/flake.nix
index b0194ce806f..b2761ace9aa 100644
--- a/flake.nix
+++ b/flake.nix
@@ -24,12 +24,13 @@
           preConfigure = "make config-clang";
           checkTarget = "test";
           installPhase = ''
-            make install PREFIX=$out ABCEXTERNAL=yosys-abc
+            make install PREFIX=$out ABCEXTERNAL=yosys-abc STRIP=\#
             ln -s ${abc-verifier}/bin/abc $out/bin/yosys-abc
           '';
 					buildPhase = ''
             make -j$(nproc) ABCEXTERNAL=yosys-abc
           '';
+          dontStrip = true;
           meta = with pkgs.lib; {
             description = "Yosys Open SYnthesis Suite";
             homepage = "https://yosyshq.net/yosys/";
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index a75fe35c3c2..51485e04cc6 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -928,7 +928,6 @@ RTLIL::Module::Module()
 	design = nullptr;
 	refcount_wires_ = 0;
 	refcount_cells_ = 0;
-	TracyAllocN(this, sizeof(RTLIL::Module), "module");
 
 #ifdef WITH_PYTHON
 	RTLIL::Module::get_all_modules()->insert(std::pair<unsigned int, RTLIL::Module*>(hashidx_, this));
@@ -947,7 +946,6 @@ RTLIL::Module::~Module()
 		delete pr.second;
 	for (auto binding : bindings_)
 		delete binding;
-	TracyFree(this);
 #ifdef WITH_PYTHON
 	RTLIL::Module::get_all_modules()->erase(hashidx_);
 #endif
@@ -3460,17 +3458,11 @@ RTLIL::Memory::Memory()
 #endif
 }
 
-RTLIL::Process::~Process()
-{
-	TracyFree(this);
-}
-
 RTLIL::Process::Process() : module(nullptr)
 {
 	static unsigned int hashidx_count = 123456789;
 	hashidx_count = mkhash_xorshift(hashidx_count);
 	hashidx_ = hashidx_count;
-	TracyAllocN(this, sizeof(RTLIL::Process), "process");
 }
 
 RTLIL::Cell::Cell() : module(nullptr)