diff --git a/docs/source/cell/index_word.rst b/docs/source/cell/index_word.rst
index cb81c69916b..409e20d2637 100644
--- a/docs/source/cell/index_word.rst
+++ b/docs/source/cell/index_word.rst
@@ -23,6 +23,7 @@ Simulation models for the RTL cells can be found in the file
    /cell/word_mem
    /cell/word_fsm
    /cell/word_arith
+   /cell/word_logic
    /cell/word_spec
    /cell/word_formal
    /cell/word_debug
diff --git a/docs/source/cell/word_arith.rst b/docs/source/cell/word_arith.rst
index eb1bfdada49..49070814add 100644
--- a/docs/source/cell/word_arith.rst
+++ b/docs/source/cell/word_arith.rst
@@ -3,9 +3,6 @@ Coarse arithmetics
 
 .. todo:: Add information about `$alu`, `$fa`, and `$lcu` cells.
 
-Multiply-accumulate
-~~~~~~~~~~~~~~~~~~~
-
 The `$macc` cell type represents a generalized multiply and accumulate
 operation. The cell is purely combinational. It outputs the result of summing up
 a sequence of products and other injected summands.
@@ -47,48 +44,6 @@ CONFIG parameter carries the following information:
 
 B is an array of concatenated 1-bit-wide unsigned integers to also be summed up.
 
-Arbitrary logic functions
-~~~~~~~~~~~~~~~~~~~~~~~~~
-
-The `$lut` cell type implements a single-output LUT (lookup table). It
-implements an arbitrary logic function with its ``\LUT`` parameter to map input
-port ``\A`` to values of ``\Y`` output port values. In psuedocode: ``Y =
-\LUT[A]``. ``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width
-of 1. Every logic function with a single bit output has a unique `$lut`
-representation.
-
-The `$sop` cell type implements a sum-of-products expression, also known as
-disjunctive normal form (DNF). It implements an arbitrary logic function. Its
-structure mimics a programmable logic array (PLA). Output port ``\Y`` is the sum
-of products of the bits of the input port ``\A`` as defined by parameter
-``\TABLE``. ``\A`` is ``\WIDTH`` bits wide. The number of products in the sum is
-set by parameter ``\DEPTH``, and each product has two bits for each input bit -
-for the presence of the unnegated and negated version of said input bit in the
-product. Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits.
-
-For example:
-
-Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``.
-There are 2 products to be summed, so ``\DEPTH`` shall be 2.
-
-.. code-block::
-
-    ~A[2]-----+
-     A[2]----+|
-    ~A[1]---+||
-     A[1]--+|||
-    ~A[0]-+||||
-     A[0]+||||| 
-         |||||| product formula
-         010000 ~\A[0]
-         001001 \A[1]~\A[2]
-
-So the value of ``\TABLE`` will become ``010000001001``.
-
-Any logic function with a single bit output can be represented with ``$sop`` but
-may have variously minimized or ordered summands represented in the ``\TABLE``
-values.
-
 .. autocellgroup:: arith
    :members:
    :source:
diff --git a/docs/source/cell/word_logic.rst b/docs/source/cell/word_logic.rst
new file mode 100644
index 00000000000..32945d560a0
--- /dev/null
+++ b/docs/source/cell/word_logic.rst
@@ -0,0 +1,46 @@
+Arbitrary logic functions
+-------------------------
+
+The `$lut` cell type implements a single-output LUT (lookup table). It
+implements an arbitrary logic function with its ``\LUT`` parameter to map input
+port ``\A`` to values of ``\Y`` output port values. In psuedocode: ``Y =
+\LUT[A]``. ``\A`` has width set by parameter ``\WIDTH`` and ``\Y`` has a width
+of 1. Every logic function with a single bit output has a unique `$lut`
+representation.
+
+The `$sop` cell type implements a sum-of-products expression, also known as
+disjunctive normal form (DNF). It implements an arbitrary logic function. Its
+structure mimics a programmable logic array (PLA). Output port ``\Y`` is the sum
+of products of the bits of the input port ``\A`` as defined by parameter
+``\TABLE``. ``\A`` is ``\WIDTH`` bits wide. The number of products in the sum is
+set by parameter ``\DEPTH``, and each product has two bits for each input bit -
+for the presence of the unnegated and negated version of said input bit in the
+product. Therefore the ``\TABLE`` parameter holds ``2 * \WIDTH * \DEPTH`` bits.
+
+For example:
+
+Let ``\WIDTH`` be 3. We would like to represent ``\Y =~\A[0] + \A[1]~\A[2]``.
+There are 2 products to be summed, so ``\DEPTH`` shall be 2.
+
+.. code-block::
+
+    ~A[2]-----+
+     A[2]----+|
+    ~A[1]---+||
+     A[1]--+|||
+    ~A[0]-+||||
+     A[0]+||||| 
+         |||||| product formula
+         010000 ~\A[0]
+         001001 \A[1]~\A[2]
+
+So the value of ``\TABLE`` will become ``010000001001``.
+
+Any logic function with a single bit output can be represented with ``$sop`` but
+may have variously minimized or ordered summands represented in the ``\TABLE``
+values.
+
+.. autocellgroup:: logic
+   :members:
+   :source:
+   :linenos:
\ No newline at end of file