From c35dd4ab42907d68e61b0f2abe7f4ccc5cd6a3a2 Mon Sep 17 00:00:00 2001
From: Claire Xenia Wolf <claire@clairexen.net>
Date: Mon, 22 Jul 2024 17:39:27 +0200
Subject: [PATCH] Updates

Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
---
 kernel/rtlil.h | 35 +++++++++++++++++++++++++++--------
 1 file changed, 27 insertions(+), 8 deletions(-)

diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index 584725288a7..d4994fdbef0 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -75,10 +75,17 @@ namespace RTLIL
 	struct Binding;
 
 #ifdef _YOSYS_VAY_
-	struct CoarseCell;   // same as Cell in a NOVAY build
-	struct FineCell;     // only single-bit ports and no parameters
-	struct AYFineCell;   // cell with single-bit ports "A" and "Y" and no parameters
-	struct ABYFineCell;  // cell with single-bit ports "A", "B", and "Y" and no parameters
+	struct CoarseDynamicCelll;     // same as Cell in a NOVAY build
+	struct FineDynamicCell;        // only single-bit ports and no parameters
+
+	// maybe instead:
+	//   #define X(classname) struct classname;
+	//   #include "kernel/dyncells.xh"
+	//   #uindef X
+	struct CoarseStaticCell_AwYw;  // cell with multi-bit "A" and "B" ports "A_WIDTH" and "Y_WIDTH" parameters
+	struct CoarseStaticCell_wABSY; // cell with multi-bit "A", "B", and "S" ports and "WIDTH" parameters
+	struct FineStaticCell_AY;      // cell with single-bit ports "A" and "Y" and no parameters
+	struct FineStaticCell_ABY;     // cell with single-bit ports "A", "B", and "Y" and no parameters
 	// ...
 #endif
 
@@ -1600,7 +1607,7 @@ struct RTLIL::Cell : public RTLIL::AttrObject
 		std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const = 0;
 };
 
-struct RTLIL::CoarseCell final : public RTLIL::Cell
+struct RTLIL::CoarseDynamicCelll final : public RTLIL::Cell
 {
 #endif
 	unsigned int hashidx_;
@@ -1651,8 +1658,9 @@ struct RTLIL::CoarseCell final : public RTLIL::Cell
 		std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const;
 };
 
+// maybe this will be #include "kernel/dyncells.h", generated by "kernel/dyncells.py"
 #ifdef _YOSYS_VAY_
-struct RTLIL::FineCell final : public RTLIL::Cell
+struct RTLIL::FineDynamicCell final : public RTLIL::Cell
 {
 	dict<RTLIL::IdString, RTLIL::SigBit> connections_;
 
@@ -1663,7 +1671,7 @@ struct RTLIL::FineCell final : public RTLIL::Cell
 		std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const;
 };
 
-struct RTLIL::AYFineCell final : public RTLIL::Cell
+struct RTLIL::FineStaticCell_AY final : public RTLIL::Cell
 {
 	SigBit portA_, portY_;
 
@@ -1682,7 +1690,7 @@ struct RTLIL::AYFineCell final : public RTLIL::Cell
 		std::vector<std::pair<int,std::vector<RTLIL::IdString>>> *allocsPtr = nullptr) const;
 };
 
-struct RTLIL::ABYFineCell final : public RTLIL::Cell
+struct RTLIL::FineStaticCell_ABY final : public RTLIL::Cell
 {
 	SigBit portA_, portB_, portY_;
 
@@ -1703,6 +1711,17 @@ struct RTLIL::ABYFineCell final : public RTLIL::Cell
 };
 
 //...
+#else // _YOSYS_VAY_
+
+struct RTLIL::CoarseDynamicCell final : public RTLIL::Cell {};
+struct RTLIL::FineDynamicCell final : public RTLIL::Cell {};
+
+struct RTLIL::CoarseStaticCell_AwYw final : public RTLIL::Cell {};
+struct RTLIL::CoarseStaticCell_wABSY final : public RTLIL::Cell {};
+
+struct RTLIL::FineStaticCell_AY final : public RTLIL::Cell {};
+struct RTLIL::FineStaticCell_ABY final : public RTLIL::Cell {};
+
 #endif
 
 struct RTLIL::CaseRule : public RTLIL::AttrObject