diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 7099c18c349..735672a43b4 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -2008,6 +2008,11 @@ void dump_proc_switch(std::ostream &f, std::string indent, RTLIL::SwitchRule *sw
 		dump_case_body(f, indent + "    ", *it);
 	}
 
+	if (sw->cases.empty()) {
+		// Verilog does not allow empty cases.
+		f << stringf("%s  default: ;\n", indent.c_str());
+	}
+
 	f << stringf("%s" "endcase\n", indent.c_str());
 }